KR101560394B1 - Liquid crystal display and driving method thereof - Google Patents

Abstract

According to the present invention, by sequentially supplying a first gate voltage of a high level, a third gate voltage of a low level, and a high level to a gate line and a second gate voltage lower than the first gate voltage, the kickback voltage is minimized, Can be improved.

Liquid crystal display, gate voltage, kickback voltage, level shifter, gate shift clock

Description

[0001] The present invention relates to a liquid crystal display device and a driving method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving image quality and a driving method thereof.

Due to the development of the information society, display devices capable of displaying information are actively being developed. The display device includes a liquid crystal display device, an organic electro-luminescence display device, a plasma display panel, and a field emission display device.

Of these, liquid crystal display devices have advantages such as light weight, low power consumption, and full color video implementation, and are widely applied to mobile phones, navigation, monitors, and televisions.

The liquid crystal display displays an image corresponding to a video signal by adjusting the light transmittance of the liquid crystal cells on the liquid crystal panel.

1 is a view showing a liquid crystal panel of a conventional liquid crystal display device. For convenience of explanation, FIG. 1 shows one pixel region among a plurality of pixel regions defined in a liquid crystal panel.

The liquid crystal panel includes a first substrate, a second substrate, and a liquid crystal layer disposed between the substrates.

The first substrate is defined by a gate line GL and a data line DL, as shown in Fig.

A thin film transistor (TFT) is electrically connected to the gate line GL and the data line DL. A pixel electrode not shown is electrically connected to the thin film transistor TFT. A storage capacitance Cst is formed by the pixel electrode and the gate line at the previous stage. The liquid crystal capacitance Clc is formed in the liquid crystal layer disposed between the pixel electrode and the common electrode Vcom formed on the second substrate.

As shown in FIG. 2, a gate high voltage VGH and a gate low voltage VGL are supplied to the gate line GL. The thin film transistor TFT is turned on by the gate high voltage VGH and the data voltage Vd supplied to the data line DL is charged to the storage capacitance Cst via the pixel electrode.

The gate high voltage VGH is supplied to the gate line GL for one horizontal period 1H and the gate low voltage VGL is supplied after one horizontal substrate 1H.

In this case, when the gate high voltage VGH supplied to the gate line GL is transferred to the gate low voltage VGL, the thin film transistor TFT is turned off, The data voltage Vd charged to the electrode is lowered by the kickback voltage Vp by the parasitic capacitance Cgs generated between the gate electrode and the source electrode of the thin film transistor TFT. This kickback voltage is heavily influenced by the magnitude of the potential difference between the gate high voltage (VGH) and the gate low voltage (VGL). Therefore, reducing the magnitude of the potential difference between the gate high voltage VGH and the gate low voltage VGL is necessary to reduce the kickback voltage Vp.

In the conventional liquid crystal display device, flicker and afterimage are generated in the image displayed on the liquid crystal panel due to the kickback voltage (Vp), resulting in a problem that the image quality is deteriorated.

An object of the present invention is to provide a liquid crystal display device capable of minimizing a kickback voltage and improving picture quality by supplying a second gate high voltage lower than a first gate high voltage and supplying the same.

According to a first embodiment of the present invention, a liquid crystal display device includes: a liquid crystal panel; A gate driver for supplying first and second gate voltages having a high level in units of one horizontal period to the liquid crystal panel; And a data driver for supplying a data voltage to the liquid crystal panel, wherein the second gate voltage may be at least lower than the first gate voltage.

According to a second aspect of the present invention, there is provided a method of driving a liquid crystal display, comprising: supplying a first and second gate voltages having a high level in units of a horizontal period to a liquid crystal panel; And supplying a data voltage to the liquid crystal panel, wherein the second gate voltage may be at least lower than the first gate voltage.

The present invention can improve the image quality by minimizing the kickback voltage by supplying the gate line with a second gate voltage lower than the first gate voltage.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram showing a liquid crystal display device according to the present invention.

3, the liquid crystal display includes a liquid crystal panel 50, a gate voltage generator 20, a gate driver 30, a data driver 40, and a timing controller 10.

The liquid crystal panel 50 includes a first substrate, a second substrate, and a liquid crystal layer disposed between the first and second substrates.

The first substrate includes a plurality of gate lines GL0 to GLn and a plurality of data lines DL1 to DLm. Pixel regions can be defined by the intersection of each gate line GL0 to GLn and each data line DL1 to DLm.

A thin film transistor (TFT) is connected to each of the gate lines GL0 to GLn and each of the data lines DL1 to DLm and a pixel electrode is connected to the thin film transistor TFT. The thin film transistor (TFT) and the pixel electrode may be disposed in respective pixel regions. The storage capacitance Cst is formed by overlapping the pixel electrode and the previous gate line. A liquid crystal capacitance (Clc) is formed by the liquid crystal layer between the pixel electrode and the common electrode to be described later.

The second substrate is provided with a color filter layer corresponding to each pixel region of the first substrate, the color filter layer including a red color filter, a green color filter, and a blue color filter, a black matrix disposed between each color filter, And a common electrode may be disposed on the black matrix.

The timing controller 10 generates control signals for controlling the gate driver 30 and the data driver 40. That is, the timing controller 10 controls the gate driver 30 such that a gate start pulse GSP, a first gate shift clock GSC1, a second gate shift clock GSC2, a gate out enable GOE ), A level shifter control signal (LSC), and the like to generate a source start pulse (SSP), a source shift clock (SSC), a source out enable (SOE), a POL do.

In this embodiment, the gate start pulse GSP generated to control the gate driver 30, the first gate shift clock GSC1, the second gate shift clock GSC2, the gate out enable GOE, The gate driver 30 generates a first gate voltage VGH1 and a second gate voltage VGH2 that is supplied separately from the first gate voltage VGH1 by the level shifter control signal LSC, To the respective gate lines GL0 to GLn of the gate driver 50. [

The gate voltage generating unit 20 generates first to third gate voltages VGH1, VGH2, and VGL and supplies the generated gate voltages to the gate driver 30.

The first gate voltage VGH1 is a voltage having a high level and is a voltage capable of sufficiently activating each gate line GL0 to GLn of the liquid crystal panel 50. [

The second gate voltage VGH2 is a voltage having a high level lower than the first gate voltage VGH1 and is a voltage capable of activating at least each of the gate lines GL0 to GLn of the liquid crystal panel 50. [ The second gate voltage VGH2 may be lowered to 40% to 90% of the first gate voltage VGH1.

The third gate voltage VGL is a voltage having a low level and is a voltage that can inactivate each of the gate lines GL0 to GLn of the liquid crystal panel 50. [

The first to third gate voltages VGH1, VGH2 and VGL generated by the gate voltage generator 20 are supplied to the gate driver 30 and the gate driver 30 supplies the first, 3 gate voltages VGH1, VGH2, and VGL may be selectively supplied to the gate lines of the liquid crystal panel 50. [

The gate driver 30 includes a shift register 32, an AND gate 34, and a level shifter 36, as shown in FIG. The gate driver 30 may further include a buffer unit (not shown) for buffering the output of the level shifter 36.

The shift register 32 is controlled by the gate start pulse GSP and the first gate shift clock GSC1 to sequentially output the output signal Sout.

As shown in Fig. 6, the gate start pulse GSP has a high level only for one horizontal period (1H) in one frame, and has a low level otherwise. That is, the gate start pulse GSP can have a high level only for one horizontal period (1H) at the beginning of each frame.

The first gate shift clock GSC1 divides one horizontal period (1H) into first and second sections, has a high level for a first section, and has a low level for a second section. The first and second sections may have the same width. The first gate shift clock GSC1 repeatedly has a high level and a low level in units of one horizontal period (1H).

Therefore, the gate start pulse GSP is output to the output signal Sout by the first gate shift clock GSC1.

The shift register 32 can output output signals as many as the number of gate lines of the liquid crystal panel 50.

The AND operation unit 34 performs an AND operation on the output signal Sout, the gate-out enable signal GOE and the second gate shift clock signal GSC2 output from the shift register 32 to generate an output signal ORout Output.

As shown in FIG. 5, the AND gate 34 may be the AND gate 38.

As shown in Fig. 6, the output signal Sout may have the same high barrel width as the gate start pulse GSP.

The gate-out enable (GOE) has a high level for one horizontal period (1H) and a low level for a certain period of the end of one horizontal period (1H). That is, the gate-out enable (GOE) may have a low level with a very narrow width in some section between one horizontal section (1H).

The second gate shift clock GSC2 is supplied with a first high level signal having a high level for at least 1/2 of one horizontal period 1H and a second high level signal having a low level for at least one tenth of a horizontal period 1H Level signal having a high level for at least 1/4 of the first horizontal interval (1H) and a second high-level signal having a high level for at least 1/100 or less of the first horizontal interval (1H) Level signal having a low level during a period of < RTI ID = 0.0 > a < / RTI >

The AND gate 38 outputs the output signal ORout having the high level by the first high level signal, the gate out enable signal GOE and the output signal Sout of the second gate shift clock GSC2 The output signal ORout having a low level is output by the first low level signal, the gate out enable signal GOE and the output signal Sout of the second gate shift clock GSC2, and the second gate shift clock An output signal ORout having a high level is output by the second high level signal of the first gate shift clock signal GSC2, the gate output enable signal GOE and the output signal Sout of the second gate shift clock GSC2, The output signal ORout having the low level is outputted by the signal, the gate output enable signal GOE and the output signal Sout.

Therefore, the output signal ORout output from the AND gate 38 is the same signal as the second gate shift clock GSC2.

The level shifter 36 divides the gate voltage corresponding to the output signal ORout output from the AND gate 34 by the level shifter control signal LSC into the first to third gate voltages VGH1, VGH2, VGL).

The first to third gate voltages VGH1, VGH2 and VGL are generated by the gate voltage generator 20 and supplied to the level shifter 36 of the gate driver 30. [

The level shifter 36 is supplied with the level shifter control signal LSC from the timing controller 10. The level shifter control signal LSC may be a control signal for matching the output signal ORout output from the AND gate 34 with the first and second gate voltages VGH1, VGH2 and VGL.

The level shifter control signal LSC may be a binary bit. Accordingly, the level shifter control signal LSC may be supplied to the level shifter 36 in the order of '00', '01', '10', and '11'.

When the level shifter control signal LSC is '00', the first gate voltage VGH1 corresponding to the output signal ORout of the first high level signal output from the AND gate 34 is input to the level shifter 36.

When the level shifter control signal LSC is '01', the third gate voltage VGL corresponding to the output signal ORout of the first low level signal outputted from the AND gate 34 is inputted to the level shifter 36.

When the level shifter control signal LSC is '10', the second gate voltage VGH2 corresponding to the output signal ORout of the second high level signal outputted from the AND gate 34 is supplied to the level shifter 34. [ (36).

When the level shifter control signal LSC is '11', the third gate voltage VGL corresponding to the output signal ORout of the second low level signal output from the AND gate 34 is supplied to the level shifter (36).

Therefore, the gate driver 30 supplies the first and second gate voltages VGH1 and VGH2 to the gate lines GL0 to GLn of the liquid crystal panel 50, respectively. A third gate voltage VGL may be applied between the first and second gate voltages VGH1 and VGH2.

The data driver 40 supplies the data voltage to the liquid crystal panel 50 according to the control signals supplied from the timing controller 10. [

7, first and second gate voltages VGH1 and VGH2 are generated in the gate driver 30 during one horizontal period (1H), and the first and second gate voltages VGH1 and VGH2 are applied to the gate line of the liquid crystal panel 50 . A third gate voltage VGL may be supplied between the first and second gate voltages VGH1 and VGH2. The first and second gate voltages VGH1 and VGH2 may have a high level and the third gate voltage VGL may have a low level. The second gate voltage VGH2 may be lowered in a range of 40% to 90% of the first gate voltage VGH1.

First, the thin film transistor connected to the gate line of the liquid crystal panel 50 is turned on by the first gate voltage VGH1. Accordingly, the data voltage Vd is supplied from the data driver 40 to the data line of the liquid crystal panel 50. The data voltage Vd is applied to the pixel electrode via the thin film transistor connected to the data line. Since the storage capacitance Cst is formed in the pixel electrode, the data voltage applied to the pixel electrode is gradually charged into the storage capacitance Cst.

The third gate voltage VGL is supplied to the gate line of the liquid crystal panel 50 after the first gate voltage VGH1. Since the third gate voltage VGL is low level, the thin film transistor connected to the gate line is turned off. In this case, when transitioning from the high level of the first gate voltage VGH1 to the low level of the third gate voltage VGL, a primary kickback voltage may be generated. Since the width of the third gate voltage VGL is very small, the kickback voltage is not large. The voltage charged in the pixel electrode by the kickback voltage is reduced.

The second gate voltage VGH2 is supplied to the gate line of the liquid crystal panel 50 after the third gate voltage VGL. Thus, the thin film transistor connected to the gate line is turned on again by the second gate voltage VGH2 having a high level. As a result, the data voltage Vd supplied to the data line is applied again to the pixel electrode via the thin film transistor, so that the voltage of the pixel electrode is increased again. Therefore, the voltage of the pixel electrode can be completely charged to the data voltage Vd.

The third gate voltage VGL is supplied to the gate line of the liquid crystal panel 50 after the second gate voltage VGH2. Thus, the thin film transistor connected to the gate line is turned off.

The second gate voltage VGH2 has a voltage relatively lower than the first gate voltage VGH1 so that the transition from the second gate voltage VGH2 to the third gate voltage VGL occurs, The kickback voltage (? Vp) becomes very small.

Therefore, in this embodiment, the second gate voltage, which is lower than the first gate voltage, is supplied to the gate line so as to minimize the kickback voltage, thereby improving the image quality.

1 is a view showing a liquid crystal panel of a conventional liquid crystal display device.

2 is a diagram showing generation of a kickback voltage in a conventional liquid crystal display device.

3 is a block diagram showing a liquid crystal display device according to the present invention.

4 is a block diagram illustrating the gate driver of Fig.

Figure 5 shows the AND gate of Figure 4;

Fig. 6 is a signal waveform diagram of the liquid crystal display device of Fig. 3; Fig.

7 is a diagram showing the generation of a kickback voltage in the liquid crystal display device of the present invention.

Description of the Related Art

10: timing controller 20: gate voltage generator

30: gate driver 32: shift register

34: AND operation unit 36: level shifter

38: AND gate 40: data driver

50: liquid crystal panel

Claims (13)

A liquid crystal panel driven by a frame unit and including a gate line; A gate driver for generating first to fourth gate voltages for supplying to the gate line during one horizontal period of the frame; And And a data driver for supplying a data voltage to the liquid crystal panel, The first horizontal period includes first to fourth intervals, The first gate voltage is supplied during the first period, the second gate voltage is supplied during the second period, the third gate voltage is supplied during the third period, and the fourth gate voltage is supplied during the fourth period, A gate voltage is supplied, The first and third gate voltages have a high level, the second and fourth gate voltages have a low level, The low level of the second gate voltage and the low level of the fourth gate voltage are the same, The low level of the second gate voltage maintains the same voltage for a certain period, Wherein the first gate voltage has at least a half or more of the width of the one horizontal period and the second gate voltage has a width of at least 1/4 of the one horizontal period, And a width of at least 1/10 of the period. delete The method according to claim 1, And a high level of the first gate voltage is transited vertically to a low level of the second gate voltage at a start point of the second section. The method according to claim 1, And a low level of the second gate voltage is vertically transited to a high level of the third gate voltage at an end point of the second section. The method according to claim 1, And the second gate voltage is a voltage for deactivating the gate line. The method according to claim 1, The gate driver includes: A shift register for sequentially outputting the first output signal of the one horizontal period by a gate start pulse and a first gate shift clock; A logical product operation unit for performing a logical product of the first output signal, the gate out enable signal, and the second gate shift clock of the shift register to output a second output signal having the same waveform as the second gate shift clock; And And a level shifter for selecting and outputting a gate voltage corresponding to the second output signal from among the first to fourth gate voltages according to a level shifter control signal. The method according to claim 6, The first or third gate voltage is selected corresponding to a high level of the second output signal and the second or fourth gate voltage is selected corresponding to a low level of the second output signal. The method according to claim 1, And the high-level width of the third gate voltage is smaller than the high-level width of the first gate voltage. The method according to claim 1, And the high level of the third gate voltage is located between the high level of the first gate voltage and the low level of the second gate voltage. The method according to claim 1, Wherein a high level of the third gate voltage is in a range of 40% to 90% of a high level of the first gate voltage. delete delete delete

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