KR20080062875A - LCD Display - Google Patents

Abstract

A liquid crystal display device capable of improving afterimage phenomenon is disclosed.

The liquid crystal display device is configured to drive a liquid crystal panel having first to m-th gate lines and first to m-th gate lines, and includes a gate driver including N gate integrated circuits, where N is a natural number of two or more. Include. The gate driver discharges the first to mth gate lines by simultaneously driving N gate integrated circuits when power is cut off.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

1 is an equivalent view of a conventional unit pixel region.

2 is a view showing a liquid crystal display device according to the present invention.

3 illustrates a gate driver according to an embodiment of the present invention.

4 is a timing diagram showing the operation of the gate driver at the time of power down according to the embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

2: liquid crystal panel 4: data driver

6: gate driver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and to a liquid crystal display device capable of improving an afterimage phenomenon.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate line GL and the data line DL cross each other as illustrated in FIG. 1. The pixel region is defined at the intersection of the gate line GL and the data line DL.

In the pixel region, a thin film transistor (TFT) for selecting each pixel and a pixel electrode connected to the thin film transistor for supplying a data signal to each pixel are formed.

Accordingly, each pixel is selected by switching control of the thin film transistor, and the arrangement of liquid crystal molecules is generated by an electric field generated by a data signal applied to the pixel electrode of each selected pixel and a common voltage supplied to a common electrode (not shown). Controlled. Accordingly, the light transmittance is adjusted so that an image is displayed.

The LCD needs to turn on the main power to display the image. In order not to display an image, the main power must be turned off.

However, since the liquid crystal panel has various kinds of capacitor components, even when the main power is turned off, the voltage charged in the capacitor is present as an organic voltage when the liquid crystal panel is driven, resulting in an afterimage phenomenon. .

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of improving afterimage phenomenon.

Another object of the present invention is to provide a liquid crystal display device capable of quickly removing an afterimage.

In order to achieve the above object, the liquid crystal display device according to the present invention, the first to m-th gate line formed liquid crystal panel; And a gate driver for driving the first to m-th gate lines, the gate driver including N gate integrated circuits (N being a natural number of 2 or more), wherein the gate driver includes the N gates when power is cut off. The first to m-th gate lines are discharged by simultaneously driving an integrated circuit.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 4.

2 is a view showing a liquid crystal display device according to the present invention.

A liquid crystal panel 2 in which liquid crystal cells are arranged in a matrix form, a gate driver 6 for driving gate lines GL1 to GLn of the liquid crystal panel 2, and data lines of the liquid crystal panel 2 ( A data driver 4 for driving the DL1 to DLm, and a timing controller 8 for controlling the gate driver 6 and the data driver 4 are provided.

The liquid crystal panel 2 includes a thin film transistor TFT formed at each intersection of the gate lines GL1 to GLn and the data lines DL1 to DLm, and a liquid crystal cell 7 connected to the thin film transistor TFT. do. The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell 7. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell 7.

The liquid crystal cell 7 is equivalently represented by a liquid crystal capacitor, and includes a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell 7 further includes a storage capacitor so that the charged pixel signal is stably maintained until the next pixel signal is charged. This storage capacitor is formed between the pixel electrode and the previous gate line. The liquid crystal cell 7 realizes gradation by adjusting light transmittance by varying an arrangement state of liquid crystals having dielectric anisotropy according to pixel signals charged through the thin film transistor TFT.

The timing controller 8 uses the synchronization signals V and H supplied from a video card (not shown) to control the gate control signals GSP1, GSP2, GSC, and GOE and the data control signals SSP, SSC, SOE, and POL. Will occur). The gate control signals GSP1, GSP2, GSC and GOE are supplied to the gate driver 6 to control the gate driver, and the data control signals SSP, SSC, SOE, and POL are supplied to the data driver 4. Control the data driver.

In particular, the timing controller 8 generates a second gate start pulse GSP2 for operating each gate driver integrated circuit at the same time when the power is turned off.

In addition, the timing controller 8 aligns the red (R), green (G), and blue (B) pixel data VD and supplies them to the data driver 4.

The gate driver 6 sequentially drives the gate lines GL1 to GLn. To this end, the gate driver 6 includes a plurality of gate integrated circuits (hereinafter referred to as " ICs "). The first to third gate ICs 10 drive the gate lines GL1 to GLn connected thereto.

For example, if the gate line is formed of 800 lines, the first gate IC 10a drives the first to second 67 gate lines GL1 to GL267 by a control signal.

The second gate IC 10b drives the 268 th through 534 th gate lines GL268 through GL534, and the third gate IC 10c drives the 535 th through 800 th gate lines GL535 through GL800.

The data driver 4 supplies the pixel signals for one line to the data lines DL1 to DLm every horizontal period. For this purpose, the data driver 4 has a plurality of data ICs. The data ICs supply pixel signals to the data lines DL1 to DLm in response to the data control signals SSP, SSC, SOE, and POL supplied from the timing controller 8.

Specifically, the data ICs shift the source start pulse SSP according to the source shift clock SSC to generate a sampling signal. Subsequently, the data ICs sequentially latch the pixel data VD in predetermined units in response to the sampling signal. Thereafter, the latched one-line pixel data VD is converted into an analog pixel signal and supplied to the data lines DL1 to DLm in an enable period of the source output enable signal SOE. In this case, the data ICs 16 convert the pixel data VD into a positive or negative pixel signal in response to the polarity control signal POL.

The operation of the gate driver when the power is applied and when the power is cut off in the liquid crystal display is as follows.

In the driving process of displaying an image on the display panel by applying power to the liquid crystal display, the first to third gate ICs 10 are applied to the gate control signals GSP1, GSC, and GOE supplied from the timing controller 8. In response, the gate high voltage VGH is sequentially supplied to the gate lines GL1 to GLm.

Specifically, the gate driver 6 shifts the gate start pulse GSP1 according to the gate shift clock GSC to generate a shift pulse. The gate driver 6 supplies the gate high voltage VGH to the corresponding gate line GL every horizontal period in response to the shift pulse. In other words, the shift pulse is shifted by one line for each horizontal period, and one of the gate ICs 10 supplies the gate high voltage VGH to the corresponding gate line GL in correspondence with the shift pulse. In this case, the gate ICs 10 supply the gate low voltage VGL in the remaining period in which the gate high voltage VGH is not supplied to the gate lines GL1 through GLn.

The operation of the liquid crystal display when the power is cut off is as follows.

The timing controller 8 applies a low voltage to the gate driver 6 as the second gate start pulse GSP2 when the power of the liquid crystal display is turned off. The second gate start pulse GSP2 is applied to the gate driver 6 as a control signal having a low voltage when the power is turned off while maintaining a high voltage in a normal driving state.

The second gate staff pulse GSP2 is simultaneously supplied to the first to third gate ICs 10a, 10b, and 10c provided in the gate driver 6.

Accordingly, the first to third gate ICs 10a, 10b, and 10c may be individually driven by the second gate start pulse GSP2.

That is, the first gate IC 10a sequentially drives the first to second gate lines GL1 to GL267.

The second gate IC 10a sequentially drives the 268 th through 534 th gate lines GL268 through GL534 simultaneously with the first gate IC 10a.

In addition, the third gate IC 10c sequentially drives the 535 to 800 gate lines GL535 to GL800 simultaneously with the first and second gate ICs 10a and 10b.

This operation is described below with reference to the timing diagram of FIG. 4.

The first and second periods t1 to t267 are periods in which the gate shift clock GSC is applied, respectively, and are set to a time of 1 ms.

At the time t0 when the power is turned off, the second gate shift pulse GSP2 is applied to the gate driver 6 as a signal having a low voltage.

In the first period t1, the second gate start pulse GSP2 is simultaneously supplied to the first to third gate ICs 10a, 10b, and 10c.

As a result, gate high voltages are sequentially generated from the respective gate ICs 10a, 10b, and 10c, and are supplied to the gate lines of the liquid crystal panel 2.

For example, the first gate IC 10a may be electrically connected to the first gate lines GL1 to 267 (GL267) of the liquid crystal panel 2. Accordingly, the gate high voltage sequentially generated by the first gate IC 10 may be supplied to the first gate lines GL1 to 267 (GL267) of the liquid crystal panel 2.

The second gate IC 10b may be electrically connected to the 268th gate lines GL268 to 534 gate lines GL534 of the liquid crystal panel 2. Accordingly, the gate high voltage sequentially generated by the second gate IC 10b may be supplied to the 268th gate lines GL268 to 534 gate lines GL534 of the liquid crystal panel 2.

The third gate IC 10c may be electrically connected to the 535th gate lines GL535 to 800th gate lines GL800 of the liquid crystal panel 2. Accordingly, the gate high voltage sequentially generated by the third gate IC 10c may be supplied to the 535 th gate lines GL535 to 800 th gate lines GL800 of the liquid crystal panel 2.

The first to third gate ICs 10a, 10b, and 10c are simultaneously driven by the gate shift pulse GSP2 having the low level, so that the first to third gate ICs 10a, 10b, and 10c are respectively driven from the first to third gate ICs 10a, 10b, and 10c. The gate high voltage may be generated sequentially.

Therefore, the time required for discharging all the gate lines GL1 to GL800 of the liquid crystal panel 2 by each gate IC 10a, 10b, and 10c is the sum of the first period t1 to the second period t267. Therefore, when one section is 1㎲, the total becomes 267㎲.

When the power is turned off, all the gate lines are driven in this manner to quickly discharge the pixels charged in the panel, thereby solving the problem of afterimages on the display surface.

In addition, the present invention is 267 ms compared to 800 ms, which is a time taken to sequentially discharge all the gate lines, and the discharge time may be shortened to 1/3 compared to the conventional art.

Accordingly, the liquid crystal display according to the present invention can secure sufficient time to operate all the gate lines through the discharge of the voltage charged in the passive elements such as the timing controller and the voltage source.

As described above, according to the liquid crystal display according to the present invention, when the power is cut off, afterimages may be improved on the screen. In particular, by simultaneously driving a plurality of gate integrated circuits, it is possible to secure a sufficient time margin to operate all the gate lines with the voltage discharged after the power is turned off.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (5)

A liquid crystal panel in which first to m-th gate lines are formed; A gate driver for driving the first to mth gate lines, the gate driver including N (N is a natural number of two or more) gate integrated circuits, And the gate driver discharges the first to m th gate lines by simultaneously driving the N gate integrated circuits when power is cut off. The method of claim 1, And each of the N gate driver integrated circuits drives m / N gate lines. The method of claim 1, And a timing controller configured to generate a control signal for simultaneously driving the N-th gate driver integrated circuits when the power is cut off. The method of claim 3, wherein And the control signal is a gate shift pulse. The liquid crystal display of claim 4, wherein the gate shift pulse has a low level.

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