KR20100042359A - Display apparatus - Google Patents

Abstract

The display device includes a display panel, a gate driver, a data driver, a power supply, a pre-driving unit, and a storage driver. The display panel includes a plurality of pixels for displaying an image, and each pixel includes a storage line electrically connected to the gate line and the data line and arranged in parallel with the gate line. The gate driver outputs a gate signal to the gate line, and the data driver outputs a data voltage to the data line. The power supply unit generates a first sustain signal and a first inverted sustain signal in which phases are inverted in the first sustain signal. The pre-driving unit pre-drives the first sustain signal and the first inverted sustain signal using an external voltage to generate a second sustain signal and a second inverted sustain signal. The storage driver outputs a storage signal having a phase inverted for each frame to the storage line using the second sustain signal and the second sustain inverted signal. Accordingly, by pre-driving by the pre-driving unit, power consumption can be reduced and response speed can be improved.

Description

Display device {DISPLAY APPARATUS}

The present invention relates to a display device, and more particularly, to a display device for reducing power consumption.

In general, the liquid crystal display includes an array substrate on which pixel electrodes are formed, an opposing substrate on which a common electrode is formed, and a liquid crystal layer having an anisotropic dielectric constant interposed between the two substrates. Such a liquid crystal display is a flat panel display that displays an image by artificially forming an electric field between two substrates and adjusting a light transmittance of the liquid crystal depending on the intensity of the electric field.

Such liquid crystal displays are widely used in various applications such as notebook computers, monitors, and the like based on the advantages of slim design, low power consumption, and high resolution. In recent years, mobile devices have attracted attention, and the liquid crystal display devices used in these portable devices are required not only to display information but also to be able to faithfully display pictures, videos, broadcasts, and the like.

However, as the liquid crystal display device becomes higher resolution, the increase in power consumption becomes a problem, and the fast response speed required for displaying a moving image becomes a problem.

Accordingly, an object of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display device for reducing power consumption.

In order to achieve the above object, a display device according to an exemplary embodiment of the present invention includes a display panel, a gate driver, a data driver, a power supply, and a storage driver. The display panel includes a plurality of pixels for displaying an image, and each pixel includes a storage line electrically connected to a gate line and a data line and arranged in parallel with the gate line. The gate driver outputs a gate signal to the gate line. The data driver outputs a data voltage to the data line. The power supply unit generates a first inversion sustain signal in which a phase is inverted in the first sustain signal and the first sustain signal. The pre-driving unit pre-drives the first sustain signal and the first inverted sustain signal using an external voltage to generate a second sustain signal and a second inverted sustain signal. The storage driver outputs a storage signal whose phase is inverted for each frame to the storage line using the second sustain signal and the second sustain inverted signal.

In order to achieve the above object, a display device according to another exemplary embodiment of the present invention includes a display panel, a gate driver, a data driver, a power supply, and a storage driver. The display panel includes a plurality of pixels for displaying an image, and each pixel includes a storage line electrically connected to a gate line and a data line and arranged in parallel with the gate line. The gate driver outputs a gate signal to the gate line. The data driver outputs a data voltage to the data line. The storage driver outputs a storage signal whose phase is inverted for each frame to the storage line using a first sustain signal and a first inversion sustain signal. The power supply unit turns off the storage signal of the storage driver in a mode in which the data driver drives at the minimum power.

According to the display device according to the present invention, the power applied to the storage driver may be driven in advance by one or more steps by the pre-driving unit. In addition, the current consumption in the IC can be reduced by turning off the sustain signals applied to the storage driver in the standby mode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific form disclosed, it should be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing. In the accompanying drawings, the dimensions of the structure is shown in an enlarged scale than actual for clarity of the present invention. The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described on the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, parts, or combinations thereof. In addition, when a part of a layer, a film, an area, a plate, etc. is said to be above another part, this includes not only the case where it is directly over another part but also another part in the middle. Conversely, if a part of a layer, film, region, plate, etc. is under another part, this includes not only the part directly under another part but also another part in the middle.

Example 1

1 is a block diagram of a display device according to a first exemplary embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment may include a display panel 500, a controller 700, a gray division unit 800, a gate driver 600, a data driver 400, and a storage driver ( 100), a power supply unit 200, and a pre-driving unit 300.

The display panel 500 crosses the data lines DL1 to DLm to which the divided data voltages (eg, data signals) are supplied, and the gate lines crossing the data lines DL1 to DLm and activated by the gate signal. And a plurality of pixel portions electrically connected to GL1 to GLn. Further, the semiconductor device further includes storage lines SL1 to SLn formed to be parallel to the gate lines GL1 to GLn and intersect the data lines DL1 to DLm. Although not shown, the display panel 100 includes an array substrate on which gate lines GL1 to GLn, data lines DL1 to DLm, and storage lines SL1 to SLn are formed, and an opposite substrate facing the array substrate. (For example, a color filter substrate) and a liquid crystal layer interposed between the two substrates.

Each pixel portion includes a thin film transistor TFT having a gate electrode and a source electrode connected to the gate line GL and the data line DL, and a liquid crystal capacitor CLC and a storage capacitor CST electrically connected to the thin film transistor TFT. ) Is formed. The liquid crystal capacitor CLC functions as a dielectric using a pixel electrode connected to the drain electrode of the thin film transistor TFT and a common electrode provided with a common voltage as two electrodes, and a liquid crystal layer between the two electrodes. The common voltage Vcom provided to the common electrode is a direct current (DC) voltage maintaining a constant level of voltage. The pixel electrode and the common electrode may be formed on the same substrate or may be formed on different substrates. The storage capacitor CST is defined by a superposition of a pixel electrode connected to the drain electrode of the thin film transistor TFT and an electrode connected to the storage line SL, and functions as an insulator between the two electrodes.

The controller 700 receives the synchronization signals CONT and the image signal DATA from the outside, and controls the signals for driving the gate driver 600 and the data driver 400 based on the synchronization signals CONT. Create The synchronization signals CONT input to the controller 700 include a main clock signal MCLK, a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, and a data enable signal DE.

The gate control signals for controlling the gate driver 600 may include a vertical start signal STV indicating the start of output of the gate on signal Von and at least one gate clock signal controlling the period of the gate on signal Von. GATE CLK). The data control signals for controlling the data driver 400 include a horizontal start signal STH indicating the start of the transmission of the data signal for one horizontal pixel column and a load indicating the application of the data signal to the data lines DL1 to DLm. Signal TP and data clock signal DCLK. The data control signals may further include a polarity inversion signal RVS for inverting the voltage polarity (hereinafter, referred to as data polarity) of the data signal with respect to the common voltage Vcom. In addition, the controller 700 properly processes the image signal DATA received from the outside according to the operating conditions of the display panel 100, and then provides the image signal DATA to the data driver 400 through the gray division unit 800.

The gate driver 600 sequentially drives the gate lines GL1 to GLn formed on the display panel 500 based on the gate control signals provided from the controller 700. That is, by sequentially supplying a gate signal (eg, a gate on signal) for activating the gate line GL, the thin film transistors TFTs are turned on by being connected to the gate line GL to which the gate signal is applied. -on) run.

The data driver 400 supplies data signals to the data lines DL1 to DLm based on the data control signals provided from the controller 700. That is, the gray level signal provided from the gray level dividing unit 800 is converted into a corresponding data voltage (gradation voltage) and supplied to the data lines DL1 to DLm. Here, the data voltages output to the data lines DL1 to DLm are driven in a line inversion method in which polarities are inverted in units of one horizontal pixel column and inverted every one frame. For example, a negative data voltage is applied to odd-numbered horizontal pixel columns as data lines, a positive data voltage is applied to even-numbered horizontal pixel columns, and data of a reverse polarity is applied to the next frame. Apply voltage.

The storage driver 100 applies a storage voltage VST that is inverted in one frame period between the storage lines SL1 to SLn adjacent to the storage lines SL1 to SLn of the display panel 500. That is, different high level storage voltages VST1 and low level storage voltages VST2 are applied between adjacent storage lines SL1 to SLn. Here, the storage driver includes a boost unit 104, a signal input unit 106, and a voltage maintaining unit 102. The boost unit 104 outputs a driving voltage for driving the storage line. The signal input unit 106 inputs the second sustain signal and the second inverted sustain signal in synchronization with the gate signal. The voltage holding unit 102 maintains the boost signal at a constant level during the frame by using the signals input from the signal input unit.

The power supply unit 200 applies a voltage to the control unit 700, the gate driver 600, the data driver 400, the pre-driving unit 300, and the storage driver 100. The power supply unit 200 generates a first inverted sustain signal and a boost signal in which the phase is inverted in the first sustain signal and the first sustain signal, provides the boost signal to the storage driver 100, and maintains the boost signal constant. The voltage of the level is provided to the boost voltage lines VBH and VBL. In addition, the power supply unit 200 generates an external voltage VCI or GND for pre-driving and provides it to the pre-driving unit 300.

The pre-driving unit 300 is positioned between the power supply unit 200 and the storage driver 100 to pre-drive a signal applied to the storage driver 100. That is, the first sustain signal VCA1 and the first inverted sustain signal VCA2 generated by the power supply unit 200 of the pre-driving unit 300 are pre-dried. Here, when the signal level is changed from the low level (or GND) to the high level, the pre-driving unit 300 performs the discharge step by one or more steps using an external voltage (GND or VCI). For example, in accordance with the level change of the existing signal, the low level signal (or GND) is changed from the low level signal (or GND) to the high level signal through the external voltage VCI or GND without changing the level. You can step to the level. That is, the pre-driving unit first drives the low level signal (or GND) from the power supply unit using an external voltage VCI or GND, and then provides the final high level signal to the storage driver 100. Because of this, it is possible to reduce the power consumption of tens to hundreds of kHz.

Here, the pre-driving unit 300 uses a plurality of external voltages to at least once generate a signal (that is, a first sustain signal and a first inverted sustain signal) applied to the signal input unit 106 of the storage driver 100. The above can be pre-dried.

The pre-driving unit 300 pre-drives the first sustain signal and the first inverted sustain signal VCA1 and VCA2 generated by the power supply unit 200 using an external voltage VCI or GND, and the second sustain signal and The second inversion holding signals VCA1 and VCA2 are applied to the storage driver 100. Thus, in order to pre-drive the first sustain signal and the first inverted sustain signal VCA1 and VCA2, an external voltage VCI or GND is provided from the IC to the pre-driving portion. That is, the sustain signals directly applied from the power supply unit 200 to the storage driver 100 are driven first by an external voltage VCI and applied to the storage driver 100. For example, the first sustain signal and the first inverted sustain signals VCA1 and VCA2 output from the power supply unit 200 are pre-dried through the pre-driving unit 300 and the second inverted sustain signal VCA1. And VCA2) to the storage driver 100.

FIG. 2 is a circuit diagram of the storage driver shown in FIG. 1.

Referring to FIG. 2, the storage driver 100 may include a boost unit 104 that outputs a boost signal to a storage line in synchronization with a gate signal, and a signal that inputs a second sustain signal and a second inversion sustain signal in synchronization with a gate signal. And a voltage holding unit 102 for maintaining the boost signal at a constant level during the frame by using the signals input from the input unit 106 and the signal input unit.

The signal input unit 106 includes a first switching element TR1 and a second switching element TR2, and the voltage maintaining unit 102 includes a third switching element TR3, a fourth switching element TR4, and a first switching element TR1. Capacitor C1 and second capacitor C2 are included. The first switching element TR1 has an input terminal connected to the pre-driving unit 300 and a control terminal connected to the gate line GL. The second switching element TR2 is connected to the pre-driving unit 300, and the control terminal is connected to the gate line GL in common with the first switching element TR1. The third switching element TR3 has an input terminal connected to a high level boost voltage line VBH, a control terminal connected to an output terminal of the first switching element TR1, and an output terminal of the third switching element TR4. Commonly connected to the storage line SL. The fourth switching element TR4 has an input terminal connected to the low level boost voltage line VBL, the control terminal is connected to an output terminal of the second switching element TR1, and the output terminal has a third switching element TR3. Commonly connected to the storage line SL. The first capacitor C1 and the second capacitor C2 are formed between the control terminal and the input terminal of the third switching element TR3 and the fourth switching element TR4, respectively.

The second sustain signal and the second inverted sustain signal VCA1 and VCA2 provided from the signal input unit 106 are switched in the switching elements TR1 and TR2 included in the signal input unit 106 and the voltage sustain unit 102. The third sustain voltage and the third inverted sustain voltage of constant levels are output through the elements TR3 and TR4, respectively. Here, the third sustain voltage is a voltage at a higher level than the third inverted sustain voltage. Therefore, the storage driver 100 outputs the storage voltage VST whose phase is inverted and maintained constant every frame by the third sustain voltage and the third inverted sustain voltage to the storage line. In response to the signal, the storage line SLn receives a sustain voltage (eg, a third sustain voltage or a third inverted sustain voltage) at a level corresponding to the boost voltage output by the voltage sustainer 102 through the booster 104. Output during frames.

3 is a waveform diagram of input and output signals of the storage driver shown in FIG. 2.

2 and 3, when the gate signal is turned on during the Mth frame, the pre-dried second sustain signal VCA1 is a high level signal to the first switching element TR1 of the signal input unit 106. The provided and pre-dried second inverted sustain signal VCA2 is provided to the second switching element TR2 of the signal input unit 106 as a low level signal. Accordingly, the second sustain signal VCA1 applied as the high level signal turns on the third switching element TR3 of the voltage holding unit 102, thereby boosting the boost unit 104 by using the high level third sustain voltage. The high level boost signal provided by the signal is kept constant at the high level signal. During the (M + 1) th frame, when the gate signal is turned on, the pre-dried second sustain signal VCA1 is provided to the first switching element TR1 of the signal input unit 106 as an inverted low level signal. The pre-dried second inversion hold signal VCA2 is provided to the second switching element TR2 of the signal input unit 106 as an inverted high level signal. Accordingly, the second inversion holding signal VCA2 applied as the high level signal turns on the fourth switching element TR4 of the voltage holding unit, thereby providing a low provided from the boost unit 104 using the third holding voltage of the low level. The level boost signal is kept constant as the low level signal.

That is, the second sustain signal VCA1 is inverted from a high level signal to a low level signal every frame. The second inversion holding signal VCA2 is inverted from a low level signal to a high level signal in contrast to the second holding signal VCA1 every frame. In addition, the boost voltage has the same phase as the second sustain signal VCA1 and is inverted for each frame. The second sustain signal VCA1 and the second inverted sustain signal VCA2 are pre-dried to form a stepped waveform, and the boost signal VBS forms a rectangular waveform.

In other words, when the gate signal becomes high during the Mth frame, the first switching element, the second switching element, and the fifth switching element are turned on. Here, when the gate signal is at a high level, the thin film transistors connected to the gate line are turned on to charge each pixel electrode with a positive data voltage.

Subsequently, the pre-dried second sustain signal VCA1, the second inverted sustain signal VCA2, and the boost signal VBS are applied from the power supply unit 200 to the storage driver 100. When the second sustain signal VCA1 is at the high level, the first switching element TR1 is turned on to output the first switching voltage, and the low level second inverted sustain signal VCA2 having the opposite phase is second switched. The device TR2 is turned off. Thus, the output first switching voltage is charged in the first capacitor, and the third switching element outputs the third sustain voltage by the charged voltage. On the other hand, when the second inversion holding signal VCA2 is at the high level, the second switching element TR2 is turned on to output the second switching voltage, and the high level of the second holding signal VCA1 having the opposite phase is set to the first level. 1 Turn off the switching element TR1. Thus, the output second switching voltage is charged in the second capacitor, and the fourth switching element outputs the third inverted sustain voltage by the charged voltage.

In addition, the boost signal VBS outputs a boost voltage through the fifth switching element in response to the gate signal. The boost voltage is output to the storage line SL at a constant level storage voltage for one frame by the third sustain voltage and the third inverted sustain voltage. That is, when the boost signal VBS is at the high level, the high level is maintained by the third sustain voltage generated by the second sustain signal VCA1 having the same phase as the boost signal VBS, and the boost signal VBS is low. In the case of the level, the low level is maintained by the third inversion sustain voltage generated by the second inversion sustain signal VCA2 having a phase different from that of the boost signal VBS.

4A through 4D are waveform diagrams of various signals pre-dried by the pre-driving unit of FIG. 1.

4A to 4D, signals may be provided in various waveform forms. For example, FIG. 4A is pre-dried using an intermediate voltage (eg, an external voltage VCI) of GND and the high level voltage VCAH, and FIG. 4B is a voltage closer to the low level voltage VCAL. Pre-dried using GND), 4c is pre-dried using the intermediate voltage VCI of the low-level voltage VCAL and the high-level voltage VCAH, and FIG. 4D is a low-level voltage. At VCAL, two steps are pre-dried using a plurality of external voltages (GND or VCI). This has the effect of reducing power consumption by pre-driving respective maintenance signals rather than applying a signal directly to the storage driver 100 without pre-driving from the power supply 200. Also, as in FIG. 4D, the effect of two stage pre-driving is greater than the effect of one stage pre-driving, as in FIGS. 4A-4C. In other words, the effect increases as the step increases.

Example 2

5 is a block diagram of a display device according to a second exemplary embodiment of the present invention.

Referring to FIG. 5, a display device according to another exemplary embodiment may include a display panel 500, a controller 700, a gray division unit 800, a gate driver 600, a data driver 400, and storage. The driving unit 100 and the power supply unit 200 are included.

Since the configuration of the display device according to the second exemplary embodiment is substantially the same except for the pre-driving unit 300 of the first exemplary embodiment, the same description as that of the first exemplary embodiment will be omitted and only the differences will be described.

The control unit 700 according to the present embodiment receives the synchronization signals CONT, the image signal DATA, and the mode signal MS from the outside, and the gate driver 600 and the data are based on the synchronization signals CONT. Control signals for driving the driver 400 are generated, and control signals for driving the storage driver 100 are generated based on the mode signal MS. Here, the mode signal MS may be divided into a standby mode signal and a normal mode signal. Standby mode is a mode of driving with minimum power. The synchronization signals CONT input to the controller 700 include a main clock signal MCLK, a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, and a data enable signal DE.

The power supply unit 200 applies a voltage to the control unit 700, the gate driver 600, the data driver 400, and the storage driver 100. The power supply unit 200 receives a control signal for driving the storage driver 100 according to a mode selected from the control unit 700. For example, there may be a normal mode in which the data voltage is 0 to 64 gradation voltages or 0 to 256 gradation voltages, and a standby mode in which the data voltages are white gradation voltages AVSS and black gradation voltages GVDD.

When the control unit 700 receives the mode signal MS indicating that the display panel 500 is in the standby mode, the control unit 700 sends the power supply unit 200 to the eight color modes (that is, the color driver). Transmit a control signal for driving in the standby mode). In this case, the control signal includes information for controlling a signal applied to the storage driver 100. According to the control signal, the power supply unit 200 turns off the first sustain signal and the first inverted sustain signals VCA1 and VCA2 applied to the storage driver 100 and applies only the boost signal VBS.

Meanwhile, when the controller 700 receives the mode signal MS indicating that the display panel 500 is a normal mode, the controller 700 processes the image signal DATA received from the outside according to the mode condition. The control signal is transmitted to the gray scale division unit 800, the transmitted image signal is divided into 64 gray levels or 256 gray levels, and the divided image signals (gradation signals) are provided to the data driver 400. Accordingly, the data driver 400 converts the gray level signals divided from the gray level dividing unit 800 into corresponding data voltages (ie, gray level voltages).

Meanwhile, although the gradation divider 800 is illustrated as an independent unit in the drawing, the gradation divider 800 may be configured to be integrated into a graphic device, a liquid crystal display module, a controller 700, and a data driver 400. .

FIG. 6 is a conceptual diagram illustrating driving of an eight color mode according to the display device of FIG. 5, and FIG. 7 is a graph illustrating voltage-transmittance of liquid crystals according to gray scale voltages.

Referring to FIG. 6, the eight-color driving is a case where only the white gray voltage AVSS and the black gray voltage GVDD are applied to each of the RGB pixels.

As shown in FIG. 7, the light transmittance according to the voltage applied to the liquid crystal has little change in the light transmittance even if the voltage decreases and increases below the voltage of V0 and above the voltage of V256. Therefore, in the standby mode, the white gray voltage AVSS below V0 and the black gray voltage GVDD above V256 are applied. Therefore, even if the voltage level has a slight error range, the transmittance and luminance are almost unchanged, so flicker or crosstalk Also does not occur. That is, in the standby mode, since there is no reason to accurately maintain the storage voltage VST by the third sustain voltages of the storage driver 100, such as V0 to V256, the first sustain signal and the first inverted sustain signal ( By turning off VCA1 and VCA2), the IC can reduce tens to hundreds of kilowatts of current.

8 is a waveform diagram illustrating input and output signals of the storage driver illustrated in FIG. 5.

2 and 8, referring to 9, the first sustain signal and the first inverted sustain signal VCA1 and VCA2 provided from the power supply unit 200 are provided in an off state, and the boost signal VBS is normal. In the same manner as the mode, the phase is provided inverted for each frame.

Therefore, according to the display device according to the present invention, by inverting the voltage level of the storage line after the data voltage is charged, the voltage level of the pixel electrode is boosted to improve the response speed, and free the signals applied to the storage driver. It is possible to effectively reduce power consumption by driving one or more steps in advance by the driving unit. In addition, the current consumption in the IC can be reduced by turning off the sustain signals applied to the storage driver in the standby mode. In addition, the storage line can improve brightness by keeping the voltage level constant without floating after inversion.

Although described with reference to the above embodiments, those skilled in the art can be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

1 is a block diagram of a display device according to a first exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram of the storage driver shown in FIG. 1.

3 is a waveform diagram of input and output signals of the storage driver shown in FIG. 2.

4A through 4D are waveform diagrams of various signals pre-dried by the pre-driving unit of FIG. 1.

5 is a block diagram of a display device according to a second exemplary embodiment of the present invention.

FIG. 6 is a conceptual diagram for describing driving of an eight color mode according to the display device of FIG. 5.

7 is a graph showing the voltage-transmittance of the liquid crystal according to the gray scale voltage.

8 is a waveform diagram illustrating input and output signals of the storage driver illustrated in FIG. 5.

       <Description of the symbols for the main parts of the drawings>

100: storage drive unit 200: power supply unit

300: pre-driving unit 400: data driver

500: display panel 600: gate driver

700: control unit 800: gradation dispenser

Claims (9)

A display panel including a plurality of pixels for displaying an image, each pixel including a storage line electrically connected to a gate line and a data line and disposed in parallel with the gate line; A gate driver configured to output a gate signal to the gate line; A data driver outputting a data voltage to the data line; A power supply unit generating a first sustain signal and a first inverted sustain signal whose phase is inverted in the first sustain signal; A pre-driving unit configured to generate a second sustain signal and a second inverted sustain signal by pre-driving the first sustain signal and the first inverted sustain signal using an external voltage; And And a storage driver configured to output a storage signal having a phase inverted for each frame to the storage line using the second sustain signal and the second sustain inverted signal. The method of claim 1, wherein the storage drive unit, A boost unit configured to output a boost signal as a storage signal in synchronization with the gate signal; A signal input unit configured to input the second sustain signal and a second inverted sustain signal in synchronization with the gate signal; And And a voltage holding unit configured to maintain the boost signal at a constant level for a frame by using the signals input from the signal input unit. The method of claim 2, wherein the signal input unit, A first switching element configured to input a second sustain signal from the power supply unit; And And a second switching element configured to input a second inversion holding signal from the power supply unit. The method of claim 2, wherein the voltage holding unit, A third switching element configured to output a third sustain signal to the storage line in response to a signal input from the signal input unit; A fourth switching element configured to output a third inversion sustain voltage to the storage line in response to an inversion signal input from the signal input unit; A first capacitor charged with the signal voltage input from the signal input unit to maintain the on / off state of the third switching element for one frame; And And a second capacitor charged with the inverted signal voltage input from the signal input unit to maintain the on / off state of the fourth switching element for one frame. The method of claim 4, wherein the boost portion, And a fifth switching device configured to output the boost signal to the storage line in response to the gate signal. The display device of claim 1, wherein the pre-driving unit pre-drives the first sustain voltage and the first inverted sustain voltage using a plurality of external voltages. A display panel including a plurality of pixels for displaying an image, each pixel including a storage line electrically connected to a gate line and a data line and disposed in parallel with the gate line; A gate driver configured to output a gate signal to the gate line; A data driver outputting a data voltage to the data line; A storage driver configured to output a storage signal having a phase inverted for each frame to the storage line, and to maintain the storage signal at a level of a boost signal during a frame by using a sustain signal and an inverted maintenance signal whose phase is inverted with the sustain signal; And And a power supply unit configured to turn off the sustain signal and the inverted sustain signal of the storage driver in a mode in which the data driver is driven at the minimum power. The display device of claim 7, wherein the data voltage output to the data line comprises a white gray voltage and a black gray voltage. The method of claim 7, wherein the storage drive unit, A boost unit configured to output the boost signal to the storage line in synchronization with the gate signal; An input signal unit having a first switching element and a second switching element connected to the power supply unit; And A third switching device connected to the signal input unit to output a high level sustain signal, a fourth switching device connected to the signal input unit to output a low level sustain signal, and the third switching device and the fourth switching device respectively. And a voltage holding unit including a first capacitor and a second capacitor formed between an input terminal and a control terminal of the second terminal.

Images