KR20080020743A - Data driving circuit and display device including same - Google Patents

Abstract

Disclosed are a data driving circuit for improving a driving failure of a display device due to a lack of timing margin, and a display device including the same. The data driving circuit includes a shift register, a first latch, a second latch, a logic operation unit, a data latch unit, and a digital / analog converter. The shift register shifts the horizontal start signal in synchronization with the data clock signal to generate a sampling signal. The first latch latches and outputs the load signal in synchronization with the data clock signal, and the second latch latches and outputs the output signal of the first latch in synchronization with the data clock signal. The logic calculating unit performs a logic operation on the output signals of the first latch and the second latch, and outputs an update control signal. The data latch unit latches the data signal in response to the sampling signal, and outputs and updates the latched data signal in response to the update control signal. The digital / analog converter converts the data signal provided from the data latch unit into a corresponding analog data signal and outputs the analog signal. As a result, when the timing margin is insufficient, the latching of the data signal is normally performed, thereby improving driving failure of the display device.

Description

Data driving circuit and display device including the same {DATA DRIVER AND DISPLAY APPARATUS HAVING THE SAME}

1 is a diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram illustrating the data driving circuit shown in FIG. 1.

FIG. 3 is a diagram for describing a configuration of an embodiment of the latch driver illustrated in FIG. 2.

4A is a signal waveform diagram when there is a timing margin of the latch driver shown in FIG. 3.

4B is a signal waveform diagram when there is no timing margin of the latch driver shown in FIG. 3.

<Description of the symbols for the main parts of the drawings>

200: data driving circuit 210: shift register

220: data register 230: latch driver

240: data latch unit 250: digital / analog conversion unit

260: output buffer unit DCLK: data clock signal

TP: load signal DATA: data signal

LS: update control signal VGMA: reference gamma voltage

The present invention relates to a data driving circuit and a display device including the same, and more particularly, to a data driving circuit for improving a driving failure of a display device due to lack of timing margin and a display device including the same.

In general, a liquid crystal display device includes a display panel displaying an image using a light transmittance of a liquid crystal, and a driving device for driving the display panel. The display panel includes a plurality of pixel parts defined by a plurality of gate lines and data lines. The driving device includes a timing controller for receiving synchronization signals and data signals from an external graphic device, a data driving circuit for outputting an analog data signal to the data lines based on the control signal and the data signal provided from the timing controller, and a timing controller. And a gate driving circuit that sequentially activates the gate lines based on a control signal provided by the control circuit.

Here, the gate driving circuit typically processes the data signal by latching the horizontal pixel column by one horizontal pixel column, and includes a data latch unit for latching the data signal provided therefor. The data latch unit updates the data signal in synchronization with the control signal.

However, in the case of a high resolution image such as a moving image, a lack of timing margin of a control signal causes a poor driving of the display device due to a poor update of the latched data signal.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a data driving circuit and a display device including the same for improving the driving failure of the display device due to lack of timing margin.

A data driving circuit according to an embodiment for realizing the above object of the present invention includes a shift register, a first latch, a second latch, a logic operation unit, a data latch unit, and a digital / analog converter. The shift register generates a sampling signal by shifting a horizontal start signal in synchronization with a data clock signal provided from an external controller. The first latch latches and outputs a load signal in synchronization with the data clock signal, and the second latch latches and outputs an output signal of the first latch in synchronization with the data clock signal. The logic calculating unit logically operates an output signal of the first latch and the second latch and outputs an update control signal. The data latch unit latches a data signal in response to the sampling signal, and outputs and updates the latched data signal in response to the update control signal. The digital / analog converter converts the data signal provided from the data latch unit into a corresponding analog data signal and outputs the analog signal.

According to at least one example embodiment of the inventive concepts, a display device includes a display panel including data lines and a plurality of pixel portions formed by data lines, a gate driving circuit and a horizontal start signal for driving the gate lines. A control signal including a data clock signal and a load signal and a data driving circuit for receiving the data signal and driving the data lines, wherein the data driving circuit includes a first latch, a second latch, a logic operation unit, and a data latch unit. And a digital / analog converter. The first latch latches and outputs the load signal in synchronization with the data clock signal, and the second latch latches and outputs an output signal of the first latch in synchronization with the data clock signal. The logic calculating unit logically operates an output signal of the first latch and the second latch and outputs an update control signal. The data latch unit latches the data signal and outputs and updates the latched data signal in synchronization with the update control signal. The digital / analog converter converts the data signal provided from the data latch unit into a corresponding analog data signal and outputs the analog signal.

According to such a data driving circuit and a display device including the same, when the timing margin of the control signal is insufficient, the latching of the data signal is normally performed to improve the driving failure of the display device.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display panel 100 and a driving circuit unit for driving the display panel 100, and the driving circuit unit includes a timing controller 400 and a gate driving circuit ( 300 and the data driving circuit 200.

The display panel 100 includes an array substrate and an opposing substrate (eg, a color filter substrate) facing each other at a predetermined interval, and a liquid crystal layer interposed between the array substrate and the opposing substrate. The display panel 100 includes a plurality of pixel parts formed by the gate lines GL1 to GLn and the data lines DL1 to DLm intersecting the gate lines GL1 to GLn. Each pixel unit includes a thin film transistor TFT as a switching element, a liquid crystal capacitor CLC and a storage capacitor CST electrically connected to the thin film transistor TFT. In this case, the gate electrode and the source electrode of the thin film transistor TFT are connected to the gate line GL and the data line DL, respectively, and the drain electrode is connected to the liquid crystal capacitor CLC and the storage capacitor CST.

The timing controller 400 receives the synchronization signals and the data signal DATA from an external device, and the synchronization signals are the main clock signal MCLK, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal. (DE). The timing controller 400 generates and provides gate control signals for controlling the gate driving circuit 300 and data control signals for controlling the data driving circuit 200 based on the input synchronization signals.

Here, the gate control signals for controlling the gate driving circuit 300 include a vertical start signal STV and a gate clock signal GATE CLK. The data control signals for controlling the data driving circuit 200 include a horizontal start signal STH, a data clock signal DCLK, and a load signal TP.

In addition, the timing controller 400 processes the data signal DATA received from an external device and provides the data driving signal to the data driving circuit 200 together with the data control signals, and the timing controller 400 is connected to the data signal DATA. The data clock signal DCLK is preferably transmitted through a differential signal transmission method such as a reduced swing differential signaling (RSDS) interface method.

The gate driving circuit 300 sequentially outputs gate signals for activating the gate lines GL1 to GLn formed on the display panel 100 based on the gate control signals received from the timing controller 400. The gate driving circuit 300 is typically disposed at one end of the gate lines GL1 to GLn, and may be formed of a plurality of driving chips or may be directly formed in the integrated circuit form on the display panel 100.

The data driving circuit 200 converts the data signal DATA into a corresponding analog data signal (for example, a data voltage) based on the data control signals input from the timing controller 400 to the data lines DL1 to DLm. Output Here, the analog data signal is generated based on the gamma reference voltages VGMAs provided by the gamma reference voltage generator (not shown). The data driving circuit 200 is typically disposed at one end of the data lines DL1 to DLm and includes a plurality of driving chips.

FIG. 2 is a block diagram illustrating the data driving circuit shown in FIG. 1.

1 and 2, the data driver circuit 200 includes a shift register 210, a data register 220, a latch driver 230, a data latch unit 240, a digital / analog converter 250, An output buffer unit 260 is included.

 The shift register 210 receives the horizontal start signal STH and the data clock signal DCLK from the timing controller 400, shifts the horizontal start signal STH in synchronization with the data clock signal DCLK, and samples the signal. And a generated sampling signal is provided to the data latch unit 240.

The data register 220 relays the data signal DATA provided from the timing controller 400 to the data latch unit 240 in synchronization with the data clock signal DCLK.

The latch driver 230 processes the load signal TP and the inverted input data clock signal DCLK to provide the data latch unit 240 with an update control signal instructing the output of the latched data signal DATA. .

 The data latch unit 240 includes a plurality of unit data latches, and sequentially latches the data signal DATA provided from the data register 220 in response to the sampling signal and sequentially latches the unit data latches. The latched data signal DATA is output in response to the update control signal provided from the latch driver 230. For example, the data latch unit 240 latches and outputs the data signal DATA in units of one horizontal pixel.

The digital / analog converter 250 receives the data signal DATA provided from the data latch unit 230 and converts the data signal DATA into corresponding analog data signals (eg, data voltages) based on the plurality of gamma reference voltages VGMA. Convert and output

The output buffer unit 260 is composed of a plurality of unit output buffers, and buffers the analog data signal provided from the digital / analog converter 250 and outputs the buffered data to the data lines DL1 to DLm.

Meanwhile, in the data driver circuit 200 according to the present invention, the latch driver 230 that controls the output and update of the data signal DATA to the data latch unit 240 includes a load signal TP and a data clock signal DCLK. In case the timing margin of the T1 is insufficient, the update control signal LS is generated to drive the data latch unit 240.

FIG. 3 is a diagram for describing a configuration of an embodiment of the latch driver illustrated in FIG. 2.

1 and 3, the latch driver 230 according to an exemplary embodiment of the present invention includes a first latch 232, a second latch 234, and a logic operator 236.

The first latch 232 latches the load signal TP provided from the timing controller 400 in synchronization with the data clock signal DCLK inverted and outputs the latched signal (hereinafter, referred to as the first latch). Output signal is referred to as a first control signal). For example, the first latch 232 is a D flip-flop in which an input signal is sampled at the rising point of the control signal and latched (input), and the output is preserved regardless of subsequent input signals until the rising point of the next control signal. -Flop). That is, the first latch 232 receives the inverted data clock signal DCLK and the load signal TP as a control signal and an input signal, respectively, and the inverted data clock signal DCLK is high at a low value. In synchronism with the ascending time of switching to a high value, the load signal TP is sampled and latched and the output is preserved until the ascending time of the next data clock signal DCLK.

The second latch 234 latches the first control signal CS1 output from the first latch 232 in synchronization with the inverted data clock signal DCLK and outputs the latched signal (hereinafter referred to as the second latch). Output signal of the second control signal). For example, the second latch 234 is a register formed of a D flip-flop, and receives the inverted data clock signal DCLK and the first control signal CS1 as a control signal and an input signal, respectively. The first control signal CS1 is latched and output in synchronization with the rising time of the inverted data clock signal DCLK.

Meanwhile, since the first latch 232 and the second latch 234 are synchronized with the rising time of the inverted data clock signal DCLK, the first latch 232 and the second latch 234 may be defined as latching in synchronization with the falling time of the data clock signal DCLK. .

The logic operation unit 236 may perform an inversion unit 236b for inverting the second control signal CS2 and an AND logic element 236a for performing an AND operation on the first control signal CS1 and the inverted second control signal CS2. And an update control signal LS instructing output and update of the data signal to the data latch unit 240 based on the first control signal CS1 and the second control signal CS2. That is, when the first control signal CS1 is a high value and the second control signal CS2 is a low value, the update control instructs the data latch unit 240 to output the data signal and instructs the latch of the new data signal. Output the signal LS.

4A and 4B are signal waveform diagrams for explaining the operation of the latch driver shown in FIG. 3, and FIG. 4A is a signal waveform diagram when there is a timing margin between the load signal and the data clock signal. This is a signal waveform diagram when there is no timing margin between the signal and the data clock signal.

Here, the rising time of the load signal TP in a diagonal line means a delay (rising time) according to information transmission using a TTL / CMOS interface in the case of the load signal TP.

3 and 4A, when there is a timing margin between the rising time of the load signal TP and the falling time of the data clock signal DCLK, the load signal TP is the falling time of the data clock signal DCLK. It is previously switched over the threshold voltage. That is, in synchronization with the first falling time point DC1 of the data clock signal DCLK, the first latch 232 latches the load signal TP to a high value and outputs the first control signal CS1 at a low value. The transition to high value. At the same time, the second latch 234 latches and outputs the first control signal CS1, which is kept at the low value, in synchronization with the first falling time DC1, so that the second control signal CS2 has a low value. Accordingly, since the logic operation unit 236 outputs a high value based on the first control signal CS1 that is a high value and the second control signal CS2 that is a low value, the update control signal LS is switched from a low value to a high value. .

Next, in synchronization with the second falling time point DC2 of the data clock signal DCLK, since the first latch 232 latches and outputs the load signal TP which is a high value, the first control signal CS1 outputs a high value. Since the second latch 234 latches and outputs the first control signal CS1 converted to the high value at the first falling time DC1, the second control signal CS2 is switched to the high value. Therefore, since the logic calculator 236 outputs a low value based on the first and second control signals CS2 that are high values, the update control signal LS is switched from the high value to the low value.

Next, the first latch 232 and the second latch 234 output the first and second control signals CS2 having high values, respectively, in synchronization with the third falling time point DC3 of the data clock signal DCLK. The control signal LS is outputted with a low value.

3 and 4B, when there is no timing margin between the rising time of the load signal TP and the falling time of the data clock signal DCLK (234), the load signal TP is the data clock signal DCLK. It is not possible to switch over the threshold voltage before the fall time of. That is, in synchronization with the first falling time point DC1 of the data clock signal DCLK, the first latch 232 latches and outputs the load signal TP to a low value, so that the first control signal CS1 has a low value. Is output. At the same time, the second latch 234 latches and outputs the first control signal CS1, which is kept at the low value, in synchronization with the first falling time DC1, so that the second control signal CS2 has a low value. Therefore, since the logic operation unit 236 outputs a low value based on the first and second control signals CS2 that are low values, the update control signal LS outputs a low value.

Next, in synchronization with the second falling time point DC2 of the data clock signal DCLK, the first latch 232 latches and outputs the load signal TP, which has been converted to a threshold voltage or higher, to a high value and thus, the first control signal. CS1 is switched to a high value, and the second latch 234 latches and outputs the first control signal CS1 that held the low value, so that the second control signal CS2 is low. Accordingly, since the logic calculator 2360 outputs a high value based on the first control signal CS1 that is a high value and the second control signal CS2 that is a low value, the update control signal LS switches from a low value to a high value. do.

Next, in synchronization with the third falling time point DC3 of the data clock signal DCLK, the first latch 232 latches the load signal TP and outputs a high value. Therefore, the first control signal CS1 is set to a high value. Since the second latch 234 latches and outputs the first control signal CS1 converted to the high value at the second falling time DC2, the second control signal CS2 is switched to the high value. Therefore, the update control signal LS is switched from the high value to the low value.

As such, when the timing margin is between the load signal TP and the data clock signal DCLK, the latch driver 230 drops the first data clock signal DCLK applied after the rising time of the load signal TP. The second control clock generates the update control signal LS in synchronization with the timing and is applied after the rising time of the load signal TP when there is no timing margin between the load signal TP and the data clock signal DCLK. The update control signal LS is generated in synchronization with the falling time of the signal DCLK. That is, by generating the update control signal LS regardless of the timing margin between the load signal TP and the data clock signal DCLK, the data latch unit 240 is controlled to output and update the data signal DATA. Drive to make this happen.

Meanwhile, the logic operation unit 236 of the latch driver 230 may be configured by using a NAND logic element instead of the AND logic element 236a. As described above, when the NAND logic element is used, the output signal of the logic operation unit 236 composed of the NAND logic element is negative (inverted) relationship with the output signal of the AND logic element 236a, so that the data latch unit 240 is NAND. An inverting part must be provided at the input terminal so that the output signal of the logic element can be inverted and input.

As described above, according to the present invention, when the timing margin between the load signal for controlling the operation of the data driving circuit and the data clock signal is insufficient, the update control signal is synchronized with the second data clock signal applied after the load signal. By generating the data signal, the data latch is outputted and updated to improve the driving failure of the display device due to the lack of timing margin.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (8)

A shift register configured to shift the horizontal start signal in synchronization with a data clock signal provided from an external controller to generate a sampling signal; A first latch configured to latch and output a load signal in synchronization with the data clock signal; A second latch configured to latch and output an output signal of the first latch in synchronization with the data clock signal; A logic operation unit configured to output an update control signal by performing a logic operation on the output signals of the first latch and the second latch; A data latch unit configured to latch a data signal in response to the sampling signal, and output and update the latched data signal in response to the update control signal; And And a digital / analog converter converting the data signal provided from the data latch unit into a corresponding analog data signal and outputting the analog signal. The data driving circuit of claim 1, wherein each of the first latch and the second latch is a register including a D flip-flop. The data driving circuit of claim 2, wherein the first latch and the second latch are latched in synchronization with the data clock signal inputted inverted. The method of claim 3, wherein the logical operation unit An inverting unit which receives the output signal of the second latch and inverts the output signal; And And an AND logic element for performing an AND operation on the output signal of the inverter and the output signal of the first latch. The data latching unit of claim 3, wherein the data latch unit receives an inverted input of the update control signal. The logical operation unit An inverting unit which receives the output signal of the second latch and inverts it; And And a NAND logic element configured to perform an AND logic operation on the output signal of the inverter and the output signal of the first latch. A display panel including data lines and a plurality of pixel portions formed by the data lines; A gate driving circuit driving the gate lines; And A data driving circuit configured to receive a control signal and a data signal including a horizontal start signal, a data clock signal, and a load signal to drive the data lines; The data driving circuit A first latch configured to latch and output the load signal in synchronization with the data clock signal; A second latch configured to latch and output an output signal of the first latch in synchronization with the data clock signal; A logic operation unit configured to output an update control signal by performing a logic operation on the output signals of the first latch and the second latch; A data latch unit for latching the data signal and outputting and updating the latched data signal in synchronization with the update control signal; And And a digital / analog converter converting the data signal provided from the data latch unit into a corresponding analog data signal and outputting the analog signal. 7. The display device according to claim 6, wherein the first latch and the second latch are registers each formed of a D flip-flop, and are driven in synchronization with the data clock signal which is inverted. The method of claim 6, wherein the logical operation unit And an update control signal for outputting and updating the latched data signal when the output signal of the first latch is a high value and the output signal of the second latch is a low value. .

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