CN101345026B - Frame data buffer device and related frame data acquisition method thereof - Google Patents

Abstract

The invention discloses a frame data buffer device, which comprises a holding display used for displaying and holding frame data of a previous frame; and a data reading module for reading the frame data of the previous frame held on the hold-type display. The invention also discloses a data driving circuit, which comprises a video data input end for receiving video data; a driving voltage output end for outputting a driving voltage to the display panel of the hold-type display; a sample and hold unit for sampling and holding the voltage of the driving voltage output terminal according to a sampling signal to generate a sampling voltage; and a driving voltage generating unit for performing signal processing on the video data according to a plurality of reference voltages, a polarity selection signal and the sampling voltage to output the driving voltage.

Description

Frame data buffer device and related frame data acquisition method

technical field

The present invention relates to a frame data buffer device and related frame data acquisition method, in particular to a method of using the display panel of the hold display directly as a frame buffer by reading back the pixel voltage of the display panel of the hold display Devices and methods.

current technology

Compared with the pulse type <Impulse Type> driving method of the traditional image tube display, the holding type <Hold Type> display, such as: Liquid Crystal Display <Liquid Crystal Display, LCD>, generally has the problem of too slow response speed, making The displayed dynamic image will produce the phenomenon of motion blur (Motion Blur). In order to speed up the LCD speed and make the displayed image have better picture quality, some image processing technologies, such as: overdrive <Over-Driving>, de-interlacing <De-interlacing>, motion compensation <Motion Compensation> and frame transfer rate conversion <Frame Rate Conversion>, etc., have been widely used in today's products. However, the aforementioned image processing methods usually need to store data of at least one frame to perform calculations and generate video data of the next display frame. Therefore, in the prior art, the holding type display usually all must use memory, as: dynamic random access memory <Dynamic Random Access Memory, DRAM> or static random access memory <Static Random Access Memory, SRAM> etc., as A frame buffer <Frame Buffer> to store frame data.

Please refer to FIG. 1 , which is a schematic diagram of a video data processor 10 in a conventional hold display. The video data processor 10 is coupled between a video source <not shown in the figure> and a display system 130 , and includes a memory 100 , a memory control unit 110 and a data processing unit 120 . The memory 100 is used as a frame buffer to store previous picture data, the memory control unit 110 is used to control the access of the memory 100, and the data processing unit 120 is used to store the picture data according to the memory 100 and the currently received picture data. The video data of the next frame is outputted to the display system 130 through operations such as overdrive, de-interlacing, motion compensation, or frame rate conversion. Therefore, the display system 130 can output driving voltages to display corresponding images according to the video data output by the video data processor 10 .

Please continue to refer to FIG. 2 , which is a schematic diagram of a display system 130 in a conventional hold display. The display system 130 includes a display panel <Display Panel> 131 , a control circuit 132 , a data driving circuit 133 and a scanning driving circuit 134 . The control circuit 132 is used to generate corresponding control signals according to a horizontal synchronization signal <Horizontal Synchronization> 135 and a vertical synchronization signal <Vertical Synchronization> 136, and input them to the data driving circuit 133 and the scanning driving circuit 134 respectively. According to the control signal generated by the control circuit 132, the scanning driving circuit 134 can sequentially activate each scanning line on the display panel 131, and the data driving circuit 133 can also generate video data 137 according to the above-mentioned video data processor 10, The corresponding driving voltage is output to the display panel 131 to control the brightness <Brightness> state of the corresponding pixel, and then display the corresponding image.

Therefore, in the prior art, since the hold display must use an additional memory as a frame buffer to store related video data, the production cost cannot be effectively reduced.

Contents of the invention

Therefore, the main objective of the present invention is to provide a data driving circuit and method for a hold-type display.

The present invention discloses a data drive circuit for a hold type display, which includes a video data input terminal for receiving a video data; a driving voltage output terminal for outputting a driving voltage to the hold type display; a sample and hold The unit is coupled to the driving voltage output terminal, and is used to sample and hold the voltage of the driving voltage output terminal according to a sampling signal to generate a sampling voltage; and a driving voltage generating unit is coupled to the video data input terminal, the driving The voltage output terminal and the sample-and-hold circuit unit are used for signal processing the video data according to a plurality of reference voltages, a polarity selection signal and the sampling voltage, so as to output the driving voltage.

The present invention also discloses a driving method for a hold-type display, including receiving a video data; sampling and holding a voltage of a driving voltage output terminal according to a sampling signal to generate a sampling voltage; according to a plurality of reference voltages, A polarity selection signal and the sampling voltage are used for signal processing the video data to output a driving voltage; and outputting the driving voltage to the holding display.

The present invention also discloses a method for obtaining frame data, which includes using a holding display to display the frame data of a previous frame; and reading from the holding display the frame data of the previous frame held on the holding display frame data.

The present invention also discloses a frame data buffering device, which includes a holding display for displaying and holding the frame data of a previous frame; and a data reading module coupled to the holding display for reading the held display Frame data of the previous frame of the hold display.

Description of drawings

FIG. 1 is a schematic diagram of a video data processor in a conventional hold display.

FIG. 2 is a schematic diagram of a display system in a conventional hold display.

FIG. 3 is a functional block diagram of a data driving circuit for a hold-type display according to the present invention.

FIG. 4 is a schematic diagram of a flow for the data driving circuit of the present invention.

FIG. 5 is a schematic diagram of an embodiment of the data driving circuit of the present invention.

FIG. 6 is a schematic diagram of another embodiment of the data driving circuit of the present invention.

Fig. 7 is a schematic diagram of an embodiment of the application of the present invention.

FIG. 8 is a schematic diagram of a gamma curve.

Description of reference symbols

10 Video data processor

130 Display system

100 memory

110 memory control unit

120 data processing unit

131 display panel

132 Control circuit

133, 30 Data drive circuit

134 Scan driving circuit

135 horizontal sync signal

136 vertical sync signal

137. D1 video data

310 Video data input terminal

320 Driving voltage output terminal

330 sample and hold unit

340 driving voltage generation unit

341, 343 signal processing module

342, 344 computing units

VOUT driving voltage

SMP sampling signal

V1 Sampling voltage

V2 Second voltage

V3 The third voltage

V1' voltage

D3 Numerical data

D4 Signal processing result

REF1～REFn reference voltage

POL Polarity selection signal

40 Process

400, 410, 420, 430, 440, 450 steps

DAC1, DAC2 digital/analog converter

AMP1, AMP2 Voltage Operational Amplifiers

ADC2 Analog/Digital Converter.

Detailed ways

Please refer to FIG. 3. FIG. 3 is a functional block diagram of a data driving circuit 30 for a hold type <Hold Type> display of the present invention. The data driving circuit 30 includes a video data input terminal 310 , a driving voltage output terminal 320 , a sample and hold unit 330 and a driving voltage generating unit 340 . The video data input terminal 310 is used for receiving a video data D1. The driving voltage output terminal 320 is used to output a driving voltage VOUT to the display panel <Display Panel> of the holding display. The sample and hold unit 330 is coupled to the driving voltage output terminal 320 for sampling and holding the <Sample and Hold> voltage of the driving voltage output terminal 320 according to a sampling signal SMP to generate a sampling voltage V1. The driving voltage generation unit 340 is coupled to the video data input terminal 310, the driving voltage output terminal 320 and the sample-and-hold circuit unit 330, and is used to generate video data D1 according to the reference voltages REF1-REFn, a polarity selection signal POL and the sampling voltage V1. Signal processing is performed to output a corresponding driving voltage VOUT.

Please note here that because the frame data of the previous frame will still be stored in the hold display before the next frame <the current frame> is displayed <for example: in the case of a liquid crystal display, the data of the previous frame will be displayed in the form of voltage The mode is stored in the internal capacitance of the display panel of the liquid crystal display >, so the present invention uses the sample and hold unit 330 to read out the frame data stored in the hold display before the current frame is displayed. Therefore, the present invention utilizes the characteristic that the hold type display will hold the data of the previous frame. By sampling and holding the voltage of the driving voltage output terminal 320, the data of the previous frame can be known. Such a mechanism can be equivalent to the hold type display. The display panel of the display is directly used as a frame buffer <FrameBuffer>, so as to improve the problem in the prior art that an additional memory is required to store the previous frame data. In this way, the memory requirement can be greatly reduced, thereby effectively saving costs.

Regarding the operation mode of the data driving circuit 30 , please continue to refer to FIG. 4 , which is a schematic diagram of a process 40 for the data driving circuit 30 of the present invention. Process 40 includes the following steps:

Step 400: start.

Step 410 : Receive video data D1 through the video data input terminal 310 .

Step 420: According to the sampling signal SMP, the sampling and holding unit 330 samples and holds the voltage of the driving voltage output terminal 320 to generate the sampling voltage V1.

Step 430: According to the reference voltages REF1-REFn, the polarity selection signal POL and the sampling voltage V1, the driving voltage generation unit 340 performs signal processing on the video data D1 to output a corresponding driving voltage VOUT.

Step 440 : Output the driving voltage VOUT to the display panel of the holding display through the driving voltage output terminal 320 .

Step 450: end.

Therefore, according to the process 40 , the present invention firstly receives the video data D1 through the video data input terminal 310 . Then, the sample and hold unit 330 can sample and hold the voltage of the driving voltage output terminal 320 according to the sampling signal SMP to generate the sampling voltage V1, so that the driving voltage generating unit 340 can generate the sampling voltage V1 according to the sampling voltage V1, the reference voltages REF1˜REFn and the polarity The signal POL is selected to perform signal processing such as overdrive, de-interlacing, motion compensation or frame rate conversion on the video data D1, so as to output a corresponding driving voltage VOUT to the display panel.

It should be noted that, in order to directly use the display panel as a frame buffer, the data driving circuit 30 must read the current pixel voltage of the display panel (ie, the voltage of the driving voltage output terminal 320 ) before outputting a new driving voltage VOUT. For example, the present invention can sample the pixel voltage of the <Sample> display panel when the sampling signal SMP is at a high logic level. At this time, the driving voltage generating unit 340 stops outputting the driving voltage VOUT, and the output of the sampling and holding unit 330 The sampling voltage V1 varies with the pixel voltage of the display panel. On the contrary, when the sampling signal SMP switches to a low logic level, the sample and hold unit 330 holds <Hold> the current sampled voltage, and outputs the sampled voltage V1. Therefore, the driving voltage generation unit 340 can perform relevant signal processing on the current video data D1 according to the sampling voltage V1 , the reference voltages REF1 ˜ REFn and the polarity selection signal POL to output the corresponding driving voltage VOUT. Such a mechanism should not be difficult for those with ordinary knowledge in this field. For example, the circuit designer can set each driving time of the gate drive signal as two phases <Phase>, and the first phase is used for sampling The holding unit 330 samples the information of the previous frame from the display panel, and the second stage is used to allow the driving voltage generation unit 340 to perform signal processing according to the information of the previous frame and the current frame, so as to output the corresponding driving voltage VOUT to Drive the screen. In an actual system, the sampling signal SMP and the polarity selection signal POL can be generated by a control circuit (not shown in the figure) of the hold display, such as a timing controller <Timing Controller>, and the reference voltages REF1~REFn can be generated according to A gamma curve <Gamma Curve> shown in FIG. 8 is generated.

In addition, the operation of using the driving voltage generation unit 340 to perform signal processing is not difficult for those who have ordinary knowledge in this field. For example, the present invention can compare the sampling voltage V1 of the video data of the previous frame with the current video data D1, and use a calculation unit (not shown in FIG. 3 ) of the driving voltage generating unit 340 to calculate the voltage of the current frame The required overdrive voltage information is used to output the corresponding drive voltage VOUT.

Please refer to FIG. 5 , which is a schematic diagram of an embodiment of the data driving circuit 30 of the present invention. As shown in FIG. 5 , the driving voltage generating unit 340 includes a digital/analog converter DAC1 and a signal processing module 341 . The digital/analog converter DAC1 is coupled to the video data input terminal 310 and can be used to convert the video data D1 into an analog second voltage V2 according to the reference voltages REF1˜REFn. The signal processing module 341 is coupled to the digital/analog conversion unit DAC1 , the sampling and holding unit 330 and the driving voltage output terminal 320 , and may include a calculation unit 342 and a voltage operational amplifier AMP1 . The calculation unit 342 can be used to perform signal processing on the second voltage V2 according to the polarity selection signal POL and the sampling voltage V1 generated by the sample and hold unit 330; and the voltage operational amplifier AMP1 is used to buffer and amplify the calculation output by the calculation unit 342 As a result, a corresponding driving voltage VOUT is generated. As known to those skilled in the art, the structure of the driving voltage generation unit 340 in the embodiment of the present invention is similar to that of the prior art, except that the signal processing module 341 can change the output driving voltage according to the polarity selection signal POL. In addition to the polarity of VOUT, according to the sampling voltage V1 output by the sample and hold unit 330 , signal processing such as overdrive, de-interlacing, motion compensation or frame rate conversion can be performed on the second voltage V2. Preferably, the calculation unit 342 can also be used to switch the polarity of the sampling voltage V1 to a polarity corresponding to the second voltage V2 according to the polarity selection signal POL.

For example, the calculation unit 342 can first convert the sampling voltage V1 to a voltage V1' having the same polarity as the second voltage V2 according to the polarity selection signal POL. In this way, the voltage amplifier AMP1 can perform related signal processing on the second voltage V2 according to the voltage V1', so as to output the corresponding driving voltage VOUT through the voltage operational amplifier AMP1. For example, during overdrive, the calculation unit 342 can output the corresponding driving voltage VOUT through the voltage operational amplifier AMP1 according to the following formula: VOUT=V2+K(V2-V1'). Wherein, K can be a default value or a variable value that can vary with the voltage V1' and the second voltage V2.

On the other hand, for the de-interlacing operation, since the calculation unit 342 can receive the information of the previous frame <that is, the voltage V1 or the aforementioned voltage V1'> and the information of the current frame <that is, the voltage V2>, therefore, when deinterleaving During the interleaving process, the calculation unit 342 can also be designed to perform an interpolation operation <Interpolation>, etc. Such corresponding changes also belong to the scope of the present invention.

In addition, please refer to FIG. 6 , which is a schematic diagram of another embodiment of the data driving circuit 30 of the present invention. The data driving circuit 30 may further include an analog/digital converter ADC2, coupled between the sampling and holding unit 330 and the driving voltage generation unit 340, for converting the output of the sampling and holding unit 330 according to the reference voltages REF1˜REFn. The sampling voltage V1 is converted into digital data D3 in digital form. Preferably, the analog/digital converter ADC1 can also convert the polarity of the digital data D3 to a polarity corresponding to the video data D1 according to the polarity selection signal POL. Therefore, a signal processing module 343 of the driving voltage generation unit 340 can perform signal processing on the video data D1 such as overdrive, de-interlacing, motion compensation, or frame rate conversion according to the digital data D3, and according to the reference voltages REF1˜REFn, Converting a signal processing result D4 to an analog third voltage V3. Preferably, the signal processing module 343 can be composed of a calculation unit 344 and a digital/analog converter DAC2, as shown in FIG. 6 . Finally, a voltage amplifier AMP2 of the driving voltage generating unit 340 can buffer and amplify the third voltage V3 according to the polarity selection signal POL, so as to output the corresponding driving voltage VOUT.

For example, when overdriving, the computing unit 344 can generate a corresponding signal processing result D4 according to the following formula: D4=D1+K(D1-D3). Wherein, K can be a default value or a variable value that can vary with the video data D1 and the digital data D3. Compared with the embodiment in FIG. 5 that performs signal processing in an analog manner, this embodiment performs signal processing on the video data D1 in a digital manner. Since digital signals are easier to use for signal processing, in addition to having a more flexible implementation In addition to various algorithms, more accurate signal processing results can also be obtained.

Please note here that although in the aforementioned embodiments, the frame data of the previous frame <that is, the data output by the sample-and-hold circuit> is provided to the data driving circuit 30 as compensation for the driving signal, such an approach is only It is an embodiment of the present invention, not a limitation of the present invention. In practical applications, the frame data of the previous frame output by the sample-and-hold circuit can actually be applied to various data processing circuits for image processing, and its implementation can be as shown in Figure 7 instead of the aforementioned The data driving circuit 30 is limited.

In FIG. 7 , the sampling voltage V1 output by the sampling and holding unit 330 represents the frame data of the previous frame. Therefore, the digital signal D3 generated by digitizing the sampling voltage V1 also represents the information of the previous frame. In this embodiment, the digital signal D3 is input to an external image processing unit 350. In this way, the image processing unit 350 can use the information of the previous frame (ie digital signal D3) and the received current frame information (ie Digital signal D1>, to carry out corresponding image processing. Therefore, a data driving circuit with an existing structure can directly generate a corresponding driving voltage VOUT according to the digital signal D4 output by the image processing unit 350 to drive the display panel and display corresponding images.

In summary, by reading back the pixel voltage of the display panel of the hold-type display, the present invention can directly use the display panel of the hold-type display as a frame buffer, so as to improve the prior art that requires an additional memory to store the previous frame data. The problem. In this way, the use of memory required by the system can be greatly reduced, thereby effectively saving costs.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (19)

1. A data drive circuit for a hold display, comprising: a video data input end, used to receive a video data; a driving voltage output terminal, used to output a driving voltage to the hold display; a sampling and holding unit, coupled to the output terminal of the driving voltage, used for sampling and holding the voltage of the output terminal of the driving voltage according to a sampling signal, so as to generate a sampling voltage; and A driving voltage generating unit, coupled to the video data input terminal, the driving voltage output terminal and the sample and hold unit, is used to process the video data according to a plurality of reference voltages, a polarity selection signal and the sampling voltage signal processing to output the driving voltage. 2. The data driving circuit according to claim 1, wherein the driving voltage generating unit comprises: a digital/analog conversion unit, coupled to the video data input terminal, for converting the video data into a second voltage in analog form according to the plurality of reference voltages; and A signal processing unit, coupled to the digital/analog conversion unit, the sampling and holding unit and the output terminal of the driving voltage, used for signal processing the second voltage according to the polarity selection signal and the sampling voltage, so as to Generate the drive voltage. 3. The data driving circuit as claimed in claim 2, wherein the signal processing unit is further configured to switch the polarity of the sampling voltage to a polarity corresponding to the second voltage according to the polarity selection signal. 4. The data driving circuit as claimed in claim 2, wherein the signal processing unit comprises a voltage operational amplifier. 5. The data driving circuit as claimed in claim 1, further comprising an analog/digital conversion unit, coupled between the sampling and holding unit and the driving voltage generating unit, for converting the sampling voltage to a digital The first numeric data of the form. 6 . The data driving circuit as claimed in claim 1 , wherein the driving voltage output by the driving voltage generating unit is used to drive the holding display, and overdrive is realized by reading back pixel voltages of the holding display. 7 . The data driving circuit as claimed in claim 1 , wherein the driving voltage output by the driving voltage generating unit is used to drive the holding display, and de-interlacing is realized by reading back pixel voltages of the holding display. 8 . The data driving circuit as claimed in claim 1 , wherein the driving voltage output by the driving voltage generating unit is used to drive the hold display to implement motion compensation by reading back pixel voltages of the hold display. 9. The data driving circuit as claimed in claim 1, wherein the driving voltage output by the driving voltage generation unit is used to drive the holding display, and realizes the frame transfer rate by reading back the pixel voltage of the holding display convert. 10. The data driving circuit as claimed in claim 1, wherein the plurality of reference voltages are generated according to a gamma curve. 11. A driving method for a hold display, comprising: receiving a video data; According to a sampling signal, sampling and holding the voltage of a driving voltage output terminal to generate a sampling voltage; performing signal processing on the video data according to a plurality of reference voltages, a polarity selection signal and the sampling voltage to output a driving voltage; and outputting the driving voltage to the holding display. 12. The driving method according to claim 11, wherein, according to the plurality of reference voltages, the polarity selection signal and the sampling voltage, performing signal processing on the video data to output the driving voltage comprises: converting the video data into a second voltage in analog form according to the plurality of reference voltages; and Signal processing is performed on the second voltage according to the polarity selection signal and the sampling voltage to generate the driving voltage. 13. The driving method according to claim 12, wherein, according to the polarity selection signal and the sampling voltage, performing signal processing on the second voltage to generate the driving voltage further comprises: according to the polarity selection signal, the The polarity of the sampling voltage is switched to the polarity corresponding to the second voltage. 14. The driving method according to claim 11, wherein, according to the sampling signal, sampling and holding the voltage of the driving voltage output terminal to generate the sampling voltage further comprises converting the sampling voltage to a The first numeric data in numeric form. 15. The driving method as claimed in claim 11, wherein outputting the driving voltage to the hold display for driving the hold display is achieved by reading back pixel voltages of the hold display to achieve overdrive. 16. The driving method as claimed in claim 11, wherein outputting the driving voltage to the hold display is to implement de-interlacing by reading back pixel voltages of the hold display. 17. The driving method as claimed in claim 11, wherein outputting the driving voltage to the hold display is to implement motion compensation by reading back pixel voltages of the hold display. 18. The driving method as claimed in claim 11, wherein outputting the driving voltage to the hold display is to realize frame rate conversion by reading back pixel voltages of the hold display. 19. The driving method as claimed in claim 11, wherein the plurality of reference voltages are generated according to a gamma curve.

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