JP7114875B2 - ELECTRO-OPTICAL DEVICE, ELECTRO-OPTICAL DEVICE CONTROL METHOD, AND ELECTRONIC DEVICE - Google Patents

Description

The present invention relates to an electro-optical device such as a liquid crystal device, a control method for the electro-optical device, and an electronic device.

In an electro-optical device that displays an image using a liquid crystal element, a data voltage that specifies the gradation of each pixel is supplied to each pixel through a data line, so that the transmittance of the liquid crystal provided in each pixel is stored as data. The transmittance is controlled according to the voltage, thereby displaying the gradation specified for each pixel.

By the way, when the supply of the data voltage to each pixel is insufficient, such as when the time to supply the data voltage to each pixel cannot be sufficiently ensured, each pixel accurately displays the gradation specified by the image signal. display quality may deteriorate. Conventionally, the following countermeasures have been taken to deal with the problem of deterioration in display quality due to insufficient writing of data voltage to pixels. For example, in Patent Document 1, a precharge voltage close to the data voltage is output to each pixel and data line before the timing of supplying the data voltage, thereby facilitating writing of the data voltage to each pixel. techniques have been proposed.

The precharge voltage is output to all data lines in advance before the data voltage is output. The period during which the precharge voltage is output is called a precharge period, and the writing of the data voltage is assisted by writing a predetermined precharge voltage during this precharge period. In addition, for example, it has the effect of suppressing vertical crosstalk that is conspicuously visible when a window pattern display is displayed on a background of halftone gradation.

WO 99/04385

By the way, the number of transistors connected to one scanning line tends to increase as the resolution of electro-optical devices increases. As a result, the parasitic capacitance associated with the scanning lines increases, and the driving load on the scanning lines increases. Therefore, when the resolution of the electro-optical device is increased, the response speed of the scanning line becomes slower, and the waveform of the scanning signal supplied to the scanning line becomes gentler. As a result, when the precharge operation for N rows (N is a natural number) is started, in the N−1 scanning lines selected immediately before the N scanning lines, the N−1 scanning lines may not have been selected, and an unintended voltage may have been written to the pixels corresponding to the N−1 scanning lines.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce unintended writing of signals to pixels by a precharge operation even when the driving load of a scanning line increases. be one.

In one aspect of the electro-optical device of the present invention to solve the above-described problems, a plurality of scanning lines, a plurality of data lines, and the intersections of the plurality of scanning lines and the plurality of data lines are provided respectively corresponding to the intersections of the plurality of scanning lines and the plurality of data lines. a pixel having a pixel transistor for taking in the voltage of the data line; after outputting a precharge voltage, outputting a data voltage having a magnitude corresponding to a gradation to be displayed; A data line driving section for inverting the polarity of the voltage at a predetermined cycle, and a scanning signal voltage for controlling the timing of outputting the precharge voltage to the data line and selecting one of the plurality of scanning lines is controlled by the voltage of the scanning signal. The elapsed time from the start of the transition from the selection voltage that turns on the pixel transistor to the non-selection voltage that turns off the pixel transistor to the output of the precharge voltage to the data line is changed according to the polarity of the data voltage. and a control unit for

As the number of pixels connected to one scanning line increases, the parasitic capacitance associated with the scanning line increases. Therefore, the waveform of the scanning signal becomes gentle. Therefore, even if the waveform of the scanning signal supplied to the scanning line switches from the selection voltage for turning on the pixel transistor to the non-selection voltage for turning off the pixel transistor, the voltage of the scanning line changes from the selection voltage to the non-selection voltage. Gradual change in voltage. Here, when the precharge voltage applied to the data line while the voltage of the scanning line is transitioning from the selection voltage to the non-selection voltage is lower than the voltage of the scanning line, the pixel transistor corresponding to the scanning line is turned on. As a result, there is a possibility that a voltage that should not be originally written is written to the pixel. According to the present invention, the elapsed time from when the voltage of the scanning signal starts transitioning from the selected voltage to the non-selected voltage to when the precharge voltage is output to the data line is changed according to the polarity of the data voltage. Even if the waveform of the scanning signal is dulled by the influence of the parasitic capacitance, by applying the precharge voltage to the data line, it is possible to suppress the turn-on of the pixel transistor that should be turned off.

In one aspect of the electro-optical device of the present invention, a plurality of scanning lines, a plurality of data lines, and a plurality of scanning lines are provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines. a pixel having a pixel transistor for capturing; a scanning line driving unit for generating a scanning signal for each of the plurality of scanning lines based on a start pulse and a clock signal; a data line driving unit for outputting a data voltage having a magnitude corresponding to a desired gradation and inverting the polarity of the data voltage with a predetermined voltage as a reference at a predetermined cycle; and start timing for outputting the precharge voltage to the data line. a selection unit for outputting the precharge voltage and the data voltage output from the data line driving unit to a predetermined data line based on a selection signal specifying the start pulse and the clock signal for the scanning line driving section, outputs the selection signal to the selection section, and calculates the elapsed time from the timing at which the clock signal transitions from one level to the other level to the start timing specified by the selection signal; and a control unit that changes according to the polarity of the voltage.

According to this aspect, the elapsed time from the timing at which the clock signal transitions from one level to the other level to the start timing specified by the selection signal is changed according to the polarity of the data voltage. Even if the waveform of the scanning signal is blunted under the influence of , by applying the precharge voltage to the data line, it is possible to suppress the turn-on of the pixel transistor that should be turned off.

In one aspect of the electro-optical device of the present invention, a plurality of scanning lines, a plurality of data lines, and a plurality of scanning lines are provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines. A pixel having a pixel transistor for capturing, a scanning line driving section for outputting a scanning signal to each of the plurality of scanning lines based on a start pulse, a clock signal, and an output control signal, and outputting a precharge voltage. a data line driving unit for outputting a data voltage having a magnitude corresponding to a gradation to be displayed and inverting the polarity of the data voltage with a predetermined voltage as a reference at a predetermined cycle; and applying the precharge voltage to the data line. a selection unit for outputting the precharge voltage and the data voltage output from the data line driving unit to a predetermined data line based on a selection signal specifying output start timing; and the start pulse and the clock signal. outputting the output control signal to the scanning line driving section; outputting the selection signal to the selection section; and a control unit that changes the elapsed time until the start timing according to the polarity of the data voltage.

According to this aspect, the elapsed time from the timing at which the output control signal transitions from one level to the other level to the start timing specified by the selection signal is changed according to the polarity of the data voltage. Even if the waveform of the scanning signal is blunted under the influence of , by applying the precharge voltage to the data line, it is possible to suppress the turn-on of the pixel transistor that should be turned off.

In one aspect of the electro-optical device described above, the output control signal becomes active during a period in which any one of the scanning signals output to each of the plurality of scanning lines is active, and the output control signal changes from one level to The timing of transition to the other level is preferably the timing of transition of the output control signal from active to inactive. In this case, by adjusting the period during which the output control signal is inactive according to the polarity of the data voltage, it is possible to suppress the turn-on of the pixel transistor that should be turned off.

In one aspect of the electro-optical device described above, it is preferable that the precharge voltage when the data voltage is positive is higher than the precharge voltage when the data voltage is negative. If the data voltage has a positive polarity, a data voltage exceeding the predetermined voltage is applied to the data line. On the other hand, when the data voltage is negative, a data voltage lower than the predetermined voltage is applied to the data line. Therefore, by changing the precharge voltage according to the polarity of the data voltage, it becomes easier to write the data voltage to the pixel.

In one aspect of the above-described electro-optical device, it is preferable that the control unit makes the elapsed time when the data voltage has negative polarity longer than the elapsed time when the data voltage has positive polarity. In order for the pixel transistor to remain off even when the precharge voltage is applied to the data line, the voltage of the scanning line must be lower than the precharge voltage. Here, the precharge voltage when the data voltage is negative is lower than the precharge voltage when the data voltage is positive. According to the present invention, when the data voltage has a negative polarity, the elapsed time is set longer than when the data voltage has a positive polarity. , it becomes possible to delay the timing of applying the precharge voltage until the pixel transistor can be kept off.

In one aspect of the electro-optical device described above, the pixel includes a storage capacitor having one terminal connected to the pixel transistor and the other terminal connected to a capacitor line. It is preferable that the period during which the precharge voltage is output to the data line is shorter than the period during which the precharge voltage is output to the data line when the data voltage is positive.

As a result of the precharge operation, the voltage of the capacitance line changes due to the coupling capacitance with the data line. Although the voltage of the capacitor line converges to a constant voltage, it is preferable to write the data voltage after the voltage of the capacitor line converges to a constant voltage from the viewpoint of displaying accurate gradation. When the precharge voltage is written from the state in which the data voltage of negative polarity is written, the potential fluctuation of the capacity line caused by the coupling capacitance with the data line is more precharged from the state in which the data voltage of positive polarity is written. Less than writing voltage. According to the present invention, the period during which the precharge voltage corresponding to the data voltage of the negative polarity is output to the data line is shorter than the period during which the precharge voltage corresponding to the data voltage of the positive polarity is output to the data line. It is possible to set a long write period for writing the data voltage while ensuring the period until the voltage of .

In one aspect of the electro-optical device described above, it is preferable that the timing at which the data line driving section starts outputting the precharge voltage is before the start timing specified by the selection signal. According to this aspect, even if the precharge voltage is output from the data line driving section, the selection section limits the period during which the precharge voltage is output to the data line.

In one aspect of the electro-optical device described above, a period during which the data line driving section outputs the precharge voltage, and a period during which the selection signal is active for outputting the precharge voltage to the predetermined data line. may substantially match. According to this aspect, the period during which the data line driving section outputs the precharge voltage is substantially matched with the period during which the selection signal is active, so that the power consumption of the data line driving section can be reduced.

Next, one aspect of an electronic device according to the present invention includes the above-described electro-optical device according to the present invention. Liquid crystal displays, projectors, and the like correspond to such electronic devices.

Next, in one aspect of the method for controlling an electro-optical device according to the present invention, a plurality of scanning lines, a plurality of data lines, and a plurality of scanning lines are provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines. , a pixel having a pixel transistor for taking in the voltage of the data line, and a method of controlling an electro-optical device comprising: outputting a precharge voltage to the data line; outputting a data voltage having a magnitude to the data line, inverting the polarity of the data voltage with a predetermined voltage as a reference at a predetermined cycle, controlling the timing of outputting the precharge voltage to the data line, and performing the plurality of scanning operations; outputting the precharge voltage to the data line after the voltage of the scanning signal for selecting one of the lines begins to transition from a select voltage that turns on the pixel transistor to a non-select voltage that turns off the pixel transistor; The elapsed time until is changed according to the polarity of the data voltage.

In one aspect of the method for controlling an electro-optical device according to the present invention, a plurality of scanning lines, a plurality of data lines, and the intersections of the plurality of scanning lines and the plurality of data lines are provided corresponding to each other, and a pixel having a pixel transistor for taking in the voltage of the data line, the method for controlling an electro-optical device comprising: outputting a precharge voltage to the data line; A scanning signal for outputting a data voltage of the same value to the data line, inverting the polarity of the data voltage with a predetermined voltage as a reference at a predetermined cycle, and controlling the pixel transistor to be on or off based on a start pulse and a clock signal. is generated and output to the plurality of scanning lines, and the elapsed time from the timing when the clock signal transitions from one level to the other level until the precharge voltage is output to the data line is the data voltage. Change according to polarity.

In one aspect of the method for controlling an electro-optical device according to the present invention, a plurality of scanning lines, a plurality of data lines, and the intersections of the plurality of scanning lines and the plurality of data lines are provided corresponding to each other, and a pixel having a pixel transistor for taking in the voltage of the data line, the method for controlling an electro-optical device comprising: outputting a precharge voltage to the data line; The data voltage is output to the data line, the polarity of the data voltage is inverted at predetermined intervals with respect to the predetermined voltage, and the pixel transistor is turned on or off based on the start pulse, the clock signal, and the output control signal. A scanning signal to be controlled is generated and output to the plurality of scanning lines, and an elapsed time from the timing when the output control signal transitions from one level to the other level until the precharge voltage is output to the data line. is changed according to the polarity of the data voltage.

1 is an explanatory diagram of an electro-optical device according to an embodiment of the invention; FIG. 2 is a block diagram showing the configuration of the electro-optical device according to the embodiment; FIG. 3 is a circuit diagram showing the configuration of a pixel; FIG. 3 is a block diagram showing the configuration of a scanning line driving circuit; FIG. 4 is a diagram showing operation timings of a scanning line driving circuit; FIG. 3 is a block diagram showing the configuration of a data line drive circuit; FIG. FIG. 5 is a diagram showing an example of supply timing of a precharge voltage during positive polarity driving; FIG. 5 is a diagram showing an example of supply timing of a precharge voltage during negative driving. FIG. 5 is a diagram showing an example of supply timing of a precharge voltage during negative driving. 1 is a circuit diagram of a pixel circuit including a capacitor line; FIG. FIG. 10 is a diagram showing the relationship between the movement of the potential of the data line and the movement of the potential of the capacity line during positive-polarity driving; FIG. 10 is a diagram showing the relationship between the movement of the potential of the data line and the movement of the potential of the capacity line during negative driving. FIG. 10 is a diagram showing an example of supply timing of a precharge voltage according to the second embodiment of the present invention; It is a figure which shows an example of the supply timing of the precharge voltage in 3rd Embodiment of this invention. It is a figure which shows an example of the supply timing of the precharge voltage in the same embodiment. It is an explanatory view showing an example of electronic equipment. FIG. 11 is an explanatory diagram showing another example of an electronic device; FIG. 11 is an explanatory diagram showing another example of an electronic device;

<First Embodiment>
A first embodiment of the present invention will be described with reference to FIGS. 1 to 10. FIG. FIG. 1 is a diagram showing the configuration of a signal transmission system for an electro-optical device 1. As shown in FIG. As shown in FIG. 1, the electro-optical device 1 includes an electro-optical panel 100, a driving integrated circuit (driver IC) 200, and a flexible circuit board 300. It is connected to the mounted flexible circuit board 300 . The electro-optical panel 100 is connected to a host CPU device (not shown) through the flexible circuit board 300 and the driving integrated circuit 200 . The driving integrated circuit 200 is a device that receives an image signal and various control signals for driving control from the host CPU device via the flexible circuit board 300 and drives the electro-optical panel 100 via the flexible circuit board 300. be.

FIG. 2 is a block diagram showing the configuration of the electro-optical panel 100 and the driving integrated circuit 200. As shown in FIG. As shown in FIG. 2, the electro-optical panel 100 includes a pixel section 10, a scanning line driving circuit 22 as a scanning line driving section, and J demultiplexers 57[1] to 57[J] as selecting sections. (J is a natural number). The driving integrated circuit 200 includes a data line driving circuit 30 as a data line driving section, a control circuit 40 as a control section, and an analog voltage generating circuit 70 .

M scanning lines 12 and N data lines 14 that cross each other are formed in the pixel section 10 (M and N are natural numbers). A plurality of pixel circuits (pixels) PIX are provided corresponding to the intersections of the scanning lines 12 and the data lines 14, and are arranged in a matrix of M rows (vertical)×N columns (horizontal).

FIG. 3 is a circuit diagram of each pixel circuit PIX. As shown in FIG. 3, each pixel circuit PIX includes a liquid crystal element 60, a storage capacitor Cst, and a pixel transistor Tr composed of a TFT (thin film transistor). The liquid crystal element 60 is an electro-optical element composed of a pixel electrode 62 and a common electrode 64 facing each other and a liquid crystal 66 between the electrodes. The transmittance (display gradation) of the liquid crystal 66 changes according to the voltage applied between the pixel electrode 62 and the common electrode 64 .
The storage capacitor Cst is provided in parallel with the liquid crystal element 60 . One terminal of the holding capacitor Cst is connected to the pixel transistor Tr, and the other terminal is connected to the common electrode 64 via a capacitor line (not shown). The pixel transistor Tr is composed of, for example, an N-channel transistor whose gate is connected to the scanning line 12, is provided between the liquid crystal element 60 and the data line 14, and is electrically connected (conduction/non-conduction) between the two. to control. By setting the scanning signal G[m] to the selection potential, the pixel transistors Tr in each pixel circuit PIX on the m-th row are simultaneously turned on (m is a natural number from 1 to M).

When the scanning line 12 corresponding to the pixel circuit PIX is selected and the pixel transistor Tr of the pixel circuit PIX is controlled to be turned on, the liquid crystal element 60 receives the data signal supplied from the data line 14 to the pixel circuit PIX. A voltage corresponding to D[n] is applied (n is a natural number from 1 to J). As a result, the transmittance of the liquid crystal 66 of the pixel circuit PIX is set according to the data signal D[n]. When a light source (not shown) is turned on (lit) and light is emitted from the light source, the light passes through the liquid crystal 66 of the liquid crystal element 60 included in the pixel circuit PIX and travels toward the viewer. That is, when a voltage corresponding to the data signal D[n] is applied to the liquid crystal element 60 and the light source is turned on, the pixel corresponding to the pixel circuit PIX is turned on according to the data signal D[n]. It will display gradation.

After the data voltage corresponding to the data signal D[n] is applied to the liquid crystal element 60 of the pixel circuit PIX, ideally, when the pixel transistor Tr is turned off, the data voltage corresponding to the data signal D[n] is applied. is retained. Therefore, ideally, each pixel displays a gradation corresponding to the data signal D[n] during the period after the pixel transistor Tr is turned on until it is turned on again.

As shown in FIG. 3, a capacitance Ca is parasitic between the data line 14 and the pixel electrode 62 (or between the data line 14 and the wiring electrically connecting the pixel electrode 62 and the pixel transistor Tr). do. Therefore, while the pixel transistor Tr is in the OFF state, the potential fluctuation of the data line 14 may propagate to the pixel electrode 62 via the capacitor Ca, causing the data voltage of the liquid crystal element 60 to fluctuate.

A common voltage LCCOM, which is a constant voltage, is supplied to the common electrode 64 via a common line (not shown). As the common voltage LCCOM, a voltage of about -0.5 V with respect to the center voltage of the amplitude of the data signal D[n] is used. This is due to the characteristics of the pixel transistor Tr, etc., the parasitic capacitance between the scanning line 12 and the pixel electrode 62, and the switch 58 that constitutes the demultiplexer 57. FIG. In this embodiment, the pushdown voltage is assumed to be zero for the sake of simplicity of explanation.

In this embodiment, in order to prevent so-called burn-in, polarity reversal driving is employed in which the polarity of the voltage applied to the liquid crystal element 60 is reversed every vertical scanning period (1 V). In this example, the level of the data signal D[n] supplied to the pixel circuit PIX via the data line 14 is inverted with respect to the center voltage of the data signal D[n] every vertical scanning period (1 V). However, the period for reversing the polarity can be set arbitrarily, and may be a natural number multiple of one vertical scanning period V, for example. In this embodiment, when the voltage of the data signal D[n] is high with respect to the central voltage (predetermined voltage), the positive polarity is assumed, and the voltage of the data signal D[n] is low with respect to the central voltage. The case of becoming negative polarity.

Returning to FIG. External signals such as a vertical synchronizing signal Vs that defines the vertical scanning period V, a horizontal synchronizing signal Hs that defines the horizontal scanning period H, and a dot clock signal DCLK are input to the control circuit 40 from an external host CPU device (not shown). be. The control circuit 40 synchronously controls the scanning line driving circuit 22 and the data line driving circuit 30 based on these signals. Under this synchronous control, the scanning line driving circuit 22 and the data line driving circuit 30 cooperate with each other to control the display of the pixel section 10 . The control circuit 40 also outputs a start pulse SP, a clock signal CK, and an output control signal EN to the scanning line driving circuit 22 . One period of the clock signal CK in this example is the horizontal scanning period H. FIG. When the output control signal EN becomes active (high level in this example), it permits the scanning signals G[1] to G[M] to become active. When the output control signal EN becomes inactive (low level in this example), it inhibits the scanning signals G[1] to G[M] from becoming active. The output control signal EN becomes active during a period in which any one of the scanning signals G[1] to G[M] output to each of the plurality of scanning lines 12 is active.
Normally, display data forming one display screen is processed in frame units, and this processing period is one frame period (1F). The frame period F corresponds to the vertical scanning period V when one display screen is configured by one vertical scanning.

The scanning line driving circuit 22 generates scanning signals G[ 1 ] to G[M] based on the start pulse SP, clock signal CK and output control signal EN, and outputs them to each of the M scanning lines 12 . FIG. 4A shows a circuit diagram of the scanning line driving circuit 22, and FIG. 4B shows a timing chart of the scanning line driving circuit 22. As shown in FIG.

As shown in FIG. 4A, the scanning line driving circuit 22 includes a shift register 23, M AND circuits 24[1] to 24[M], and M level shifters LS[1] to LS[M]. Prepare.
The shift register 23 shifts the start pulse SP according to the clock signal CK to generate shift signals SR[1] to SR[M]. The shift register 23 can be configured by connecting D flip-flops in multiple stages, for example. The m-th shift signal SR[m] is supplied to one input terminal of the AND circuit 24[m]. An output control signal EN is supplied to the other input terminal of the AND circuit 24[m]. The AND circuit 24[m] calculates the AND of the shift signal SR[m] and the output control signal EN. The level shifter LS[m] level-shifts the output signal of the AND circuit 24[m] and outputs the scanning signal G[m] to the m-th scanning line 12 . Although one output control signal EN is used in this example, a plurality of output control signals EN may be used due to problems such as signal response. For the sake of explanation, it is assumed that there is no signal delay due to the AND circuit 24[m] and the level shifter LS[m].

As a result, the scanning line driving circuit 22 generates the scanning signals G[1] to G[M] for each scanning line 12 within the vertical scanning period V every horizontal scanning period (1H) in synchronization with the horizontal synchronizing signal Hs. sequentially active. However, in this example, the scanning signals G[1] to G[M] are selected voltages during selected periods in one horizontal scanning period, and are not selected voltages during other non-selected periods. When the selection voltage is supplied to the pixel transistor Tr, the pixel transistor Tr is turned on, and when the non-selection voltage is supplied to the pixel transistor Tr, the pixel transistor Tr is turned off.

Here, the voltage of the scanning signal G[m] corresponding to the m-th row becomes the selection voltage, and the selection period during which the scanning line 12 corresponding to the row is selected is the N pixel circuits PIX of the m-th row. Each pixel transistor Tr is turned on. As a result, the N data lines 14 are electrically connected to the respective pixel electrodes 62 of the N pixel circuits PIX in the m-th row via the respective pixel transistors Tr.

In the present embodiment, the N data lines 14 in the pixel section 10 are divided into J wiring blocks B[1] to B[J] (J=N/ 4). In other words, the data lines 14 are grouped for each wiring block B. FIG. The demultiplexers 57[1] to 57[J] correspond to the J wiring blocks B[1] to B[J], respectively. As will be described later, in this embodiment, the data lines 14 are divided into four lines, so the data signal D[n] includes data voltages for four pixels.

Each of the demultiplexers 57[j] as a selection unit is composed of four switches 58[1] to 58[4] (j is a natural number from 1 to J). In each demultiplexer 57[j], one contact of each of the four switches 58[1]-58[4] is commonly connected. A common connection point of one contact of each of the four switches 58[1] to 58[4] of the demultiplexer 57[j] is connected to the J VID signal lines 15, respectively. The J VID signal lines 15 are connected to the data line driving circuit 30 of the driving integrated circuit 200 via the flexible circuit board 300 . The switches 58[1] to 58[4] are composed of, for example, N-channel transistors.
Further, in each demultiplexer 57[j], the other contact of each of the four switches 58[1] to 58[4] is connected to the wiring block B[j] corresponding to the demultiplexer 57[j]. ] are connected to four data lines 14, respectively.

The four switches 58[1] to 58[4] of each demultiplexer 57[j are turned on/off by four selection signals S1 to S4, respectively. These four selection signals S 1 to S 4 are supplied from the control circuit 40 of the driving integrated circuit 200 via the flexible circuit board 300 . The selection signals S1 to S4 specify the start timing of outputting the precharge voltage to the data line 14. FIG. Here, for example, when one selection signal S1 is at active level and the other three selection signals S2 to S4 are at inactive level, J switches 58 [ 1] is turned on. Therefore, each of the demultiplexers 57[j] distributes the data signals D[1] to D[J] on the J VID signal lines 15 to the first wiring blocks B[1] to B[J]. Output to the data line 14 respectively. Similarly, the data signals D[1] to D[J] on the J VID signal lines 15 are applied to the second, third and fourth data of the wiring blocks B[1] to B[J]. Each output on line 14 .

The control circuit 40 has a frame memory and has at least a memory space of M×N bits corresponding to the resolution of the pixel section 10, and stores display data input from an external host CPU device (not shown) in units of frames. ·Hold. Here, the display data defining the gradation of the pixel section 10 is, for example, data of 64 gradations composed of 6 bits. The display data read out from the frame memory is serially transferred as an image signal to the data line driving circuit 30 via a 6-bit bus.
Note that the control circuit 40 may be configured to include a line memory for at least one line. In this case, display data for one line is stored in the line memory, and the display data is transferred to each pixel as an image signal.

A data line driving circuit 30 as a data line driving section cooperates with the scanning line driving circuit 22 to output data signals to the data lines 14 to be supplied to each pixel row to which data is to be written. The data line driving circuit 30 generates a latch signal based on the selection signals S1 to S4 output from the control circuit 40, and sequentially latches the precharge signal and N 6-bit image signals supplied as serial data. . The image signals are grouped as time-series signals every four pixels.

FIG. 5 is a block diagram showing the configuration of the data line driving circuit 30. As shown in FIG. The data line drive circuit 30 includes a D/A (Digital to Analog) conversion circuit 301, a voltage amplification section 302, and a polarity inversion section 303, as shown in FIG. The D/A conversion circuit 301 performs D/A conversion based on the grouped image signals and the analog voltage generated by the analog voltage generation circuit 70 and having the voltage value set by the polarity inverting section 303 . Furthermore, the voltage amplifying section 302 amplifies the voltage generated by the D/A conversion to generate a data signal having a predetermined analog voltage. As a result, the image signal time-series in units of four pixels is converted into a data signal D[n] having a predetermined data voltage. Also, the precharge signal is similarly converted into a precharge data signal PD having a predetermined precharge voltage, and a set of the precharge data signal PD and the data signal D[n] for four pixels is this They are supplied to each VID signal line 15 in order as the voltage of the data signal D[n] and the precharge voltage.

The polarity inversion unit 303 inverts the polarity of the voltage of the data signal D[n] every vertical scanning period V. FIG. Specifically, the polarity inverting unit 303 inverts the voltage of the data signal D[n] with respect to the center voltage of the data signal D[n] every vertical scanning period V. FIG. However, the period for inverting the polarity can be set arbitrarily, and may be a natural number multiple of the vertical scanning period V, for example. In the present embodiment, when the data signal D[n] has a high voltage with respect to the central voltage, it is positive, and when the data signal D[n] has a low voltage with respect to the central voltage, it has a negative polarity. . The polarity inverting unit 303 inverts the polarity of the data voltage at regular intervals.

Further, the polarity inverting unit 303 outputs the first precharge voltage Vpp as the precharge voltage when the data voltage has a positive polarity, and outputs the second precharge voltage Vpp as the precharge voltage when the data voltage has a negative polarity. Output voltage Vpm. That is, the voltage value of the precharge voltage when the data voltage is positive differs from the voltage value of the precharge voltage when the data voltage is negative. This is because the range of data voltage for each polarity is different, and therefore the optimum voltage for obtaining both the effect of preliminary writing and the effect of suppressing vertical crosstalk is different. In the following description, when there is no need to distinguish between the first precharge voltage Vpp and the second precharge voltage Vpm, they are simply referred to as precharge voltages.

The switches 58[1] to 58[4] of the demultiplexer 57[j] are conductively controlled (turned on/off) by selection signals S1 to S4 output from the control circuit 40, and turned on at a predetermined timing. During the application period of the precharge signal, conduction is controlled by the selection signals S1 to S4 output from the control circuit 40, and the switches 58[1] to 58[4] of the demultiplexer 57[j] are turned on all at once. do.
As a result, in one horizontal scanning period (1H), the precharge data signal PD supplied to each VID signal line 15 and the data signal D[n] for four pixels are connected to the switches 58[1] to 58[4]. are output to the data line 14 in time series.

This embodiment employs polarity reversal driving. Precharging means writing a predetermined voltage to the data line 14 before writing the data voltage of the data signal D[n] to the data line 14 . As described above, the precharge voltage when the polarity of the data voltage is positive is the first precharge voltage Vpp, and the precharge voltage when the polarity of the data voltage is negative is the second precharge voltage Vpm. be. For example, the first precharge voltage Vpp is set to 4.0V and the center voltage Vc is set to 7.5V in positive polarity driving. Common voltage LCCOM is set to 7.5V. The second precharge voltage Vpm in negative drive is set to 2.0V. That is, the first precharge voltage Vpp when the data voltage is positive is higher than the second precharge voltage Vpm when the data voltage is negative.
In this embodiment, the control circuit 40 controls the supply timing of the precharge data signal PD during negative polarity driving in the polarity inversion driving to be delayed from the supply timing of the precharge data signal PD during positive polarity driving. ing.

Here, the relationship between the scanning signal G[m] supplied to the m-th row scanning line 12 and the supply timing of the precharge voltage will be described with reference to FIGS. 6 to 10. FIG. FIG. 6 is a diagram showing supply timing of the first precharge voltage Vpp during positive polarity driving. FIG. 7A is a diagram showing supply timing of the second precharge voltage Vpm during negative driving. FIG. 8 is a circuit diagram of the pixel circuit PIX including the capacitor line 16. As shown in FIG. FIG. 9 is a diagram showing the relationship between the potential movement of the data line 14 and the potential movement of the capacity line 16 during positive polarity driving. FIG. 10 is a diagram showing the relationship between the potential movement of the data line 14 and the potential movement of the capacity line 16 during negative driving.

As shown in FIG. 6, the scanning signal G[m] supplied to the m-th scanning line 12 becomes the selection voltage VGH for selecting the m-th scanning line 12 during the selection period, and the m-th scanning line 12 during the non-selection period. It is switched to a non-selection voltage VGL (0V) for non-selecting the scanning line 12 of the row. However, in the high-resolution electro-optical panel 100 with a large number of pixels as in this embodiment, the parasitic capacitance of the scanning lines 12 increases. As shown in FIG. 8, the scanning line 12 has a capacitance C2 between the scanning line 12 and the capacitance line 16 and a capacitance C3 between the scanning line 12 and the data line 14 . Therefore, as the number of pixels increases, the parasitic capacitance of each scanning line 12 increases. Therefore, as shown in FIG. 6, at timing t0 at the end of the m-th horizontal scanning period, the voltage of the scanning signal G[m] does not reach the non-selection voltage VGL (0 V), and the selection voltage VGH is changed to the non-selection voltage. It is the voltage during the transition to the selection voltage VGL (0V).

During positive polarity driving, even if the first precharge voltage Vpp is supplied to the data line 14 at timing t0, which is the end of the m-th horizontal scanning period, the voltage of the scanning signal G[m] at timing t0 is the first voltage. It has a value smaller than the precharge voltage Vpp. Therefore, even if the precharge voltage Vpp is supplied to the data line 14 at the timing t0, the gate-source voltage Vgs of the pixel transistor Tr of the pixel circuit PIX becomes a negative value. Therefore, the pixel transistor Tr in the m-th row is turned off at timing t0. Therefore, even if the first precharge voltage Vpp is supplied to the data line 14 at timing t0, which is the start of the (m+1)th horizontal scanning period, the pixel transistor Tr of the pixel circuit PIX corresponding to the mth row scanning line 12 is It does not turn on.

However, during negative driving, as shown in FIG. 7A, when the second precharge voltage Vpm is supplied to the data line 14 at timing t0, which is the end of the m-th horizontal scanning period, the timing of the scanning signal G[m] is reduced. The voltage during the transition at t0 is greater than the second precharge voltage Vpm. Therefore, when the second precharge voltage Vpm is supplied to the data line 14 at the timing t0, the pixel transistor Tr of the pixel circuit PIX corresponding to the m-th scanning line 12 is turned on. As a result, the second precharge voltage Vpm supplied before writing the data voltage corresponding to the gradation of the pixel circuit PIX corresponding to the scanning line 12 of the (m+1)th row is applied to the pixel circuit corresponding to the scanning line 12 of the (m+1)th row. The data voltage written to the PIX will fluctuate, degrading the image quality.

Therefore, in the present embodiment, as shown in FIG. 7A, in the (m+1)-th horizontal scanning period, the supply timing of the second precharge voltage Vpm to the data line 14 is supplied to the m-th row scanning line 12. The control circuit 40 turns on the selection signals S1 to S4 so that the voltage of the scanning signal G[m] reaches the non-selection voltage VGL at timing t1. That is, in this embodiment, the supply timing of the second precharge voltage Vpm during negative driving is delayed from the timing t0, which is the timing of the end of the m-th horizontal scanning period. By controlling in this way, the voltage of the scanning signal G[m] becomes a value smaller than the second precharge voltage Vpm at the timing t1. Therefore, even if the second precharge voltage Vpm is supplied to the data line 14 at timing t1, the pixel transistor Tr of the pixel circuit PIX corresponding to the scanning line 12 of the m-th row does not turn on. As a result, the second precharge voltage Vpm supplied before writing the data voltage corresponding to the gradation of the pixel circuit PIX corresponding to the scanning line 12 of the (m+1)th row is applied to the pixel circuit corresponding to the scanning line 12 of the (m+1)th row. Good display quality can be maintained without changing the data voltage written to the PIX.
In other words, the control circuit 40 reduces the precharge voltage after the scanning signal G[m] output to the m-th row scanning line 12 starts transitioning from the selection voltage VGH to the non-selection voltage VGL at the timing tx. The elapsed time until output to the data line 14 is changed according to the polarity of the data voltage.

Here, at the timing tx at which the scanning signal G[m] output to the m-th row scanning line 12 starts transitioning from the selection voltage VGH to the non-selection voltage VGL, the output control signal EN transitions from active to inactive. coincides with the timing tde. That is, the control circuit 40 controls the timing from when the output control signal EN transitions from one level to the other (tu1 or tde shown in FIGS. 6 and 7A) until the precharge voltage is output to the data line 14. The time is changed according to the polarity of the data voltage.

More specifically, the control circuit 40 determines the elapsed time from the timing (tde shown in FIGS. 6 and 7A) at which the output control signal EN transitions from active to inactive until the precharge voltage is output to the data line 14. , are changing according to the polarity of the data voltage.
Further, the control circuit 40 sets the elapsed time Tm (see FIG. 7A) for writing the negative data voltage to the pixel circuit PIX longer than the elapsed time Tp (see FIG. 6) for writing the positive data voltage. is doing.

By the way, the timing t0 shown in FIG. 6 is the timing to start outputting the precharge voltage to the data lines 14 specified by the selection signals S1 to S4 when the data voltage is positive, and the timing t1 shown in FIG. This is the start timing of outputting the precharge voltage to the data lines 14 specified by the selection signals S1 to S4 when the data voltage is of positive polarity. Also, the m-th row scanning signal G[m] shown in FIGS. 6 and 7A is obtained by shifting the start pulse SP according to the clock signal CK. Therefore, the control circuit 40 precharges the data lines 14 specified by the selection signals S1 to S4 from the timing when the clock signal CK transitions from one level to the other (tu1 or td1 shown in FIGS. 6 and 7A). The elapsed time until the voltage output start timing is changed according to the polarity of the data voltage.

By controlling the supply of the precharge voltage as described above, the precharge period Tpm during negative drive shown in FIG. 7A becomes shorter than the precharge period Tpp during positive drive shown in FIG. Securing the precharge period is necessary for stabilizing the potential of the capacity line 16. However, the fluctuation of the potential of the capacity line during negative drive is smaller than the fluctuation of the potential of the capacity line during positive drive. , the precharge period Tpm during negative drive can be made shorter than the precharge period Tpp during positive drive, and good display quality can be maintained. By the way, the precharge voltage Vpm during negative drive is lower than the precharge voltage Vpp during positive drive. Therefore, when N-channel type transistors are used for the pixel transistor Tr of the pixel circuit PIX and the switches 58[1] to 58[4] of the demultiplexer 57[j], the gate voltage is higher during negative driving than during positive driving. It becomes an operation of increasing the voltage and writing the precharge voltage. This point is also the reason why the precharge period Tpp can be shortened.

In the example shown in FIG. 7A, the data line driving circuit 30 outputs the precharge voltage and demultiplexes the data line driving circuit 30 during at least the period from timing t0 at which the m-th horizontal scanning period starts to timing t2 at which the precharge period Tpm ends. The signal processor 57 outputs the precharge data signal PD output from the data line driving circuit 30 to the data line 14 during the precharge period Tpm. The timing t0 at which the data line driving circuit 30 starts outputting the precharge data signal PD is earlier than the start timing t1 specified by the selection signals S1 to S4.

As shown in FIG. 8, the data line 14 and the capacitance line 16 are coupled by a coupling capacitor C1, and the capacitance line 16 is also connected to the storage capacitance Cst of the pixel circuit PIX. Since the capacitance line 16 is connected to the power supply LCCOM via the external resistance Rex and the wiring resistance Rc of the capacitance line 16 itself, which are caused by various factors, it exhibits a potential behavior with a certain time constant. Therefore, when the potential of the data line 14 fluctuates, the potential of the capacitor line 16 also fluctuates based on the time constant. As shown in FIG. 9, during the precharge period Tpp during positive driving, the potential of the data line 14 varies from the maximum data voltage to the first precharge voltage Vpp. In this case, the potential of the capacitance line 16 once greatly drops from the common voltage LCCOM and fluctuates so as to return to the common voltage LCCOM again. However, as shown in FIG. 10, during the precharge period Tpm during negative drive, the voltage difference between the common voltage LCCOM, which is the maximum value of the data voltage, and the second precharge voltage Vpm is the same as the data voltage during positive drive. It is smaller than the voltage difference between the maximum voltage and the first precharge voltage Vpp. As a result, the fluctuation of the potential of the capacity line 16 during the precharge period Tpm during negative drive is smaller than the fluctuation of the potential of the capacity line 16 during the precharge period Tpp during positive drive. Therefore, even if the precharge period Tpm during negative drive is shorter than the precharge period Tpp during positive drive, the potential of the capacitor line 16 is stabilized, and by writing a desired data voltage into the pixel circuit PIX, , good display quality can be maintained.

In negative driving, as shown in FIG. 7AB, even if the second precharge voltage Vpm is supplied to the data line 14 at the timing t0 at the end of the m-th horizontal scanning period, the timing of the scanning signal G[m] is The voltage at t0 is higher than the second precharge voltage Vpm. Therefore, when the second precharge voltage Vpm is supplied to the data line 14 at the timing t0, the pixel transistor Tr of the pixel circuit PIX corresponding to the m-th scanning line 12 is turned on. As a result, the second precharge voltage Vpm supplied before writing the data voltage corresponding to the gradation of the pixel circuit PIX corresponding to the scanning line 12 of the (m+1)th row is applied to the pixel circuit corresponding to the scanning line 12 of the (m+1)th row. The data voltage written to the PIX will fluctuate, degrading the image quality.

Therefore, in the present embodiment, as shown in FIG. 7A, in the (m+1)-th horizontal scanning period, the supply timing of the second precharge voltage Vpm to the data line 14 is supplied to the m-th row scanning line 12. The control circuit 40 turns on the selection signals S1 to S4 so that the voltage of the scanning signal G[m] reaches the non-selection voltage VGL at timing t1. That is, in this embodiment, the supply timing of the second precharge voltage Vpm during negative driving is delayed from the timing t0, which is the timing of the end of the m-th horizontal scanning period. By controlling in this way, the voltage of the scanning signal G[m] becomes a value smaller than the second precharge voltage Vpm at the timing t1. Therefore, even if the second precharge voltage Vpm is supplied to the data line 14 at timing t1, the pixel transistor Tr of the pixel circuit PIX corresponding to the scanning line 12 of the m-th row does not turn on. As a result, the second precharge voltage Vpm supplied before writing the data voltage corresponding to the gradation of the pixel circuit PIX corresponding to the scanning line 12 of the (m+1)th row is applied to the pixel circuit corresponding to the scanning line 12 of the (m+1)th row. Good display quality can be maintained without changing the data voltage written to the PIX.
In other words, the control circuit 40 reduces the precharge voltage after the scanning signal G[m] output to the m-th row scanning line 12 starts transitioning from the selection voltage VGH to the non-selection voltage VGL at the timing tx. The elapsed time until output to the data line 14 is changed according to the polarity of the data voltage.

Here, at the timing tx at which the scanning signal G[m] output to the m-th row scanning line 12 starts transitioning from the selection voltage VGH to the non-selection voltage VGL, the output control signal EN transitions from active to inactive. coincides with the timing tde. That is, the control circuit 40 controls the timing from when the output control signal EN transitions from one level to the other (tu1 or tde shown in FIGS. 6 and 7A) until the precharge voltage is output to the data line 14. The time is changed according to the polarity of the data voltage.

More specifically, the control circuit 40 determines the elapsed time from the timing (tde shown in FIGS. 6 and 7A) at which the output control signal EN transitions from active to inactive until the precharge voltage is output to the data line 14. , are changing according to the polarity of the data voltage.
Further, the control circuit 40 sets the elapsed time Tm (see FIG. 7A) for writing the negative data voltage to the pixel circuit PIX longer than the elapsed time Tp (see FIG. 6) for writing the positive data voltage. is doing.

In the above example of negative polarity driving, as shown in FIG. 7A, the timing at which the precharge voltage is applied to the data line 14 in the (m+1)-th horizontal scanning period is from the timing t0 at which the (m+1)-th horizontal scanning period starts. It was delayed timing t1. The reason why the application of the precharge voltage to the data line 14 is started from the timing t1 is that the voltage of the m-th scanning line 12 at the timing t1 can keep the pixel transistor Tr off in relation to the precharge voltage. It is for Therefore, when the application of the precharge voltage to the data line 14 is started, if the voltage of the m-th scanning line 12 is a voltage that can keep the pixel transistor Tr off, the precharge voltage to the data line 14 is applied. The timing of starting the application may be earlier than the timing t1.

FIG. 7B is a diagram showing an example of supply timing of the precharge voltage during negative driving. The timing tx at which the scanning signal G[m] starts transitioning from the selection voltage VGH to the non-selection voltage VGL and the output control signal EN transitions from active to inactive is earlier than during positive polarity driving (see FIG. 6). is set. Therefore, during negative driving, the time for the voltage of the m-th scanning line 12 to drop can be longer than during positive driving.
That is, the control circuit 40 determines the elapsed time from the timing tx at which the output control signal EN transitions from active to inactive to the start timing at which the precharge voltage is output to the data lines designated by the selection signals S1 to S4 as the data voltage. Change according to polarity.

As described above, according to the present embodiment, during negative driving, the supply timing of the precharge voltage Vpm when selecting a certain scanning line 12 is set to the voltage of the scanning line 12 selected immediately before. Control is performed so that the timing reaches the voltage. By performing control in this manner, good display quality can be maintained without affecting the potential of the pixel circuit PIX for which writing has been completed.

<Second embodiment>
Next, a second embodiment of the invention will be described with reference to FIG. FIG. 11 is a diagram showing supply timing of the precharge voltage in this embodiment. In this embodiment, polarity inversion is performed not for each vertical scanning period (1V) but for each horizontal scanning period (1H). In the example shown in FIG. 11, positive driving is performed in the m-th horizontal scanning period, and negative driving is performed in the (m+1)-th horizontal scanning period. Even in this case, in the (m+1)-th horizontal scanning period in which negative driving is performed, the supply timing of the second precharge voltage Vpm is delayed from the timing t0, which is the end of the m-th horizontal scanning period. That is, the control circuit 40 sets the supply timing of the second precharge voltage Vpm to the timing at which the voltage of the scanning signal G[m] supplied to the m-th row scanning line 12 reaches the non-selection voltage VGL. The selection signals S1 to S4 are turned on.

As described above, even when polarity reversal is performed every horizontal scanning period, the supply timing of the second precharge voltage Vpm when selecting a certain scanning line 12 is changed immediately before negative polarity driving. Control is performed so that the voltage of the selected scanning line 12 reaches the unselected voltage at the timing. By performing control in this manner, good display quality can be maintained without affecting the potential of the pixel circuit PIX for which writing has been completed.

<Third embodiment>
Next, a third embodiment of the present invention will be described with reference to FIG. 12A. FIG. 12A is a diagram showing an example of supply timing of the second precharge voltage Vpm during negative drive in this embodiment. In this embodiment, polarity reversal is performed every horizontal scanning period (1 V), as in the first embodiment. As shown in FIG. 12A, also in this embodiment, the timing of turning on the selection signals S1 to S4 during the precharge period Tpm is set to the voltage of the scanning signal G[m] supplied to the scanning line 12 of the m-th row. reaches the non-selection voltage VGL at timing t1. Furthermore, in this embodiment, the control circuit 40 controls the data line drive circuit 30 to output the precharge data signal PD during the precharge period Tpm. That is, the period during which the data line driving circuit 30 outputs the precharge voltage substantially coincides with the period during which the selection signals S1 to S4 are active (high level in this example) to output the precharge voltage to the data lines 14. do.

As a result, in the present embodiment, the start timing of the precharge period Tpm during negative drive when a certain scanning line 12 is selected is set to the timing at which the voltage of the previously selected scanning line 12 reaches the non-selection voltage. Control is performed so that By performing control in this manner, good display quality can be maintained without affecting the potential of the pixel circuit PIX for which writing has been completed. Further, according to the present embodiment, the data line driving circuit 30 is precharged only during the precharge period Tpm during which the demultiplexer 57 is turned on and the data line 14 and the output terminal of the data line driving circuit 30 are connected. Output voltage. Therefore, by shortening the operating time of the data line driving circuit 30, power consumption can be reduced, and the amount of heat generated by the data line driving circuit 30 can be suppressed to improve reliability.

In the above example, as shown in FIG. 12A, the timing at which the precharge voltage is applied to the data line 14 in the m+1-th horizontal scanning period is delayed from the timing t0 at which the m+1-th horizontal scanning period starts. It was timing t1. However, as shown in FIG. 12B, the timing at which the precharge voltage is applied to the data line 14 in the (m+1)th horizontal scanning period may coincide with the timing t0 at which the (m+1)th horizontal scanning period starts.
In this case, the timing tx at which the scanning signal G[m] starts transitioning from the selection voltage VGH to the non-selection voltage VGL and the output control signal EN transitions from active to inactive is is also set before Therefore, during negative driving, the time for the voltage of the m-th scanning line 12 to drop can be longer than during positive driving.
That is, the control circuit 40 determines the elapsed time from the timing tx at which the output control signal EN transitions from active to inactive to the start timing at which the precharge voltage is output to the data lines designated by the selection signals S1 to S4 as the data voltage. Change according to polarity.

<Modification>
The present invention is not limited to each embodiment described above, and various modifications described below are possible, for example. Moreover, it goes without saying that each embodiment and each modification may be appropriately combined.

(1) In the above-described embodiment, an N-channel transistor is used as the pixel transistor Tr of the pixel circuit PIX. Then, when the voltage of the scanning line 12 selected immediately before reaches the non-selecting voltage, the start timing of the precharge period when selecting a certain scanning line 12 during negative polarity driving, which is one polarity of the polarity inversion driving, is set. I controlled the timing. However, the present invention is not limited to such embodiments. For example, a P-channel transistor is used as the pixel transistor Tr of the pixel circuit PIX, and the precharge voltage is set to the end of one horizontal scanning period in the scanning line 12 selected immediately before a certain scanning line 12 during positive polarity driving. It is also applicable when it is less than the voltage during the time transition. In this case, during positive polarity driving, the timing of supplying the precharge voltage when selecting a certain scanning line 12 is adjusted to the timing when the voltage of the scanning line 12 selected immediately before reaches the non-selected voltage. Control should be performed.

(2) In the above-described embodiment, the mode in which the voltage during the precharge period is kept constant has been described, but the present invention is not limited to this mode. For example, it can be applied to so-called two-stage precharging, in which precharging in the first stage and precharging in the second stage are performed during the precharging period. In this case, the supply timing of the first-stage precharge voltage during negative driving when a certain scanning line 12 is selected is the timing when the voltage of the scanning line 12 selected immediately before reaches the unselected voltage. Control should be performed so that

(3) In the above-described embodiments, the liquid crystal is used as an example of the electro-optical material, but the present invention is also applicable to electro-optical devices using other electro-optical materials. An electro-optical material is a material whose optical properties such as transmittance and brightness are changed by supplying an electrical signal (current signal or voltage signal). For example, the present invention can be applied to display panels using light-emitting elements such as organic EL (ElectroLuminescent), inorganic EL, and light-emitting polymers in the same manner as the above embodiments. The present invention can also be applied to an electrophoretic display panel using microcapsules containing a colored liquid and white particles dispersed in the liquid as an electro-optical material in the same manner as the above embodiments. Furthermore, the present invention can also be applied to a twist ball display panel using, as an electro-optical material, twist balls in which different colors are applied to regions with different polarities, in the same manner as in the above embodiment. The present invention can also be applied to various electro-optical devices such as a toner display panel using black toner as an electro-optical material, or a plasma display panel using a high-pressure gas such as helium or neon as an electro-optical material. can be applied.

(4) In each of the above-described embodiments, the precharge voltage and data voltage output from the data line drive circuit 30 are supplied to the data line 14 via the demultiplexer 57, but the present invention is not limited to this. The data line driving circuit 30 has as many output terminals as the number of data lines 14 (4·J), and each output terminal of the data line driving circuit 30 and each data line 14 of the data line driving circuit 30 are connected one-to-one. may Furthermore, the data line driving circuit 30 may be formed in the electro-optical panel 100. FIG.

<Application example>
INDUSTRIAL APPLICABILITY This invention can be used in various electronic devices. 13 to 15 illustrate specific forms of electronic equipment to which the present invention is applied.

FIG. 13 is a perspective view of a portable personal computer employing an electro-optical device. A personal computer 2000 includes an electro-optical device 1 that displays various images, and a main body 2010 in which a power switch 2001 and a keyboard 2002 are installed.

FIG. 14 is a perspective view of a mobile phone. A mobile phone 3000 includes a plurality of operation buttons 3001 and scroll buttons 3002, and an electro-optical device 1 that displays various images. By operating the scroll button 3002, the screen displayed on the electro-optical device 1 is scrolled. The present invention can also be applied to such mobile phones.

FIG. 15 is a schematic diagram showing the configuration of a projection-type display device (three-panel projector) 4000 employing an electro-optical device. This projection display device 4000 includes three electro-optical devices 1 (1R, 1G, 1B) corresponding to different display colors R, G, B, respectively. The illumination optical system 4001 supplies the red component r of the light emitted from the illumination device (light source) 4002 to the electro-optical device 1R, the green component g to the electro-optical device 1G, and the blue component b to the electro-optical device 1B. supply to Each electro-optical device 1 (1R, 1G, 1B) functions as an optical modulator (light valve) that modulates each monochromatic light supplied from the illumination optical system 4001 according to a display image. A projection optical system 4003 synthesizes the emitted light from each electro-optical device 1 and projects it onto a projection surface 4004 . The present invention can also be applied to such liquid crystal projectors.

In addition to the devices illustrated in FIGS. 1 and 13 to 15, electronic devices to which the present invention is applied include personal digital assistants (PDA). In addition, there are digital still cameras, televisions, video cameras, car navigation devices, in-vehicle displays (instrument panels), electronic notebooks, electronic paper, calculators, word processors, workstations, videophones, and POS terminals. Furthermore, printers, scanners, copiers, video players, devices with touch panels, and the like are included.

REFERENCE SIGNS LIST 1 electro-optical device 10 pixel portion 12 scanning line 14 data line 15 VID signal line 22 scanning line driving circuit 30 data line driving circuit 40 control circuit 57 demultiplexer 58 switch 60 liquid crystal element 62 pixel electrode 64 common electrode 66 liquid crystal 70 analog voltage generation circuit 100 electro-optical panel 200 driving integrated circuit 300 flexible circuit board .

Claims (11)

a plurality of scan lines;
a plurality of data lines;
a pixel provided corresponding to each of the intersections of the plurality of scanning lines and the plurality of data lines and including pixel transistors for capturing the voltage of the data lines;
a data line driving unit for outputting a data voltage having a magnitude corresponding to a gradation to be displayed after outputting the precharge voltage, and for inverting the polarity of the data voltage at a predetermined cycle with a predetermined voltage as a reference;
The timing of outputting the precharge voltage to the data line is controlled, and the voltage of the scanning signal for selecting one of the plurality of scanning lines is changed from the selection voltage for turning on the pixel transistor to the non-turning voltage for turning off the pixel transistor. a control unit that changes the elapsed time from the start of the transition to the selected voltage to the output of the precharge voltage to the data line according to the polarity of the data voltage;
with
When the polarity of the data voltage is positive, the controller controls the precharge voltage as the precharge voltage.
When a first precharge voltage lower than the common voltage is output to the data line and the polarity of the data voltage is negative, the precharge voltage is lower than the common voltage.
A second precharge voltage , which is a voltage, is output to the data line, and the first precharge voltage when the data voltage is positive is higher than the second precharge voltage when the data voltage is negative. and the elapsed time when the data voltage is of negative polarity is longer than the elapsed time when the data voltage is of positive polarity. a plurality of scan lines;
a plurality of data lines;
a pixel provided corresponding to each of the intersections of the plurality of scanning lines and the plurality of data lines and including pixel transistors for capturing the voltage of the data lines;
a scanning line driver that outputs a scanning signal to each of the plurality of scanning lines based on a start pulse and a clock signal;
a data line driving unit for outputting a data voltage having a magnitude corresponding to a gradation to be displayed after outputting the precharge voltage, and for inverting the polarity of the data voltage at a predetermined cycle with a predetermined voltage as a reference;
a selection unit for outputting the precharge voltage and the data voltage output from the data line driving unit to a predetermined data line based on a selection signal specifying start timing for outputting the precharge voltage to the data line; ,
outputting the start pulse and the clock signal to the scanning line driving section; outputting the selection signal to the selection section; and designating the selection signal from timing at which the clock signal transitions from one level to the other level. a control unit that changes the elapsed time until the start timing to start according to the polarity of the data voltage;
with
When the polarity of the data voltage is positive, the controller controls the precharge voltage as the precharge voltage.
When a first precharge voltage lower than the common voltage is output to the data line and the polarity of the data voltage is negative, the precharge voltage is lower than the common voltage.
A second precharge voltage , which is a voltage, is output to the data line, and the first precharge voltage when the data voltage is positive is higher than the second precharge voltage when the data voltage is negative. and the elapsed time when the data voltage is of negative polarity is longer than the elapsed time when the data voltage is of positive polarity. a plurality of scan lines;
a plurality of data lines;
a pixel provided corresponding to each of the intersections of the plurality of scanning lines and the plurality of data lines and including pixel transistors for capturing the voltage of the data lines;
a scanning line driver that outputs a scanning signal to each of the plurality of scanning lines based on a start pulse, a clock signal, and an output control signal;
a data line driving unit for outputting a data voltage having a magnitude corresponding to a gradation to be displayed after outputting the precharge voltage, and for inverting the polarity of the data voltage at a predetermined cycle with a predetermined voltage as a reference;
a selection unit for outputting the precharge voltage and the data voltage output from the data line driving unit to a predetermined data line based on a selection signal specifying start timing for outputting the precharge voltage to the data line; ,
outputting the start pulse, the clock signal, and the output control signal to the scanning line driving section; outputting the selection signal to the selection section; a control unit that changes the elapsed time until the start timing specified by the selection signal according to the polarity of the data voltage;
with
When the polarity of the data voltage is positive, the controller controls the precharge voltage as the precharge voltage.
When a first precharge voltage lower than the common voltage is output to the data line and the polarity of the data voltage is negative, the precharge voltage is lower than the common voltage.
A second precharge voltage , which is a voltage, is output to the data line, and the first precharge voltage when the data voltage is positive is higher than the second precharge voltage when the data voltage is negative. and the elapsed time when the data voltage is of negative polarity is longer than the elapsed time when the data voltage is of positive polarity. the output control signal becomes active during a period in which any one of the scanning signals output to each of the plurality of scanning lines is active;
the timing at which the output control signal transitions from one level to the other level is the timing at which the output control signal transitions from active to inactive;
4. The electro-optical device according to claim 3, wherein: the pixel includes a storage capacitor having one terminal connected to the pixel transistor and the other terminal connected to a capacitor line;
A period during which the precharge voltage is output to the data line when the data voltage has a negative polarity is set shorter than a period during which the precharge voltage is output to the data line when the data voltage has a positive polarity. 4. The electro-optical device according to claim 1, wherein: The timing at which the data line driving section starts outputting the precharge voltage is earlier than the start timing specified by the selection signal.
4. The electro-optical device according to claim 2, wherein: A period during which the data line driving section outputs the precharge voltage substantially coincides with a period during which the selection signal is active for outputting the precharge voltage to the predetermined data line.
4. The electro-optical device according to claim 2, wherein: An electronic apparatus comprising the electro-optical device according to claim 1 . a plurality of scanning lines, a plurality of data lines, and pixels each provided corresponding to each intersection of the plurality of scanning lines and the plurality of data lines and provided with pixel transistors for taking in the voltage of the data lines. A control method for an electro-optical device comprising:
after outputting a precharge voltage to the data line, outputting a data voltage having a magnitude corresponding to a gradation to be displayed to the data line;
inverting the polarity of the data voltage at a predetermined cycle with respect to a predetermined voltage;
The timing of outputting the precharge voltage to the data line is controlled, and the voltage of the scanning signal for selecting one of the plurality of scanning lines is changed from the selection voltage for turning on the pixel transistor to the non-turning voltage for turning off the pixel transistor. changing the elapsed time from the start of the transition to the selected voltage to the output of the precharge voltage to the data line according to the polarity of the data voltage;
When the polarity of the data voltage is positive, the precharge voltage is higher than the common voltage.
A first precharge voltage , which is a low voltage, is output to the data line, and when the polarity of the data voltage is negative , a second precharge voltage, which is a voltage lower than the common voltage, is applied to the data line as the precharge voltage. line, the first precharge voltage when the data voltage is positive is higher than the second precharge voltage when the data voltage is negative, and the data voltage is negative when the data voltage is negative. A method of controlling an electro-optical device, wherein the elapsed time is made longer than the elapsed time when the data voltage has a positive polarity. a plurality of scanning lines, a plurality of data lines, and pixels each provided corresponding to each intersection of the plurality of scanning lines and the plurality of data lines and provided with pixel transistors for taking in the voltage of the data lines. A control method for an electro-optical device comprising:
after outputting a precharge voltage to the data line, outputting a data voltage having a magnitude corresponding to a gradation to be displayed to the data line;
inverting the polarity of the data voltage at a predetermined cycle with respect to a predetermined voltage;
generating a scanning signal for controlling on or off of the pixel transistor based on a start pulse and a clock signal, and outputting the scanning signal to the plurality of scanning lines;
changing the elapsed time from the timing when the clock signal transitions from one level to the other level until the precharge voltage is output to the data line according to the polarity of the data voltage;
When the polarity of the data voltage is positive, the precharge voltage is higher than the common voltage.
A first precharge voltage , which is a low voltage, is output to the data line, and when the polarity of the data voltage is negative , a second precharge voltage, which is a voltage lower than the common voltage, is applied to the data line as the precharge voltage. line, the first precharge voltage when the data voltage is positive is higher than the second precharge voltage when the data voltage is negative, and the data voltage is negative when the data voltage is negative. A method of controlling an electro-optical device, wherein the elapsed time is made longer than the elapsed time when the data voltage has a positive polarity. a plurality of scanning lines, a plurality of data lines, and pixels each provided corresponding to each intersection of the plurality of scanning lines and the plurality of data lines and provided with pixel transistors for taking in the voltage of the data lines. A control method for an electro-optical device comprising:
after outputting a precharge voltage to the data line, outputting a data voltage having a magnitude corresponding to a gradation to be displayed to the data line;
inverting the polarity of the data voltage at a predetermined cycle with respect to a predetermined voltage;
generating a scanning signal for turning on or off the pixel transistor based on a start pulse, a clock signal, and an output control signal, and outputting the scanning signal to the plurality of scanning lines;
changing the elapsed time from the timing when the output control signal transitions from one level to the other level until the precharge voltage is output to the data line according to the polarity of the data voltage;
When the polarity of the data voltage is positive, the precharge voltage is higher than the common voltage.
A first precharge voltage , which is a low voltage, is output to the data line, and when the polarity of the data voltage is negative , a second precharge voltage, which is a voltage lower than the common voltage, is applied to the data line as the precharge voltage. line, the first precharge voltage when the data voltage is positive is higher than the second precharge voltage when the data voltage is negative, and the data voltage is negative when the data voltage is negative. A method of controlling an electro-optical device, wherein the elapsed time is made longer than the elapsed time when the data voltage has a positive polarity.

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