KR20050109653A - Preparation of semiconductor substrate by build up technology - Google Patents

Abstract

The present invention comprises the steps of forming a seed layer on top of the insulating resin, forming a photoresist layer on the top of the seed layer, an exposure step of exposing the mask having an arbitrary pattern on the top of the photoresist layer and then exposed A developing step for removing a portion of the exposed photoresist, a plating step of sequentially stacking a copper layer, a nickel layer, and a gold layer on top of the portion where the photoresist is removed, after the plating step is completed Stripping and soft etching to remove the remaining photoresist and seed layer, and a solder resist printing after the stripping and soft etching is finished provides a method of manufacturing a semiconductor mounting substrate.

According to the present invention, since there is no etching element, it is possible to secure excellent straightness, and the excellent straightness has the effect of ensuring excellent reliability during wire bonding in the semiconductor assembly process.

Description

Manufacturing Method of Semiconductor Mounting Substrate Using Build-up Technology {Preparation of Semiconductor Substrate by Build up Technology}

The present invention relates to a method for manufacturing a semiconductor mounting substrate, and more particularly, to configure a seed layer for electroplating on a non-conductive resin, and to form a copper (Cu) layer on the seed layer using ion deposition. Forming a nickel layer on the top of the copper layer to prevent diffusion of copper, and forming a gold layer on the top of the nickel layer. It relates to a substrate and a method of manufacturing the same.

Semiconductor package (semiconductor package) is a commercial name for a functional component device including a semiconductor chip, which is one of the important devices that is mounted on a circuit board, such as a printed circuit board (PCB) together with other devices to implement an electronic circuit .

The semiconductor package is largely comprised of a memory device, a semiconductor chip, and a semiconductor mounting substrate on which the semiconductor chip is mounted, and these are usually coated with a molding material on the front surface to protect it from external impact.

Meanwhile, the semiconductor mounting substrate, which is one of the elements constituting the semiconductor package, is classified into various types such as a lead frame, a ball grid array (BGA), a pin grid array (PGA), or a tape-BGA.

As described above, as an example of a semiconductor package including a semiconductor mounting substrate, the semiconductor mounting substrate is described through a semiconductor package which is a lead frame. FIG. 1 is an exploded perspective view of the semiconductor package 1 using the lead frame 20. As the semiconductor package 1, the semiconductor package 1 is largely composed of a semiconductor chip 10, which is a memory device, and a lead frame 20, which is a semiconductor mounting substrate on which the semiconductor chip 10 is mounted. 2 shows the lead frame 20.

In this case, the semiconductor chip 10 is a basic cell of a semiconductor substrate that is completed by stacking and patterning various materials on a wafer, and has a plurality of gate regions, which are portions connected to external circuits, on a top thereof, 20 has a plurality of internal leads 12 electrically connected to gate regions of the semiconductor chip 10, and a plurality of external leads 13 electrically connected to external circuits. Lay out so that the 10 can be electrically connected.

In addition, the lead frame 20 in which the semiconductor chip 10 is mounted in this manner is generally used in all parts except the part of the external lead 13 connected to the external circuit for protection from external elements such as temperature change or impurities. 30: Epoxy Mold Compound) and the like is coated.

For reference, the lead frame 20 will be described in more detail. This is a plate-like material made of a material such as copper (Cu) or iron (Fe), and is connected to the gate region of the semiconductor chip as shown in FIG. 2. And a plurality of external leads 13 connected to the internal leads 12 and the external circuits, respectively.

Meanwhile, a method of manufacturing a semiconductor mounting substrate having the above-described configuration will be briefly described with reference to FIG. 3. In the macroscopic view, a solder resist printing process for protecting an etching process, a plating process, and a circuit will be described. Thereby manufacturing a semiconductor mounting substrate.

Here, the etching process is a process of completing a circuit of a mounting substrate, and forming a copper layer on top of a resin, and coating or laminating a photoresist on top of the copper layer to form a photoresist layer. After forming a circuit pattern, the circuit pattern is exposed by using a mask and an ultraviolet light source engraved in reverse phase to shape a circuit pattern on top of the photoresist, and the exposed photoresist is developed to etch the portion of the portion to be etched. The photoresist is removed, and a circuit is fabricated on the mounting substrate by removing the copper layer from which the photoresist is removed with an etching solution.

In this case, as shown in FIG. 4, the copper layer etched by the etching process etches the portion of the photoresist layer 58 removed by the developing process, and the copper layer 56 etched by the etching process. Is etched in a downwardly curved shape by an etching factor so that the shape of the circuit finally manufactured has a pointed peak at the top (FIG. 5).

On the other hand, the plating process is to plate the nickel (Ni) on the top of the copper layer to protect the copper layer, to prevent the diffusion of the copper layer, the gold and the chip (wire bonding) for wire bonding (wire bonding) Au) is plated, and a solder resist printing process is performed to protect the remaining portions except for the bonding.

In the semiconductor mounting substrate manufactured by the above-described method, as shown in FIGS. 4 and 5 by an etching process of etching a copper layer, an etching element is generated to produce a substrate having a shape that is difficult to secure a wire bonding portion. Due to the shape of the peak-like circuit, it is difficult to wire-bond the circuit and it is not possible to pursue the fineness of the circuit due to the multifunction and light weight of the semiconductor.

Accordingly, the present inventors do not etch the copper layer formed on the semiconductor mounting substrate while continuously studying to overcome the above-mentioned problems, and the copper layer, the nickel layer, and the like on a predetermined portion of the photoresist layer on which the circuit pattern is formed. The present invention has been completed by focusing on a build-up technique for plating and laminating a metal.

The present invention was derived to overcome the above problems, to form a seed layer for electroplating on a non-conductive resin, to form a copper layer using ion deposition on the seed layer, the copper layer of the There is a technical problem to provide a method of manufacturing a semiconductor mounting substrate using a build-up technique of forming a nickel layer to prevent diffusion, and forming a gold layer on the stacked nickel layer.

The present invention comprises the steps of forming a seed layer on top of the insulating resin, forming a photoresist layer on the top of the seed layer, an exposure step of exposing the mask having an arbitrary pattern on the top of the photoresist layer and then exposed A developing step for removing a portion of the exposed photoresist, a plating step of sequentially stacking a copper layer, a nickel layer, and a gold layer on top of the portion where the photoresist is removed, after the plating step is completed Stripping and soft etching to remove the remaining photoresist and seed layer, and providing a solder resist printing after the stripping and soft etching is finished, a method for manufacturing a semiconductor mounting substrate do.

Here, the mask used in the exposure step is used to form a pattern of the circuit on the mounting substrate of the circuit, the mask is printed on the circuit pattern to be manufactured, the mask is formed on the mask according to the type of photoresist The circuit pattern is different. For example, when a negative photoresist is formed on the seed layer, the mask is engraved in reverse phase, and when the positive photoresist is formed, an exposure step is performed using a mask engraved with a circuit pattern to be manufactured. Preferably, it is preferable to use negative photoresist.

Meanwhile, in the present invention, the copper layer 56, the nickel layer 60, and the gold layer 66 are formed on the top of the seed layer 54 by the plating.

Hereinafter, a method of manufacturing a semiconductor mounting substrate according to the present invention will be described with reference to the accompanying drawings.

6 is a flowchart illustrating a method of manufacturing a semiconductor mounting substrate according to the present invention.

As shown in FIG. 6, in the method of manufacturing a semiconductor mounting substrate according to the present invention, forming a seed layer 54 on the top of the non-conductive resin 52, and a photoresist layer on the top of the seed layer 54. (58) forming, exposing and then exposing a mask (64) having a predetermined pattern on top of the photoresist layer (8), removing a portion of the exposed photoresist layer (58) Development step for the plating step to build up by sequentially forming the copper layer 56, nickel layer 60 and gold layer 66 on the upper portion of the photoresist layer 58 is removed, the plating step is completed And stripping and soft etching to remove the remaining photoresist layer 58 and seed layer 54, and then printing the solder resist 62 after the stiffening and soft etching are finished. .

The resin 52 according to the present invention means a resin 52 having non-conductivity, and any resin 52 may be used as long as the resin 52 is generally used in the art, and preferably epoxy It is preferable to use a resin, polyimide, phenolic resin, polytetrafluorethylene (PTFE), bismaleide triagen resin (BT resin) or polyimide glass.

The seed layer 54 according to the present invention is a medium for forming the copper layer 56 by using the electroplating principle, and examples of materials that can be used include conventional materials used to form the seed layer 54 in the art. For example, any conductive material such as copper, copper / chromium (Cu / Cr), or copper / molybdenum (Cu / Mo) may be used, and the resin layer 52 may be used as a method of forming the seed layer 54. Can be formed through sputtering or spin coating, etc., but the preferred material constituting the seed layer 54 of the present invention is copper, copper / chromium (Cu / Cr) or copper. In view of being a conductive material such as / molybdenum (Cu / Mo), it is preferable to use a sputtering method, which is a physical vapor deposition method.

The photoresist layer 58 according to the present invention refers to a layer made of photoresist, and the photoresist is classified into a positive or negative photoresist as the photosensitive portion is not dissolved or dissolved in a developer. After exposure to a light source such as ultraviolet light, the portion of the photoresist exposed to the light source is dissolved in a developer and is a positive photoresist, and vice versa.

Therefore, in manufacturing the semiconductor mounting substrate according to the present invention, the photoresist may be any conventional photoresist used in the art, and the pattern of the circuit engraved in the mask according to the type of the photoresist It has a reverse phase or normal for the desired circuit shape. For example, if the photoresist used is negative, the pattern of the circuit engraved in the mask is reversed with respect to the desired circuit pattern. If the photoresist is positive, the pattern of the circuit engraved in the mask is the same as the pattern of the intended circuit. It is done.

The plating step according to the present invention is to sequentially form the copper layer 56, nickel layer 60 and gold layer 66 on the mounting substrate after the development step is completed, the copper layer 56 is ion deposition It is formed on top of the seed layer 54 through.

Here, the copper layer 56 is a medium for transmitting an electrical signal generated from a chip, preferably a silicon chip, corresponds to a circuit of a semiconductor mounting substrate, and preferably has a thickness of 6 to 30 μm. When the thickness of 56) is formed to be 6 μm or less, data loss occurs due to electrical resistance, and the resistance is inversely proportional to the thickness of the copper layer 56, so that a thin copper layer 56 transmits an electrical signal. Will act as a resistance.

The nickel layer 60 is formed by plating on top of the copper layer 56 to protect the copper surface of the copper layer 56 and to prevent diffusion of copper by heat generated in a semiconductor manufacturing process. In general, the nickel layer 60 may be formed to have a thickness of at least 0.1 μm to prevent diffusion of copper. However, the nickel layer 60 may have a thickness of at least 0.2 μm.

The gold layer 66 is formed by plating the upper end of the nickel layer 60 to wire bond the substrate circuit formed of the silicon chip and copper, but the thickness is known to be better, but at least 0.1 in the present invention. It is preferable to have a thickness of at least μm.

As described above, the copper layer 56, the nickel layer 60, and the gold layer 66 are sequentially formed on the top of the seed layer 54 to be formed. Although any method may be used as long as it is a conventional plating method, it is preferable to use the plating method by ion electrodeposition. In addition, the ion electrodeposition is a plating method commonly used in the art, using the principle of ion precipitation by the electrode on the aqueous electrolyte solution using the Faraday principle.

The method of manufacturing a semiconductor mounting substrate according to the present invention is not only related to the influence of the etching elements generated by the etching process by applying the above-described build-up technique, and there is no reduction factor of reliability according to the cross-sectional shape of the circuit, Accordingly, reliability of wire bonding can be realized.

Meanwhile, the stripping is performed to remove the remaining photoresist layer 58 after completing the mounting substrate by the buildup, and the soft etching is performed to remove the seed layer 54 remaining on the mounting substrate. do.

The semiconductor mounting substrate according to the present invention described above may be applied to all semiconductor mounting substrates having a configuration electrically connected through semiconductor wire bonding, that is, lead frames, BGAs, PGAs, Tape-BGAs, and the like.

Hereinafter, the present invention will be described in detail through examples. However, the following examples are only for illustrating the present invention in detail and are not intended to limit the scope of the present invention by these examples.

<Example 1>

A copper layer was laminated on the top of the bismaleide triazene resin [Mitsubishi Chemical, Japan] using Cu liquid for general purpose plating [Kojima Chemical, Japan], and then a DRY Film [Hitachi, Japan] on the top of the seed layer. The photoresist layer was formed.

Then, after aligning the mask having a predetermined pattern on the photoresist layer, the mask was irradiated with ultraviolet rays using a UV lamp.

Next, the photoresist layer irradiated with ultraviolet rays is developed using a developer, and then nickel and gold layers are sequentially formed on the top of the copper layer using Ni solution [Kojima Chemical, Japan] and Au solution [Kojima Chemical, Japan]. Plated with.

Then, the remaining photoresist layer was removed by stripping and soft etching, and then solder resist printing was performed to fabricate a semiconductor mounting substrate.

The surface of the prepared semiconductor mounting substrate was measured by a scanning electron microscope (SEM) using a cross section, and is shown in FIG. 7.

As shown in FIG. 7, since the etching element does not exist in the manufactured semiconductor mounting substrate, the upper and lower portions of the circuit pattern may be manufactured in the same width so as to secure excellent straightness. The straightness not only facilitates the mounting of the semiconductor chip (or DIE), but also shows excellent reliability in terms of post-installation reliability.

As described above, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, the exemplary embodiments described above are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention should be construed that all changes or modifications derived from the meaning and scope of the appended claims and their equivalents, rather than the detailed description, are included in the scope of the present invention.

As described above, the mounting substrate manufactured according to the present invention can secure excellent straightness because there is no etching element, and the excellent straightness can ensure excellent reliability during wire bonding in a semiconductor assembly process. It can be effective.

In addition, the present invention can reduce the lead time (lead time) because the semiconductor mounting substrate can be manufactured in a single process using a plating technology, unlike the manufacturing method of the semiconductor mounting substrate that is separated by the conventional etching and plating process It works.

1 is an exploded perspective view showing an internal structure of a semiconductor package using a lead frame of a typical semiconductor package;

2 is a plan view of a typical lead frame,

3 is a flowchart illustrating a method of manufacturing a conventional semiconductor mounting substrate;

4 is a view illustrating an etching state of a copper layer according to an etching process in a conventional method of manufacturing a semiconductor mounting substrate;

5 is a view showing a circuit structure of a mounting board manufactured according to a conventional method for manufacturing a semiconductor mounting board.

6 is a flowchart illustrating a method of manufacturing a semiconductor mounting substrate according to the present invention;

7 is a diagram illustrating a circuit structure of a mounting board manufactured according to the method of manufacturing a semiconductor mounting board according to the present invention.

<Description of the symbols for the main parts of the drawings>

52: Resin 54: Seed Layer

56 copper layer 58 photoresist layer

60: nickel layer 62: solder resist

64: mask 66: gold layer

Claims (5)

Forming a seed layer on top of the insulating resin, Forming a photoresist layer on top of the seed layer, An exposure step of exposing the mask having an arbitrary pattern on the top of the photoresist layer and then exposing the mask; A developing step for removing a part of the exposed photoresist, Plating step of building up by sequentially stacking a copper layer, a nickel layer and a gold layer on the upper portion of the photoresist removed, Stripping and soft etching to remove remaining photoresist and seed layers after the plating step is completed, And soldering the resist after the stripping and the soft etching are completed. The method of claim 1, The seed layer is a manufacturing method of a semiconductor mounting substrate, characterized in that the copper, copper / chromium or copper / molybdenum. The method according to claim 1 or 2, The thickness of the copper layer in the plating step is a manufacturing method of a semiconductor mounting substrate, characterized in that 6 to 30㎛. The method according to claim 1 or 2, The thickness of the nickel layer in the plating step is a manufacturing method of a semiconductor mounting substrate, characterized in that more than 1.2㎛. The method according to claim 1 or 2, The thickness of the gold layer of the plating step is a manufacturing method of a semiconductor mounting substrate, characterized in that more than 0.1㎛.