KR20050010260A - Method of manufacturing NAND flash memory device - Google Patents

Abstract

The present invention relates to a method for manufacturing a NAND flash memory device, wherein a portion of a common source line to be formed is connected to an active region during a mask separation process, and a common source line during a mask process for a floating gate and a mask process for a dielectric film. After exposing the semiconductor substrate of the portion to be formed, impurity ions for the source line are implanted so that the cell source region and the ion implantation region are alternately connected, and the control gate conductive layer is the cell source region and the ion during the mask process for the control gate. Since the common source line is formed to remain on the injection region, the common source line can be formed by a device separation mask process / control gate mask process rather than a contact mask process, which simplifies the process. Can lower the resistance and process steps One can.

Description

Method of manufacturing NAND flash memory device {Method of manufacturing NAND flash memory device}

The present invention relates to a method of manufacturing a NAND flash memory device, and in particular, to improve the cell source contact forming process, simplify the process, reduce the resistance of the common source line, and reduce the process step. A method for manufacturing a device.

Information stored in a cell of a nonvolatile memory device such as a flash memory device is not destroyed even when the power is cut off. Therefore, flash memory devices are widely applied to memory cards and the like. Flash memory devices are classified into two categories. One is a NAND-type flash memory device, and the other is a NOR-type flash memory device.

NAND flash memory devices can be divided into cell regions and peripheral circuit regions. The cell region is composed of a plurality of strings, and a source select transistor, a plurality of memory cells, and a drain select transistor are connected in series to each string. The source region of the source select transistor is connected with the common source line, and the drain region of the drain select transistor is connected with the bit line. The peripheral circuit area is composed of peripheral transistors such as PMOS transistors and NMOS transistors.

Meanwhile, the cell region of the NOR flash memory device includes a plurality of memory cells, bit lines, and common source lines, and only one memory cell is interposed between the bit line and the common source line.

Accordingly, NAND flash memory devices exhibit higher integration levels than NOR flash memory devices, but require high cell currents. Here, the cell current refers to a current flowing through the bit line and the common source line while reading information stored in the memory cell. Therefore, efforts to increase the cell current of NAND flash memory devices are more demanded than NOR flash memory devices. This is because the larger the cell current, the faster the access time of the flash memory device. As a result, in order to improve the operating speed of the NAND flash memory device, it is required to reduce the electrical resistance of the bit line and / or the common source line.

1A is a cross-sectional view illustrating a method of manufacturing a NAND flash memory device according to the prior art, and FIG. 1B is a cross-sectional view taken along a region where a common source line is to be formed to explain a method of manufacturing a NAND flash memory device according to the prior art. It is a cross section.

1A and 1B, a plurality of device isolation layers 12 parallel to each other are formed in a predetermined region of the semiconductor substrate 11 to define an active region. The device isolation layers 12 are formed by a local oxidation of silicon (LOCOS) process or a trench device isolation process, and recently, many trench device isolation processes are applied for high integration of devices. NAND flash memory devices can be roughly divided into cell regions and peripheral circuit regions. The cell regions are composed of a plurality of strings, each of which has a source select transistor (SST), a plurality of memory cells (MC1 to MCn), and a drain selector. Transistors DST are formed in series. In the peripheral circuit region, peripheral transistors PT such as PMOS transistors and NMOS transistors are formed. The metal contact process is then carried out to electrically connect them, as described below.

After the etch stop layer 14 is formed on the entire structure including the transistors SST, MC, and DST, the first interlayer insulating layer 15 is formed on the entire structure of the resultant structure on which the etch stop layer 14 is formed. After planarizing the surface of the first interlayer insulating layer 15 by a chemical mechanical polishing (CMP) process, the first interlayer insulating layer 15 and the etch stop layer 14 are etched by an etching process using a mask for a common source line contact. After forming the common source line contact hole in which the cell source regions 13S and the device isolation layers 12 are exposed, and forming the doped polysilicon layer to fill the common source line contact hole, the first interlayer insulating layer 15 ) The entire surface of the doped polysilicon layer is etched to form a common source line CSL. This process is called a cell source poly plug process.

The second interlayer insulating film 18 is formed on the first interlayer insulating film 15 including the common source line CSL, and the second interlayer insulating film 18 and the first interlayer insulating film 18 are formed by an etching process using a drain contact mask. 15) and the etch stop layer 14 are etched to form cell drain contact holes exposed to each of the cell drain regions 13D, and a doped polysilicon layer is formed to fill the cell drain contact holes, followed by a second interlayer. The doped polysilicon layer is etched entirely so that the insulating layer 18 is exposed to form cell drain contact plugs DCP. This process is called a cell drain poly plug process.

After the trench nitride layer 19 and the trench oxide layer 20 are sequentially formed on the second interlayer insulating layer 18 including the cell drain contact plugs DCC, damascene patterns are formed by a damascene process. . After the metal is deposited to fill the damascene patterns, the front surface etching process is performed to form a metal wiring 22S connected to the common source line CSL, a bit line 22D connected to the drain contact plug DCP, and a peripheral transistor. The metal wiring 22G connected to the gate of PT and the metal wiring 22P connected to the source / drain junction 13P of the peripheral transistor PT are formed.

As described above, according to the related art, the thickness of the common source line CSL is determined by the first interlayer insulating layer 15. In other words, the electrical resistance of the common source line CSL decreases as the thickness of the first interlayer insulating layer 15 becomes thicker. Therefore, when considering the electrical resistance of the common source line (CSL), there is a limit to reducing the thickness of the first interlayer insulating film 15, which acts as a factor of increasing the aspect ratio in the subsequent metal contact process, especially the cell drain contact process Therefore, the cell drain contact plug DCD must be formed first, and when the aspect ratio is high, the metal wiring 22G connected to the gate of the peripheral transistor PT and the source / drain junction 13P of the peripheral transistor PT are formed. The contact process for forming the metal wiring 22P connected to is performed by a separate mask operation, which is accompanied by process inconvenience. That is, the conventional NAND flash metal contact process uses five reticles due to the difficulty of forming source and drain contacts in a cell. As a result, in order to implement a high performance NAND flash memory device, it is required to minimize the resistance of the common source line while preventing an increase in the aspect ratio of the contact hole for connecting the bit line 22D to the cell drain region 13D.

Accordingly, the present invention can reduce the aspect ratio of the drain contact hole while reducing the resistance of the common source line, simplify the process, reduce the resistance of the common source line, and reduce the process steps. It is an object of the present invention to provide a method for manufacturing a memory device.

1A is a cross-sectional view illustrating a method of manufacturing a NAND flash memory device according to the prior art.

1B is a cross-sectional view taken along a region where a common source line is to be formed to explain a method of manufacturing a NAND flash memory device according to the prior art.

2A is a cross-sectional view illustrating a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.

2B is a cross-sectional view taken along a region where a common source line is to be formed to explain a method of manufacturing a NAND flash memory device according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11, 31: semiconductor substrate 12: device isolation film

13S, 33S: cell source region 13C, 33C: cell impurity region

13D, 33D: cell drain region 13P, 33P: source / drain junction

14, 34: etch stop film 15, 35: first interlayer insulating film

36: common source line contact hole 37: ion implantation region

18: second interlayer insulating film 19, 39: trench etch stop film

20, 40: trench insulating film

41S: damascene pattern for common source line contacts

41D: damascene pattern for cell drain contacts

41P: damascene pattern for source / drain contacts of peripheral transistors

41G: damascene pattern for gate contact of peripheral transistors

22S, 42S: Metal Wiring for Cell Sources

22D, 42D: Bitline

22P, 42P: Metal Wiring for Gate of Peripheral Transistor

22G, 42G: Metal wiring for source / drain junctions of peripheral transistors

50: tunnel oxide film 51: pad polysilicon layer

52: polysilicon layer for floating gate 53: dielectric film

54: conductive layer for control gate 55: hard mask layer

SST: source select transistor MC1, ..., MCn: memory cell

DST: Drain Select Transistor PT: Peripheral Transistor

CSL: Common source line DCP: Drain contact plug

In the method of manufacturing a NAND flash memory device according to an embodiment of the present invention for achieving the above object, a device isolation process forms a device isolation layer in a field region of a semiconductor substrate to define an active region, but a portion in which a common source line is to be formed. Allowing all of them to be connected to the active area; After forming the floating silicon polysilicon layer on the entire structure in which the device isolation layers are formed, the polysilicon layer is patterned by an etching process using a floating gate mask, exposing an active region of a portion where the common source line is to be formed. Making a step; Forming ion implantation regions in the exposed active region between cell source regions and the cell source region by a source line ion implantation process; Forming a dielectric film on the entire structure including the patterned polysilicon layer, and then removing the dielectric film on a portion where the cell source region and the ion implantation region are formed by an etching process using a dielectric film mask; and forming the dielectric film After the conductive layer for the control gate is formed on the entire structure, gates are formed in the cell region and the peripheral circuit region by an etching process using a control gate mask, but the control gate is formed on the cell source region and the ion implantation region. Leaving the conductive layer in the form of a line pattern, thereby forming a common source line.

In the above method, after the forming of the common source line, forming an interlayer insulating layer on the entire structure including the common source line; Sequentially forming a trench etch stop layer and a trench insulating layer on the interlayer insulating layer; Simultaneously forming a plurality of damascene patterns in a damascene process; And filling metals of the damascene patterns with metal to form metal wires electrically connected to a lower layer, respectively.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, like reference numerals refer to like elements.

2A is a cross-sectional view illustrating a method of manufacturing a NAND flash memory device according to an embodiment of the present invention, and FIG. 2B illustrates a common source line for explaining a method of manufacturing a NAND flash memory device according to an embodiment of the present invention. Sectional view cut along the area to be cut. In the manufacturing process of the NAND flash memory device, the cell region and the peripheral circuit region are all related to the process steps, but the following description will focus on the cell region.

First, after the well process and the Vt adjustment process, the tunnel oxide film 50 and the pad polysilicon are formed on the semiconductor substrate 31 for the self-aligned device isolation (SA-STI) process. A semiconductor substrate is formed by forming a layer 51 and a nitride film (not shown), and using a device isolation trench etching process, a well oxidation process, a device isolation layer deposition process, a chemical mechanical polishing process, and a nitride film removal process. A plurality of device isolation layers (not shown) parallel to each other are formed in the field region 31 to define the active region. In this case, all portions in which the common source line of the cell region is to be formed are connected to the active region. This can be well understood by comparing FIG. 2B with the existing drawing 1B. That is, as shown in FIG. 1B, the device isolation layers 12 are formed in the portion where the common source line of the cell region is to be formed, but in the present invention, all of them are connected to the active region.

After forming the floating gate polysilicon layer 52 on the entire structure where the device isolation layers are formed, the floating gate polysilicon layer 52 covers the active region while partially overlapping the device isolation layer by an etching process using a floating gate mask. Pattern). In this case, the floating gate polysilicon layer 52 and the tunnel oxide layer 50 on the active region of the portion where the common source line of the cell region is to be formed are removed. The first source line ion implantation process is performed to form ion implantation regions 37 connecting the cell source regions 33S and the cell source region 33S to the semiconductor substrate 31 on which the common source line is to be formed. Since other regions are regions in which device isolation layers are formed, there is no problem with the first source line ion implantation process. In the first source line ion implantation process, 1E12 to 1E14 atom / cm with an injection energy of 15keV to 25keV ² Dosing is carried out, and as the impurity used at this time is used (As) or phosphorus (P).

After the dielectric film 52 is formed over the entire structure including the patterned floating silicon polysilicon layer 52, an active region (cell source) in which a common source line of the cell region is to be formed by an etching process using a dielectric film mask. The dielectric film 53 on the region and the portion where the ion implantation region is formed is removed. In the dielectric film mask process, the dielectric film 53 of the peripheral circuit region is also removed, so that the floating silicon polysilicon layer 52 to be used as a gate of the peripheral circuit region and the control gate conductive layer 54 formed by a subsequent process are electrically connected. You can make a direct connection. The second source line ion implantation process is performed to once again implant the cell source regions 33S and the ion implantation regions 37. In the second source line ion implantation process, 1E12 to 1E14 atom / cm with an injection energy of 15keV to 25keV ² Dosing is carried out, and as the impurity used at this time is used (As) or phosphorus (P). In addition, you may perform only one of the 1st and 2nd ion implantation process.

After forming the control gate conductive layer 54 and the hard mask layer 55 on the entire structure where the dielectric film 53 is formed, the hard mask layer 55 and the control gate are formed by an etching process using a mask for the control gate. The conductive layer 54, the dielectric film 53, the floating gate polysilicon layer 52, and the pad polysilicon layer 51 are patterned to form gates in each of the cell region and the peripheral circuit region. In this case, the control gate conductive layer 54 is formed on the cell source regions 33S and the ion implantation regions 37 to form a line pattern, which is formed by a conventional cell source poly plug process. The same common source line CSL is formed. In general, the control layer conductive layer 54 has a structure in which polysilicon and metal-silicide are laminated in order to lower wiring resistance. Thereafter, the cell impurity region 33C, the cell drain region 33D, and the source / drain junction 33P are formed through a source / drain ion implantation process.

As a result of the above process, the cell region is composed of a plurality of strings, and the source select transistor SST, the plurality of memory cells MC1 to MCn, and the drain select transistor DST are connected in series to each string. Is formed. In the peripheral circuit region, peripheral transistors (Peri-Transistors (PT)) such as PMOS transistors and NMOS transistors are formed. The source select transistor SST has a cell source region 33S, the plurality of memory cells MC1 to MCn have a cell impurity region 33C, and the drain select transistor DST has a cell drain region 33D. The peripheral transistor PT has a source / drain junction 33P.

After the etch stop film 34 is formed of nitride on the entire structure of the resultant product, an interlayer insulating layer 35 having a flattened surface is formed on the resultant overall structure on which the etch stop film 34 is formed. After the trench etch stop layer 39 is formed of nitride on the interlayer insulating layer 35, and the trench insulating layer 40 is formed on the trench etch stop layer 39, the damascene patterns are formed by a damascene process. (41S, 41D, 41P, and 41G) are formed simultaneously. Damascene pattern 41S for common source line contact, damascene pattern 41D for cell drain contact, source / drain contact damascene pattern 41P for peripheral transistor, and damascene pattern 41G for gate contact of peripheral transistor Each can be simultaneously formed in one damascene process. The conventional interlayer insulating film has a very high height with a two-layer structure (indicated by reference numerals 15 and 18 of FIG. 1A), whereas the interlayer insulating film of the present invention has a single layer structure. This is possible because the aspect ratio of the contact hole portion of each of the drinking patterns 41S, 41D, 41P, and 41G is lowered.

After depositing a metal on the entire structure so that the damascene patterns 41S, 41D, 41P, and 41G are buried, the entire surface etching process is performed until the upper surface of the trench insulating film 40 is exposed, thereby conducting the conductive layer for the control gate. The metal wire 42S connected to the common source line CSL made of 54, the bit line 42D connected to the cell drain region 33D, and the metal wire 42G connected to the gate of the peripheral transistor PT. And metal wiring 42P connected to the source / drain junction 33P of the peripheral transistor PT, respectively.

In the method of manufacturing a NAND flash memory device of the present invention, the portions to be formed in the common source line are all connected to the active region during the mask isolation process, and the common source lines are used during the mask process for the floating gate and the mask process for the dielectric film. After exposing the semiconductor substrate to be formed, impurity ions for the source line are implanted so that the cell source region and the ion implantation region are alternately connected, and the control gate conductive layer is the cell source region and the ion implantation during the mask process for the control gate. Remain on the area to form a common source line.

The invention is not limited to the specific field herein described with reference to the suitable embodiments, but rather the scope of the invention should be understood by the claims herein.

As described above, the present invention forms a common source line as a conductive layer for a control gate having a low resistance, thereby minimizing the resistance of the common source line, and does not require a cell source contact plug process and a cell drain contact plug process separately. Since the contact mask process step can be reduced, and the interlayer insulating film is formed as a single layer, the contact process margin can be simplified and the contact process margin can be secured due to the topology reduction, thereby improving device reliability and product productivity. have.

Claims (6)

Forming an isolation region in the field region of the semiconductor substrate by an isolation process to define an active region, wherein all portions on which the common source line is to be formed are connected to the active region; After forming the floating silicon polysilicon layer on the entire structure in which the device isolation layers are formed, the polysilicon layer is patterned by an etching process using a floating gate mask, exposing an active region of a portion where the common source line is to be formed. Making a step; Forming ion implantation regions in the exposed active region between cell source regions and the cell source region by a source line ion implantation process; Forming a dielectric film on the entire structure including the patterned polysilicon layer, and then removing the dielectric film on a portion where the cell source region and the ion implantation region are formed by an etching process using a dielectric film mask; And After the conductive layer for the control gate is formed over the entire structure of the dielectric layer, gates are formed in the cell region and the peripheral circuit region by an etching process using a mask for the control gate, on the cell source region and the ion implantation region. Leaving the control gate conductive layer in the form of a line pattern, thereby forming a common source line. The method of claim 1, The source line ion implantation process is 1E11 to 1E14 atom / cm with an injection energy of 15keV to 25keV ² A method for manufacturing a NAND flash memory device using a dose of amine and using ascetic or phosphorus as impurity ions. The method of claim 1, And performing the source line ion implantation step once more after the dielectric film removal step. The method of claim 1, A method of manufacturing a flash memory device to remove the dielectric film in the peripheral circuit area during the mask process for the dielectric film. The method of claim 1, The control gate conductive layer is a method of manufacturing a flash memory device having a structure in which polysilicon and metal-silicide are laminated. The method of claim 1, After forming the common source line, Forming an interlayer insulating film on the entire structure including the common source line; Sequentially forming a trench etch stop layer and a trench insulating layer on the interlayer insulating layer; Simultaneously forming a plurality of damascene patterns in a damascene process; And And filling the damascene patterns with metal to form metal wires electrically connected to a lower layer, respectively.