KR20030073006A - A thin film transistor substrate of using insulating layers having law dielectric constant and a method of manufacturing the same - Google Patents

Abstract

A gate wiring is formed on an insulating substrate, a data wiring insulated from and intersecting with the gate wiring is formed, and a thin film transistor connected to the gate wiring and the data wiring is formed. On the thin film transistor, a protective film made of a polyorganosilsesquioxane or a film containing a polyorganosilsesquioxane with pores (low dielectric insulating film) is formed, and a pixel electrode connected to the thin film transistor is formed on the protective film. Formed. In this way, the parasitic capacitance problem can be solved, a high opening ratio structure can be realized, and the process time can be shortened.

Description

A thin film transistor substrate using a low dielectric constant insulating film and a method of manufacturing the same {A THIN FILM TRANSISTOR SUBSTRATE OF USING INSULATING LAYERS HAVING LAW DIELECTRIC CONSTANT AND A METHOD OF MANUFACTURING THE SAME}

The present invention relates to a thin film transistor substrate and a method of manufacturing the same.

The thin film transistor substrate is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic EL (electro luminescence) display device, or the like. The thin film transistor substrate includes a scan signal line or a gate line for transmitting a scan signal and an image signal line or data line for transmitting an image signal, a thin film transistor connected to the gate line and a data line, and a pixel connected to the thin film transistor. And an electrode, a gate insulating film covering and insulating the gate wiring, and a thin film transistor and a protective film covering and insulating the data wiring. The thin film transistor includes a semiconductor layer forming a gate electrode and a channel, which are part of a gate wiring, a source electrode and a drain electrode, which are part of a data wiring, a gate insulating film, a protective film, and the like. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

As a representative device using such a thin film transistor substrate, there is a liquid crystal display device. As the liquid crystal display device is gradually enlarged in size and high in size, a signal distortion problem caused by an increase in various parasitic capacitances has emerged as an urgent problem. In addition, the need for increasing the aperture ratio is increasing due to the reduction in power consumption in the notebook computer and the need for improving the luminance to increase the viewing distance in the liquid crystal display for TVs. However, in order to increase the aperture ratio, it is necessary to form the pixel electrode so as to overlap the data line, but in this case, the parasitic capacitance between the pixel electrode and the data line increases. In order to solve the problem caused by the parasitic capacitance increase, a sufficient vertical separation between the pixel electrode and the data line should be secured. In order to secure the vertical separation, a protective film is mainly formed of an organic insulating layer. However, the process using the organic insulating film has the following disadvantages. First, the material cost is expensive. In particular, the amount of loss during spin coating increases the cost of materials. Next, the organic insulating film lacks heat resistance, and subsequent processes are restricted. In addition, the frequency of occurrence of impurity particles due to the aggregation of materials and the like is high. Adhesion to the upper and lower layers is weak. The etching error is very large when forming the pixel electrode formed on the passivation layer.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor substrate having a high opening ratio and no parasitic capacitance problem and a method of manufacturing the same.

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1;

3A, 4A, 5A, and 6A are layout views of a thin film transistor substrate, illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, according to a process sequence thereof;

3B is a cross sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

4B is a cross sectional view taken along the line IVb-IVb ′ in FIG. 4A showing the next step of FIG. 3B;

FIG. 5B is a cross sectional view taken along the line Vb-Vb ′ in FIG. 5A and showing the next step in FIG. 4B;

FIG. 6B is a cross sectional view taken along the line VIb-VIb ′ in FIG. 6A and showing the next step in FIG. 6;

7 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

8 and 9 are cross-sectional views taken along lines VII-VII 'and IX-IX' of FIG. 7, respectively.

10A is a layout view of a thin film transistor substrate in a first step of manufacturing according to the second embodiment of the present invention;

10B and 10C are cross-sectional views taken along lines Xb-Xb 'and Xc-Xc', respectively, in FIG. 10A.

11A and 11B are cross-sectional views taken along the lines Xb-Xb 'and Xc-Xc' in FIG. 10A, respectively, and are cross-sectional views in the next steps of FIGS. 10B and 10C,

12A is a layout view of a thin film transistor substrate in FIGS. 11A and 11B next steps;

12B and 12C are cross-sectional views taken along lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively.

13A, 14A, 15A and 13B, 14B, and 15B are cross-sectional views of the XIIb-XIIb 'line and the XIIc-XIIc' line in FIG. 12A, respectively, illustrating the following steps in the order of a process.

16A and 16B are cross-sectional views of the thin film transistor substrate in the next steps of FIGS. 15A and 15B;

17A is a layout view of a thin film transistor substrate at a next step of FIGS. 16A and 16B,

17B and 17C are cross sectional views taken along lines XVIIb-XVIIb 'and XVIIc-XVIIc', respectively, in FIG. 17A;

18 is a layout view of a thin film transistor substrate having a color filter according to a third embodiment of the present invention;

19 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 18 along a cutting line XIX-XIX ′,

20A is a layout view of a substrate in a first manufacturing step of the thin film transistor substrate according to the third embodiment of the present invention,

20B is a cross-sectional view taken along the cutting line XXb-XXb shown in FIG. 20A.

21A is a layout view of the substrate in the next step of FIG. 20A,

FIG. 21B is a cross-sectional view taken along cut line XXIb-XXIb ′ shown in FIG. 21A;

FIG. 22A is a layout view of a substrate in the next step of FIG. 22A, and FIG.

FIG. 22B is a cross-sectional view taken along cut line XXIIb-XXIIb 'shown in FIG. 22A.

FIG. 23 is a cross sectional view of the substrate in the next step of FIG. 22B;

24A is a layout view of the substrate in the next step of FIG. 23,

24B is a cross-sectional view taken along the cutting line XXIVb-XXIVb 'shown in FIG. 24A.

25 to 26 show a cross section of the manufacturing process performed between FIGS. 23 and 24b,

27A is a layout view of the substrate in the next step of FIG. 24A,

FIG. 27B is a cross-sectional view taken along cut line XXVIIb-XXVIIb ′ shown in FIG. 27A, and FIG.

28 is a layout view of a thin film transistor substrate for a liquid crystal display according to a fourth exemplary embodiment of the present invention.

FIG. 29 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 28 taken along the line XXIX-XXIX ',

30A is a layout view of a thin film transistor substrate at a first stage of manufacture in accordance with a fourth embodiment of the present invention,

FIG. 30B is a cross-sectional view taken along the line XXXb-XXXb 'in FIG. 30A;

31A is a layout view of a thin film transistor substrate in a second step of manufacturing according to the fourth embodiment of the present invention;

FIG. 31B is a cross-sectional view taken along the line XXXIb-XXXIb 'of FIG. 31A;

32A is a layout view of a thin film transistor substrate in a third step of manufacturing according to the fourth embodiment of the present invention;

FIG. 32B is a cross-sectional view taken along the line XXIIb-XXXIIb 'of FIG. 32A;

33A is a layout view of a thin film transistor substrate in a fourth step of manufacturing according to the fourth embodiment of the present invention;

FIG. 33B is a cross-sectional view taken along the line XXXIIIb-XXXIIIb 'of FIG. 33A;

34A is a layout view of a thin film transistor substrate at a fifth step of manufacturing according to the fourth embodiment of the present invention;

34B is a cross-sectional view taken along the line XXXIVb-XXXIVb 'in FIG. 34A;

35 is a layout view of a thin film transistor substrate for a liquid crystal display according to a fifth embodiment of the present invention;

36 and 37 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 35 taken along lines XXXVI-XXXVI 'and XXXVII-XXXVII'.

In order to solve this problem, in the present invention, a low dielectric constant insulating film including polyorganosilsesquioxane or polyorganosilsesquioxane having pores formed by spin on glass (SOG) or chemical vapor deposition is used as a protective film of a thin film transistor substrate. I use it.

Specifically, an insulating substrate, a first signal line formed on the insulating substrate, a first insulating film formed on the first signal line, a second signal line formed on the first insulating film and intersecting the first signal line, a first signal line, and A low dielectric constant insulating film including a thin film transistor, a polyorganosilsesquioxane, or a polyorgano silsesquioxane having pores formed therein, and is formed on a thin film transistor and exposes a predetermined electrode of the thin film transistor. A thin film transistor substrate including a second insulating film having a contact hole and a pixel electrode formed on the second insulating film and connected to a predetermined electrode of the thin film transistor is provided through the first contact hole.

In this case, the first insulating film may be formed of a lower film, which is a low dielectric constant insulating film, and an upper film, which is a silicon nitride film, and the second insulating film may have an uneven pattern on its surface.

The low dielectric constant insulating film may be formed of a polyorganosilsesquioxane organic insulating film using a spin on glass (SOG) process. Preferably, the polyorganosilsesquioxane system uses a compound of the following formula (1) or (2).

[Formula 1] [Formula 2]

In Formula 1 and Formula 2,

R is hydrogen, a hydroxy group, an alkyl having 1 to 5 carbon atoms, or an aryl group; X is ethylene or propylene and n is an integer from to 1,000.

Polyorganosilsesquioxane of Formula 1 or Formula 2 has a basic structure of SiO _x in a molecule, and forms a regular ladder structure having various substituents on Si. The preparation of the polyorganosilsesquioxane may be prepared by, for example, hydrolysis condensation of the silane compound, but is not limited thereto. The polyorganosilsesquioxane-based compound determines the density, porosity, and network structure of the polymer according to the difference in precursor structure, and accordingly, values such as dielectric constant (K), hardness, stress, and efficiency of thermal expension (CTE) are determined. This is decided. Such polyorganosilsesquioxane-based compounds are known and commercialized in various product names, such as FOX, HOSP (Allied signal), PPSQ (intersilicon). The composition of the polyorganosilsesquioxane to be used in the present invention is preferably in the range of _0.3-2.0 SiO _1.2-1.8 R.

In addition, the present invention can form various types of pores in the polyorganosilsesquioxane polymer, it is possible to reduce the thickness of the protective film and further increase the dielectric constant through this process. That is, the polyorganosilsesquioxane compound has a low dielectric constant (K) of 2 to 3 in itself, but when the porosity is increased by controlling the size and content of the pores, the dielectric constant value is 2.0 or less. You can even lower. The present invention can use a method of intramolecularly bonding a cage compound of silica (SiO ₂ ) series to polyorganosilsesquioxane to form nano-sized pores. In addition, the polyorganosilsesquioxane may be mixed with another kind of pore generating material (porogen) to form pores by decomposition. The size of the pores thus formed is preferably 5 to 500 mm 3. The form of the protective film using polyorganosilsesquioxane is preferably used as a single film of polyorganosilsesquioxane or as a structure of silicon nitride (SiN _x ) / polyorganosilsesquioxane double membrane.

Thus, when the polyorganosilsesquioxane-based insulating film is used as a protective film, the dielectric constant is lower than that of conventional silicon nitride alone or a low dielectric material, and has a transmittance of 98% or more over the full-wavelength field in the visible light region. There is almost no reduction. In addition, it is possible to form a protective film up to about 2 um, low dielectric constant value is not a problem even if applied to the actual 2 um or less, it is more stable to OLB regeneration because the hardness and mechanical strength is superior to the conventional low dielectric material. In addition, even after 6 months at room temperature, there is almost no change in viscosity, so it is excellent in storage stability, and excellent in solubility and stability in propylene glycol monomethyl ether acetate (PGMEA), ethoxyethyl propionate (EEP), and after spin coating. Residue on the wall in the chamber can be easily removed using a solvent or thinner for PR, which is advantageous for facility management. The polyorganosilsesquioxane may increase the degree of curing at a high temperature of about 300 to 400 ℃ and can be cured even below 300 ℃ / 1 hr. Since the precursor of the polyorganosilsesquioxane uses a cheap and easily synthesized raw material, it is excellent in price competitiveness.

Then, a person having ordinary knowledge in the technical field to which the present invention belongs can easily implement the thin film transistor substrate to which the structure of the low resistance wiring according to the embodiment of the present invention is applied and the manufacturing method thereof with reference to the accompanying drawings. It will be explained in detail.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II of the thin film transistor substrate shown in FIG.

The first gate wiring layers 221, 241, and 261 made of chromium (Cr) or molybdenum (Mo) alloy and the like, and the second gate wiring layer 222 made of aluminum (Al) or silver (Ag) alloy, or the like on the insulating substrate 10. Gate wirings formed of a double layer of 242 and 262 are formed. The gate wire is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24 in an island shape, and silicide or n-type impurities are doped with high concentration on the semiconductor layer 40. Resistive contact layers 54 and 56 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.

On the ohmic contact layers 54 and 56 and the gate insulating layer 30, the first data wiring layers 621, 651, 661, and 681 made of Cr or Mo alloy, etc., and the second data wiring layers 622 made of Al or Ag alloy, etc. Data wirings 62, 65, 66, and 68 formed of double layers of 652, 662, and 682 are formed. The data lines 62, 65, 66, and 68 are formed in the vertical direction and intersect with the gate line 22 to define the pixel, the branch of the data line 62, the data line 62, and the resistive contact layer 54. It is connected to one end of the source electrode 65 and the data line 62 extending to the upper portion, and separated from the data pad 68 and the source electrode 65 to which an image signal from the outside is applied, and the gate electrode 26. And a drain electrode 66 formed over the ohmic contact layer 56 opposite the source electrode 65.

The passivation layer 70 is formed on the data wires 62, 65, 66, and 68 and the semiconductor layer 40 not covered by the data lines 62. Here, the protective film 70 is made of a low dielectric constant insulating film containing polyorganosilsesquioxane, has a low dielectric constant of 2.0 to 3.0, and is made of a polyorganosilsesquioxane film having pores. The dielectric constant is 2.0 or less, resulting in a lower dielectric constant. Therefore, even a thin thickness does not cause a parasitic capacity problem. Excellent adhesion to another membrane and step coverage. Moreover, since it is an inorganic insulating film, heat resistance is excellent compared with an organic insulating film. In addition, a film (low dielectric constant insulating film) containing polyorganosilsesquioxane or pores formed polyorganosilsesquioxane deposited by PECVD method is 4 to 10 times faster than the silicon nitride film by the deposition rate or etching rate. It is also very advantageous in terms of process time.

In the passivation layer 70, contact holes 76 and 78 are formed to expose the drain electrode 66 and the data pad 68, respectively. The contact hole 74 exposing the gate pad 24 together with the gate insulating layer 30 is formed. Is formed. In this case, the contact holes 74 and 78 exposing the pads 24 and 68 may be formed in various shapes having an angle or a circular shape, and the area thereof does not exceed 2 mm × 60 μm, preferably 0.5 mm × 15 μm or more. Do.

On the passivation layer 70, a pixel electrode 82 electrically connected to the drain electrode 66 and positioned in the pixel is formed through the contact hole 76. In addition, the auxiliary gate pad 86 and the auxiliary data pad 88, which are connected to the gate pad 24 and the data pad 68, respectively, are formed on the passivation layer 70 through the contact holes 74 and 78. Here, the pixel electrode 82, the auxiliary gates, and the data pads 86 and 88 are made of indium tin oxide (ITO) or indium zinc oxide (IZO).

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring.

The pixel electrode 82 is also formed to overlap the data line 62 to maximize the aperture ratio. As such, even when the pixel electrode 82 is overlapped with the data line 62 in order to maximize the aperture ratio, the dielectric constant of the passivation layer 70 is low, so that the parasitic capacitance formed therebetween is small.

Next, a method of manufacturing the thin film transistor substrate for a liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2, and FIGS. 3A to 6B.

First, as illustrated in FIGS. 3A and 3B, the first gate wiring layers 221, 241, and 261 are laminated by depositing Cr or Mo alloy having excellent physicochemical properties on the substrate 10, and Al or the low resistance. Second gate wiring layers 222, 242, and 262 are laminated by depositing Ag or an alloy including the same, and then patterned to form a horizontal direction including the gate line 22, the gate electrode 26, and the gate pad 24. To form a gate wiring extending.

At this time, when the first gate wiring layers 221, 241, and 261 are formed of Mo alloy and the second gate wiring layers 222, 242, and 262 are formed of Ag alloy, both of these layers are phosphoric acid which is an Ag alloy etchant. It is etched by a mixture of nitric acid, acetic acid and deionized water. Therefore, the gate wirings 22, 24, and 26 of the double layer may be formed by one etching process. In addition, since the etching ratio of the Ag alloy and the Mo alloy by the phosphoric acid, nitric acid, acetic acid, and ultrapure water mixture is larger than that of the Ag alloy, the gate wiring may be formed in a tapered structure.

Next, as shown in FIGS. 4A and 4B, a three-layer film of a gate insulating film 30 made of silicon nitride, a semiconductor layer 40 made of amorphous silicon, and a doped amorphous silicon layer 50 is sequentially stacked, and the semiconductor The semiconductor layer 40 and the ohmic contact layer 50 are formed on the gate insulating layer 30 on the gate electrode 24 by photolithography by etching the layer 40 and the doped amorphous silicon layer 50.

Next, as illustrated in FIGS. 5A to 5B, the first data wiring layers 651, 661, and 681 are deposited by depositing Cr or Mo alloys, and the second data wiring layer 652 by depositing Al or Ag alloys. , 662, and 682 are stacked, and then photo-etched to form a data line 62 intersecting the gate line 22 and a source electrode 65 connected to the data line 62 and extending to an upper portion of the gate electrode 26. The data line 62 is separated from the data pad 68 and the source electrode 64 connected to one end and includes a drain electrode 66 facing the source electrode 65 around the gate electrode 26. A data wiring is formed.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 6A and 6B, a film (low dielectric insulating film) containing polyorganosilsesquioxane or a polyorganosilsesquioxane with pores is grown by chemical vapor deposition (CVD) to form a protective film. Form 70. In this case, the low-dielectric CVD film is dissolved in a polyorganosilsesquioxane of Formula 1 or Formula 2 in a solvent such as propylene glycol monomethyl ether acetate (PGMEA) and then coated on a thin film transistor to form a film and N ₂ O or O _It can be made by depositing by PECVD method using ₂ . In addition, when the pore-forming polyorganosilsesquioxane is included, the SiO ₂ series cage compound may be combined in the molecule, or mixed with the pore-forming material and decomposed to form a film, and then deposited by PECVD. have.

Subsequently, the passivation layer 70 is patterned together with the gate insulating layer 30 by a photolithography process to form contact holes 74, 76, and 78 that expose the gate pad 24, the drain electrode 66, and the data pad 68. Form. Here, the contact holes 74, 76, 78 may be formed in an angled shape or a circular shape, the area of the contact holes 74, 78 exposing the pads 24, 68 is greater than 2mm x 60㎛. It is preferable that it is 0.5 mm x 15 micrometers or more.

Next, as shown in FIGS. 1 and 2, the ITO or IZO film is deposited, photo-etched, and connected to the drain electrode 66 through the first contact hole 76, and the second and second electrodes. The auxiliary gate pad 86 and the auxiliary data pad 88 are formed to be connected to the gate pad 24 and the data pad 68 through the three contact holes 74 and 78, respectively. It is preferable to use nitrogen as the gas used in the pre-heating process before laminating ITO or IZO. This is to prevent the metal oxide film from being formed on the upper portions of the metal films 24, 66, and 68 exposed through the contact holes 74, 76, and 78.

As described above, by using a film (low dielectric constant insulating film) containing polyorganosilsesquioxane or a polyorganosilsesquioxane having pores as the protective film 70, the parasitic capacitance problem can be solved, and thus the aperture ratio can be maximized. have. In addition, the deposition and etch rates are fast, reducing process time.

As described above, the method can be applied to a manufacturing method using five masks, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 7 to 9.

FIG. 7 is a layout view of a thin film transistor substrate for a liquid crystal display device according to a second exemplary embodiment of the present invention, and FIGS. 8 and 9 are lines VIII-VIII 'and IX-IX', respectively, of the thin film transistor substrate shown in FIG. The cross section for

First, the first gate wiring layers 221, 241, and 261 made of chromium (Cr) or molybdenum (Mo) alloy and the like on the insulating substrate 10, and aluminum (Al) or silver (Ag) alloy, as in the first embodiment. A gate wiring formed of a double layer of the second gate wiring layers 222, 242, and 262 formed of the back and the like is formed. The gate wiring includes a gate line 22, a gate pad 24, and a gate electrode 26.

The storage electrode line 28 is formed on the substrate 10 in parallel with the gate line 22. The storage electrode line 28 also includes a double layer of the first gate wiring layer 281 and the second gate wiring layer 282. The storage electrode line 28 overlaps with the conductive capacitor pattern 68 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line to be described later will be described. If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed. The same voltage as that of the common electrode of the upper substrate is usually applied to the storage electrode line 28.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and the storage electrode line 28 to cover the gate wirings 22, 24, 26, and 28.

On the gate insulating layer 30, semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed, and on the semiconductor patterns 42 and 48, n-type impurities such as phosphorus (P) have a high concentration. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56, and 58, the first data wiring layers 621, 641, 651, 661, and 681 made of Cr or Mo alloy and the like and the second data wiring layers 622 and 642 made of Al or Ag alloy and the like. Data lines 62, 64, 65, 66, and 68 formed of a double layer of 652, 662, and 682 are formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 68 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And data line portions 62, 68, and 65 made up of a source electrode 65, and are separated from the data line portions 62, 68, and 65, and formed on the gate electrode 26 or the channel portion C of the thin film transistor. On the other hand, the drain electrode 66 of the thin film transistor positioned on the opposite side of the source electrode 65 and the conductor pattern 64 for the storage capacitor located on the storage electrode line 28 are also included. When the storage electrode line 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed.

The data lines 62, 64, 65, 66, 68 may be formed of a single layer of Al or Ag as in the first embodiment.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

On the data lines 62, 64, 65, 66, 68, a protective film 70 made of a polyorganosilsesquioxane or a polyorganosilsesquioxane formed with pores (low dielectric constant insulating film) is formed. Therefore, even a thin thickness does not cause a parasitic capacity problem. Excellent adhesion to another film and step coverage. Moreover, since it is an inorganic insulating film, heat resistance is excellent compared with an organic insulating film. In this case, the dielectric constant of the low dielectric constant insulating film has a value between 1.5 and 4.0.

The protective film 70 has contact holes 76, 78, and 72 that expose the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor, and also the gate along with the gate insulating film 30. It has a contact hole 74 which exposes the pad 24.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as ITO or indium tin oxide (IZO), and is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor pattern 64 through the contact hole 72 to transmit an image signal to the conductor pattern 64. On the other hand, an auxiliary gate pad 86 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively, are formed. 68) and to protect the pads and the adhesion of the external circuit device, and is not essential, their application is optional.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 7 to 9 using four masks will be described in detail with reference to FIGS. 7 to 9 and 10A to 17C. .

First, as shown in FIGS. 10A to 10C, the first gate wiring layers 221, 241, 261, and 281 are laminated by depositing Cr or Mo alloy having excellent physicochemical properties, and the like, as in the first embodiment. The second gate wiring layers 222, 242, 262, and 282 are stacked by depositing the small Al or Ag alloy, and then photo-etched to include the gate lines 22, the gate pads 24, and the gate electrodes 26. The gate wiring and the sustain electrode line 28 are formed.

Next, as shown in FIGS. 11A and 11B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kPa and 500 kPa to 2,000 using chemical vapor deposition. 증착, 300 600 to 600 연속 continuous deposition, followed by deposition by a method such as sputtering the first conductive film 601 made of Cr or Mo alloy or the like and the second conductive film 602 made of Al or Ag alloy. After the conductor layer 60 is formed, the photosensitive film 110 is applied thereon with a thickness of 1 μm to 2 μm.

Thereafter, the photosensitive film 110 is irradiated with light through a mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 12B and 12C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed, and all the photoresist of the other portion B is removed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 13A and 13B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

In this way, as shown in FIGS. 13A and 13B, only the conductor layers of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 68 for the storage capacitor, are provided. All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 67 and 64 have the same shape as the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 14A and 14B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 thereunder are simultaneously removed by the dry etching method together with the first portion 114 of the photosensitive film. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions in which the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 14A and 14B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductor patterns 64, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as illustrated in FIGS. 15A and 15B, the source / drain conductor pattern 67 of the channel part C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in the " In the latter case of alternating between wet etching and dry etching, the side surface of the wet-etched source / drain conductor pattern 67 is etched, but the dry-etched intermediate layer pattern 57 is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include a mixture gas of CF ₄ and HCl or a mixture gas of CF ₄ and O ₂ , and CF ₄ and O ₂ . The semiconductor pattern 42 may be left at a uniform thickness. In this case, as shown in FIG. 15B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

Next, as shown in FIGS. 16A and 16B, a film (low dielectric insulating film) containing polyorganosilsesquioxane or a polyorganosilsesquioxane with pores is grown by chemical vapor deposition (CVD). The protective film 70 is formed. In this case, the low-dielectric CVD film is dissolved in a polyorganosilsesquioxane of Formula 1 or Formula 2 in a solvent such as propylene glycol monomethyl ether acetate (PGMEA) and then coated on a thin film transistor to form a film and N ₂ O or O _It can be made by depositing by PECVD method using ₂ . In addition, when the pore-forming polyorganosilsesquioxane is included, the SiO ₂ series cage compound may be combined in the molecule, or mixed with the pore-forming material and decomposed to form a film, and then deposited by PECVD. have. In this case, the dielectric constant of the low dielectric constant insulating film has a value between 1.5 and 4.0.

17A to 17C, the protective film 70 is etched together with the gate insulating film 30 to electrically conduct the drain electrode 66, the gate pad 24, the data pad 68, and the conductive capacitor. Contact holes 76, 74, 78, and 72 are formed to expose the sieve pattern 64, respectively. At this time, the area of the contact holes 74 and 78 exposing the pads 24 and 68 does not exceed 2 mm x 60 m, and is preferably 0.5 mm x 15 m or more.

Finally, as shown in FIGS. 8 to 10, a pixel connected to the drain electrode 66 and the conductive capacitor conductor 64 for the storage capacitor by depositing and etching the ITO layer or the IZO layer having a thickness of 400 kHz to 500 kHz. An electrode 82, an auxiliary gate pad 86 connected to the gate pad 24, and an auxiliary data pad 88 connected to the data pad 68 are formed.

In this case, when the pixel electrode 82, the auxiliary gate pad 86, and the auxiliary data pad 88 are formed of IZO, chromium etchant may be used as an etchant. Thus, the data exposed through the contact hole during the photolithography process for forming them may be used. Corrosion of the wiring or gate wiring metal can be prevented. Such chromium etchant includes (HNO ₃ / (NH ₄ ) ₂ Ce (NO ₃ ) ₆ / H ₂ O). In addition, in order to minimize the contact resistance of the contact portion, it is preferable to stack IZO in a range of 200 ° C. or less at room temperature, and a target used to form the IZO thin film preferably includes In ₂ O ₃ and ZnO. The content of ZnO is preferably in the range of 15-20 wt%.

On the other hand, as a gas used in the pre-heating process before laminating ITO or IZO, it is preferable to use nitrogen, which is the metal film 24 exposed through the contact holes 72, 74, 76, and 78. This is to prevent the metal oxide film from being formed on the upper portions of 64, 66 and 68.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48 may be formed using a single mask, and the manufacturing process may be simplified by separating the source electrode 65 and the drain electrode 66 in this process.

The low dielectric constant insulating film according to the present invention may also be used as a buffer layer separating the color filter and the thin film transistor in an array on color filter (AOC) structure in which a thin film transistor array is formed on the color filter.

18 is a layout view of a thin film transistor substrate according to a third exemplary embodiment of the present invention, and FIG. 19 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 18 along a cutting line XIX-XIX ′. 19 illustrates a lower substrate as a thin film transistor substrate and an upper substrate facing the same.

First, the lower substrate includes a lower layer 201 made of any one of materials such as copper, copper alloy, silver, silver alloy, aluminum and aluminum alloy, chromium, molybdenum, molybdenum alloy, chromium nitride, and the like on the upper portion of the insulating substrate 100. Data wirings 120, 121, and 124 including an upper layer 201 made of any one of materials such as molybdenum nitride are formed.

The data wires 120, 121, and 124 are connected to the data lines 120 and the data lines 120 extending in the vertical direction, and receive data signals from the outside and transmit them to the data lines 120. And a light blocking unit 121 for blocking light incident to the semiconductor layer 170 of the thin film transistor formed later from the lower portion of the substrate 100 by the branch of the data line 120. Here, the light blocking unit 121 also has a function of a black matrix that blocks light leakage, and may be formed by disconnecting the data line 120 and disconnected wiring.

Although the data wirings 120, 121, and 124 are formed of a double layer, copper or copper alloy or aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr) ) And a single film made of a conductive material such as tantalum (Ta).

Here, the lower layer 201 is resisted considering that the pixel wirings 410, 411, 412 and the auxiliary pads 413, 414 formed after the data wirings 120, 121, and 124 are indium tin oxide (ITO). For example, this small material is formed of aluminum, aluminum alloy, silver, silver alloy, copper (Cu), copper alloy, and the like, and the upper layer 202 is formed of chromium, which is a material having good contact properties with other materials. will be. As a specific example, the lower layer 201 may be formed of Al-Nd, and the upper layer 202 may be formed of CrNx.

In the case where the pixel wirings 410, 411, 412 and the auxiliary pads 413, 414 are indium zinc oxide (IZO), it is preferable to make the data wirings 120, 121, and 124 a single layer of aluminum or an aluminum alloy. Since copper has excellent contact properties with IZO and ITO, it may be formed from a single film of copper.

On the lower insulating substrate 100, color filters 131, 132, and 133 of red (R), green (G), and blue (B), whose edges overlap the edges of the data lines 120 and 121, are respectively formed. Formed. The color filters 131, 132, and 133 may be formed to cover all of the data lines 120.

A buffer layer 140 made of a film (low dielectric insulating film) containing polyorganosilsesquioxane or polyorganosilsesquioxane with pores formed on the data wires 120, 121, 124 and the color filters 131, 132, and 133. ) Is formed. Here, the buffer layer 140 is a layer for preventing outgassing from the color filters 131, 132, and 133 and preventing the color filter itself from being damaged by heat and plasma energy in a subsequent process. In addition, since the buffer layer 140 separates the lowermost data lines 120, 121, and 124 from the thin film transistor array, the lower the dielectric constant and the thicker the thickness, the more advantageous it is to reduce the parasitic capacitance therebetween. In view of this point, a film containing a polyorganosilsesquioxane (low dielectric constant CVD film) is suitable for use as the buffer layer 140. That is, the dielectric constant of the buffer layer is low as a value between 1.5 and 4, the deposition rate is very fast, and the price is lower than that of an organic insulating material such as bisbenzocyclobutene (BCB) or perfluorocyclobutene (PFCB). In addition, the thin film including the polyorganosilsesquioxane has excellent insulation properties in a wide temperature range from room temperature to 400 ℃.

On the buffer layer 140, any one of a lower layer 501 made of any one of materials such as copper, copper alloy, silver, silver alloy, aluminum, and aluminum alloy and material such as chromium, molybdenum, molybdenum alloy, chromium nitride, and molybdenum nitride The gate wiring of the double layer structure which consists of one upper layer 502 is formed.

The gate line extends in the horizontal direction and is connected to the gate line 150 and the gate line 150 defining the unit pixel by crossing the data line 120 to receive the scan signal from the outside to the gate line 150. And a gate electrode 151 of the thin film transistor which is a part of the gate pad 152 and the gate line 150 to transfer.

Here, the gate line 150 overlaps with the pixel electrode 410 to be described later to form a storage capacitor that improves the charge storage capability of the pixel, and the sustain is generated by overlapping the pixel electrode 410 and the gate line 150 to be described later. If the capacitance is not sufficient, a common electrode for the storage capacitance may be formed.

As described above, when the gate wiring is formed in two or more layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials. An example is a double layer or a double layer of Cu＼Cr. In addition, a chromium nitride film, a molybdenum nitride film, or the like may be added to improve contact characteristics.

The gate wirings 150, 151, and 152 may be formed of a single film of copper, aluminum, or an aluminum alloy having low resistance.

The low temperature deposition gate insulating layer 160 is formed on the gate lines 150, 151, and 152 and the buffer layer 140. In this case, the low temperature deposition gate insulating film 160 may be formed of an organic insulating film, a low temperature amorphous silicon oxide film, a low temperature amorphous silicon nitride film, or the like. In the thin film transistor structure according to the present invention, since the color filter is formed on the lower substrate, the gate insulating film may be deposited at a low temperature, not a normal insulating film deposited at a high temperature, for example, low temperature deposition capable of depositing at a low temperature of 250 ° C. or less. An insulating film is used.

The double layer semiconductor layer 171 is formed in an island shape on the gate insulating layer 160 of the gate electrode 151. In the double layer semiconductor layer 171, the lower semiconductor layer 701 is made of amorphous silicon having a high band gap, and the upper semiconductor layer 702 is made of ordinary amorphous silicon having a lower band gap than the lower semiconductor 701. . For example, the band gap of the lower semiconductor layer 701 may be 1.9 to 2.1 eV, and the band gap of the upper semiconductor layer 702 may be 1.7 to 1.8 eV. Here, the lower semiconductor layer 701 is formed to a thickness of 50 to 200 GPa, and the upper semiconductor layer 702 is formed to a thickness of 1000 to 2000 GPa.

As such, a band offset corresponding to the difference between the band gaps of the two layers is formed between the upper semiconductor layer 702 and the lower semiconductor layer 701 having different band gaps. At this time, when the TFT is turned on, a channel is formed in the band offset region located between the two semiconductor layers 701 and 702. Since this band offset region has basically the same atomic structure, there are few defects and favorable TFT characteristics can be expected.

The semiconductor layer 171 may be formed as a single layer.

On the semiconductor layer 171, ohmic contact layers 182 and 183 including amorphous silicon or microcrystalline silicon or metal silicide doped with a high concentration of n-type impurities such as phosphorus (P) are mutually formed. It is formed separately.

On the ohmic contacts 182 and 183, pixel wirings 410, 411 and 412 including source and drain electrodes 412 and 411 and pixel electrodes 410 made of ITO are formed. The source electrode 412 is connected to the data line 120 through the contact hole 161 formed in the gate insulating layer 160 and the buffer layer 140. The drain electrode 411 is connected to the pixel electrode 410 and receives an image signal from the thin film transistor and transmits the image signal to the pixel electrode 410. The pixel wirings 410, 411 and 412 are made of a transparent conductive material such as ITO or IZO.

In addition, the auxiliary gate pad 413 and the auxiliary data pad connected to the gate pad 152 and the data pad 124 through the contact holes 162 and 164 in the same layer as the pixel wirings 410, 411, and 412, respectively. 414 is formed. Here, the auxiliary gate pad 413 is in direct contact with the chrome film, which is the upper film 502 of the gate pad 152, and the auxiliary data pad 414 is also a chrome film, which is the upper film 202 of the data pad 124. Is in direct contact with In this case, when the gate pad 152 and the data pad 124 include a chromium nitride film or a molybdenum nitride film, the auxiliary gate pad 413 and the auxiliary data pad 414 are in contact with the chromium nitride film or the molybdenum nitride film. desirable. These are not essential to complement the adhesion between the pads 152 and 124 and the external circuit device and to protect the pads, and their application is optional. The pixel electrode 410 also overlaps the neighboring gate line 150 and the data line 120 to increase the aperture ratio, but may not overlap.

Here, the ohmic contact layers 182 and 183 have a function of reducing contact resistance between the source and drain electrodes 412 and 411 of the ITO and the semiconductor layer 171, and may be a microcrystalline silicon layer or molybdenum, nickel, Metal silicides such as chromium may be included, and a metal film for silicide may remain.

A passivation layer 190 is formed on the source and drain electrodes 412 and 411 to protect the thin film transistor, and a photosensitive colored organic layer 430 having a dark color having excellent light absorption is formed thereon. have. In this case, the colored organic layer 430 serves to block light incident to the semiconductor layer 171 of the thin film transistor, and adjusts the height of the colored organic layer 430 to face the lower insulating substrate 100. It is used as a spacer to maintain the gap between the insulating substrate 200. Here, the passivation layer 190 and the organic layer 430 may be formed along the gate line 150 and the data line 120, and the organic layer 430 blocks light leaking around the gate line and the data line. It can have a role.

In this case, when the organic layer 430 is designed to cover all the gaps between the pixel electrode and each metal layer, as in the thin film transistor substrate according to the fourth embodiment of the present invention described below, light blocking is performed on the upper substrate. There is an advantage that does not need to design a separate black matrix for.

Meanwhile, the upper substrate 200 is made of ITO or IZO, and the common electrode 210 for generating an electric field together with the pixel electrode 410 is formed on the entire surface.

Next, a method of manufacturing the thin film transistor substrate according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 20A to 27B and FIGS. 18 and 19.

First, as shown in FIGS. 20A and 20B, a conductive material having low resistance, such as aluminum, an aluminum alloy, copper, or a copper alloy, and an excellent contact property with ITO such as chromium or molybdenum or titanium, chromium nitride, or molybdenum nitride, etc. The material is sequentially deposited by a method such as sputtering, and is dry or wet etched by a photolithography process using a mask to form a double layer structure of a lower layer 201 and an upper layer 202 on the lower insulating substrate 100. The data wires 120, 121, and 124 including the data pads 124 and the light blocking unit 121 are formed.

As described above, considering that the pixel wirings 410, 411, 412 and the auxiliary pads 413, 414 formed thereafter are indium tin oxide (ITO), aluminum or aluminum alloys or copper (Cu) or copper alloys may be used. Although the data wiring including the lower layer 201 and the upper layer 202 of chromium, molybdenum or titanium is formed, the pixel wirings 410, 411 and 412 and the auxiliary pads 413 and 414 are indium zinc oxide (IZO). It can be formed of a single film of aluminum or aluminum alloy, and can be formed of a single film of copper or copper alloy to simplify the manufacturing process.

Next, as shown in FIGS. 21A and 21B, a photosensitive material including pigments of red (R), green (G), and blue (B) is sequentially applied, and patterned by a photo process using a mask to display red (R), The color filters 131, 132, and 133 of green (G) and blue (B) are sequentially formed. At this time, the red (R), green (G), and blue (B) color filters 131, 132, and 133 are formed using three masks, but they are formed by moving one mask to reduce manufacturing costs. It may be. In addition, using a laser transfer method or a print method can be formed without using a mask, thereby minimizing the manufacturing cost. At this time, as shown in the figure. The edges of the color filters 131, 132, and 133 of red (R), green (G), and blue (B) may be formed to overlap the data line 120.

Subsequently, as shown in FIGS. 22A and 22B, a film (low dielectric insulating film) containing a polyorganosilsesquioxane or a polyorganosilsesquioxane formed with pores on the insulating substrate 100 is deposited using chemical vapor deposition (CVD). Growing) by a method to form a buffer layer 140.

Subsequently, a physicochemically stable material such as chromium or molybdenum or titanium or chromium nitride or molybdenum nitride and a conductive material having a low resistance such as aluminum or an aluminum alloy or copper or a copper alloy are successively deposited by sputtering, and the like. Patterning is performed by a photolithography process to form gate lines 150, 151, and 152 including the gate line 150, the gate electrode 151, and the gate pad 152 on the buffer layer 140.

In this case, the gate lines 150, 151, and 152 may be formed in a single layer structure.

Next, as shown in FIG. 23, the low-temperature deposition gate insulating layer 160, the first amorphous silicon film 701, and the second amorphous silicon film 702 on the gate wirings 150, 151, and 152 and the organic insulating film 140. And an amorphous silicon film 180 doped with impurities.

The low temperature deposition gate insulating layer 160 may be formed using an organic insulating layer, a low temperature amorphous silicon oxide film, a low temperature amorphous silicon nitride film, or the like, which may be deposited even at a deposition temperature of 250 ° C. or lower.

The first amorphous silicon film 701 is formed of an amorphous silicon film having a high band gap, for example, a band gap of 1.9 to 2.1 eV, and the second amorphous silicon film 702 has a band gap of the first amorphous silicon film. For example, it is formed of a conventional amorphous silicon film having a band gap of less than 701, for example, 1.7 to 1.8 eV. In this case, the first amorphous silicon film 701 may be deposited by CVD by adding an appropriate amount of CH ₄ , C ₂ H ₂ , or C ₂ H ₆ to SiH _{4, which} is a raw material gas of the amorphous silicon film. . For example, when SiH ₄ : CH ₄ is added to a CVD apparatus at a ratio of 1: 9 and the deposition process is performed, an amorphous silicon film containing about 50% of C and having a band gap of 2.0 to 2.3 eV is deposited. can do. As such, the band gap of the amorphous silicon layer is affected by the deposition process conditions, and the band gap can be easily adjusted in the range of 1.7 to 2.5 eV, depending on the amount of carbon compound added.

In this case, the low temperature deposition gate insulating layer 160, the first amorphous silicon film 701, the second amorphous silicon film 702, and the amorphous silicon film 180 doped with impurities are continuous without breaking the vacuum in the same CVD apparatus. Can be deposited.

Next, as shown in FIGS. 24A and 24B, the first amorphous silicon film 701, the second amorphous silicon film 702, and the amorphous silicon film 180 doped with impurities are patterned by a photolithography process using a mask. The island-shaped semiconductor layer 171 and the ohmic contact layer 181 are formed, and at the same time, the data line 120, the gate pad 152, and the data pad 124 are formed on the low temperature deposition gate insulating layer 160 and the organic insulating layer 140. Contact holes 161, 162, and 164 are respectively formed.

In this case, except for the upper portion of the gate electrode 151, all of the first and second amorphous silicon layers 701 and 702 and the amorphous silicon layer 180 doped with impurities should be removed, and the upper portion of the gate pad 152 may be removed. Along with the first and second amorphous silicon films 701 and 702 and the amorphous silicon film 180 doped with impurities, the gate insulating layer 160 should be removed, and the upper portion of the data line 120 and the data pad 124 may be removed. The organic insulating layer 140 should be removed along with the first and second amorphous silicon layers 701 and 702, the amorphous silicon layer 180 doped with impurities, and the low temperature deposition gate insulating layer 160.

In order to form this in a photolithography process using one mask, a photoresist pattern having a different thickness is used as an etching mask. This will be described with reference to FIGS. 25 and 26 together.

First, as shown in FIG. 25, after the photoresist film is coated on the impurity doped amorphous silicon film 180 to a thickness of 1 μm to 2 μm, the photoresist film is irradiated with light through a photolithography process. The photoresist patterns 312 and 314 are formed.

In this case, the first portion 312 positioned above the gate electrode 151 among the photoresist patterns 312 and 314 is formed to have a thickness greater than that of the remaining second portions 314, and the data line 120 and the data pad are formed. The photoresist may not exist on the portion 124 and the gate pad 152. It is preferable to make the thickness of the 2nd part 314 into 1/2 or less of the thickness of the 1st part 312, for example, it is good that it is 4,000 Pa or less.

As described above, there may be various ways of varying the thickness of the photosensitive film according to the position. Here, the case of using the positive photosensitive film will be described.

When the light is irradiated to the photosensitive film through a mask 1000 that can control the amount of light by forming a pattern smaller than the resolution of the exposure machine, for example, a slit or lattice pattern in the B region or a semi-transparent film, Depending on the amount or intensity of light irradiated, the degree of decomposition of the polymers is different. At this time, if the exposure is stopped at a time when the polymers of the C region completely exposed to light are completely decomposed, the amount of light passing through the B region where the slit or translucent film is formed is smaller than that of the portion completely exposed to the light. Part of the photoresist in the region is decomposed and the rest remains undecomposed. The longer exposure time decomposes all the molecules, so it should be avoided.

When the photoresist is developed, the first portion 312 in which the molecules are not decomposed remains almost intact, and the second portion 314 which is irradiated with less light remains in a thinner thickness than the first portion 312, and is completely exposed to light. The photosensitive film is almost removed at the portion corresponding to the exposed C region.

Through this method, photoresist patterns having different thicknesses are formed according to positions.

Next, as shown in FIG. 26, the amorphous silicon film 180, the second amorphous silicon film 702, and the first amorphous silicon film doped with impurities using the photoresist patterns 312 and 314 as an etching mask are used. 702 and the low temperature deposition gate insulating layer 160 are dry etched to complete the contact hole 162 exposing the gate pad 152, and expose the buffer layer 140 in the C region. Subsequently, dry etching the buffer layer 140 in the C region using the photoresist patterns 312 and 314 as an etching mask to complete the contact holes 161 and 164 exposing the data line 120 and the data pad 124. .

Subsequently, the operation of completely removing the second portion 314 of the photoresist film is performed. In this case, an ashing process using oxygen may be added to completely remove the photoresist residue of the second portion 314.

In this way, the second portion 314 of the photoresist pattern is removed, and the amorphous silicon film 180 doped with impurities is exposed, and the first portion 312 of the photoresist pattern is formed on the second portion 312 of the photoresist pattern. It remains reduced by thickness.

Next, the amorphous silicon film 180 doped with impurities and the first and second amorphous silicon films 701 and 702 under the impurities are etched and removed using the first portion 312 of the remaining photoresist pattern as an etching mask. As a result, an island-like semiconductor layer 171 and an ohmic contact layer 181 are left on the low temperature deposition gate insulating layer 160 on the gate electrode 151.

Finally, the remaining first portion 312 of the photoresist film is removed. Here, an ashing process using oxygen may be added to completely remove the photoresist residue of the first portion 312.

Next, as shown in FIGS. 27A and 27B, an ITO layer is deposited and patterned by a photolithography process using a mask to form a pixel electrode 410, a source electrode 412, a drain electrode 411, and an auxiliary gate pad ( 413 and auxiliary data pads 414. In this case, IZO may be used instead of ITO.

Subsequently, the resistive contact layer 181 is etched between the source electrode 412 and the drain electrode 411 as an etching mask to form a resistive contact layer pattern separated into two parts 182 and 183. The semiconductor layer 171 is exposed between the source electrode 412 and the drain electrode 411.

Finally, as shown in FIGS. 18 and 19, an insulating material such as silicon nitride or silicon oxide and an insulating material such as a photosensitive organic material including black pigment are sequentially stacked on the lower insulating substrate 100, and a mask is applied. The exposure process is performed using the photolithography process to form the colored organic layer 430, and the protective layer 190 is formed by etching the insulating material under the substrate using the colored organic layer 430 as an etching mask. In this case, the colored organic layer 430 may block light incident to the thin film transistor, and may be formed on the gate line or the data line to provide a function of blocking light leaking around the wire. In addition, as in the embodiment of the present invention, the height of the organic layer 430 may be adjusted to be used as a spacer.

Meanwhile, the common electrode 210 is formed by stacking a transparent conductive material of ITO or IZO on the upper insulating substrate 200.

In this case, when the colored organic layer 430 is designed to cover all the gaps between the pixel electrode 410 and each metal layer, it is not necessary to design a separate black matrix for light blocking on the upper substrate. have.

When the gate line 150 and the pixel electrode 410 are designed to have a predetermined interval, it is necessary to cover the light leaking portion between the pixel electrode 410 and the gate line 150. To this end, a portion of the data line 120 formed under the color filters 131, 132, and 133 is extended to protrude in the direction of the gate line 150 to close the gap between the gate line 150 and the pixel electrode 410. It can be formed to cover up. In this case, the colored organic layer 430 may be covered in a portion that cannot be covered by the data line 120, that is, an area between two neighboring data lines 120.

On the other hand, although not shown in the drawing, a black matrix is formed on the same layer as the gate wirings 150, 151 and 152 to block light leaking around the edge of the screen display with a material for forming the gate wirings 150, 151 and 152. The vertical portion of the black matrix is formed on the same layer as the data lines 120, 121, and 124 to prevent light leaking around the edge of the screen display with a metal material for forming the data lines 120, 121, and 124. An addition can be formed.

As such, the horizontal and vertical portions of the black matrix are formed of a material forming the gate wirings 150, 151 and 152 and the data wirings 120, 121 and 124 to block light leaking around the edges of the screen display. The light leaking area between the gate line 150 and the pixel electrode 410 is covered by the data wires 120, 121, and 124, and the light leaking area between two data wires 150 that is adjacent to the colored organic film 430. In this case, the data wirings, the gate wirings, and the spacers may cover all areas where light leaks from the thin film transistor substrate, and there is no need to form a separate black matrix on the upper substrate. Therefore, it is not necessary to consider the alignment error between the upper substrate and the lower substrate can improve the aperture ratio. In addition, since the gate insulating layer 160 and the buffer layer 140 having a low dielectric constant are formed between the data line 120 and the pixel electrode 410, the parasitic capacitance generated between them can be minimized, so that the characteristics of the display device can be minimized. As a result, the aperture ratio can be maximized since there is no need to space between them.

As described above, in the embodiment of the present invention, in order to stably implement the thin film transistor substrate forming the thin film transistor on the color filter, the TFT is manufactured under low temperature process conditions. That is, in order to prevent damage of the color filter by the high temperature process, the gate insulating film is formed of the low temperature deposition insulating film, and in order to prevent deterioration of the characteristics of the channel caused by contact with the low temperature deposition gate insulating film, the channel is formed by the low temperature deposition gate insulating film and the semiconductor. It is not formed at the interface of the layer but is formed on the bulk side of the semiconductor layer.

The low dielectric constant CVD film according to the present invention is also useful as a protective film formed between the color filter and the pixel electrode in a color filter on array (COA) structure for forming a color filter on the thin film transistor array. This will be described in detail with reference to the drawings.

First, the structure of the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 28 to 29.

FIG. 28 is a layout view of a thin film transistor substrate for a liquid crystal display according to a fourth exemplary embodiment of the present invention, and FIG. 29 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 28 taken along the line XXIX-XXIX '.

First, a gate made of a metal or a conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) or the like on the insulating substrate 10. Wiring is formed. The gate wiring is connected to the scan signal line or the gate line 22 extending in the horizontal direction, and the gate pad 24 and the gate that receive the scan signal from the outside and transmit the scan signal to the gate line 22 from the outside. A gate electrode 26 of the thin film transistor that is part of the line 22. The protruding portion of the gate line 22 overlaps with the conductive pattern 64 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor that improves the charge storage capability of the pixel.

The gate wirings 22, 24, and 26 may be formed in a single layer, but may also be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials, and a double layer of Cr / Al (or Al alloy) or Al / Mo Bilayers are an example. In the embodiment of the present invention, the gate wirings 22, 24, and 26 are formed of a lower layer made of chromium and an upper layer made of aluminum-neodymium.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and the substrate 10, and the gate electrode 24 is covered with the gate insulating film 30.

A semiconductor pattern 40 made of a semiconductor such as hydrogenated amorphous silicon is formed on the gate insulating layer pattern 30, and is heavily doped with n-type impurities such as phosphorus (P) on the semiconductor pattern 40. Ohmic contact layers 55 and 56 made of amorphous silicon are formed.

On the ohmic contacts 55 and 56, source and drain electrodes 65 and 66 of thin film transistors, which are part of a data line made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, and Ta, are formed, respectively. have. The data line is formed in a vertical direction and is connected to one end of the data line 62 and the data line 62 connected to the source electrode 65, and the data pad 68 and the gate line to which image signals from the outside are applied. Also included is a conductor pattern 64 for a storage capacitor which overlaps with the protrusion of (22).

The data lines 62, 64, 65, 66, and 68 may be formed in a single layer like the gate lines 22, 24, and 26, but may be formed in a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

The ohmic contacts 55 and 56 lower the contact resistance between the semiconductor pattern 40 below and the data lines 62, 64, 65, 66, and 68.

Although not illustrated, an interlayer insulating layer made of an insulating material such as silicon oxide or silicon nitride may be formed on the data lines 62, 64, 65, 66, and 68 and the semiconductor pattern 40 not covered by the data lines. .

The red, green, and blue color filters R, G, and B having the openings C1 and C2 exposing the drain electrode 65 and the conductive capacitor pattern 64 are formed in the pixel region above the gate insulating layer 30. It is formed in the vertical direction. Here, the boundaries of the color filters R, G, and B of red, green, and blue are shown to coincide with each other on the upper part of the data line 62, but overlapped with each other on the upper part of the data line 62 to leak light between the pixel areas. It may have a function of blocking and is not formed in the pad portion where the gate and data pads 24 and 68 are formed.

On the blue, green, and blue color filters 81, 82, and 83, a protective film 70 made of a polyorganosilsesquioxane or a polyorganosilsesquioxane formed with pores (low dielectric insulating film) is formed. have. The protective film 90, together with the gate insulating film 30, has contact holes 74, 78, and 76 that expose the gate pad 24, the data pad 68, the drain electrode 66, and the conductive pattern 64 for the storage capacitor. , 72). In this case, the contact holes 76 and 72 exposing the drain electrode 66 and the conductor pattern 64 for the storage capacitor are located inside the openings C1 and C2 of the color filters R, G, and B, and described above. As described above, when the interlayer insulating film is added to the lower portion of the color filters R, G, and B, it has the same pattern as the interlayer insulating film.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and is physically and electrically connected to the drain electrode 66 through a contact hole 76 to receive an image signal. I receive it. The pixel electrode 82 overlaps the gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor pattern 64 through the contact hole 72 to transmit an image signal to the conductor pattern 64. On the other hand, an auxiliary gate pad 84 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively, are formed. 68) and to protect the pads and the adhesion of the external circuit device, and is not essential, their application is optional.

Next, a method of manufacturing a thin film transistor array substrate for a liquid crystal display device according to a first embodiment of the present invention will be described in detail with reference to FIGS. 30A to 34B and FIGS. 28 and 29.

First, as shown in FIGS. 30A to 30B, a conductive layer such as a metal is laminated by a sputtering method, and then dry or wet etched by a first photolithography process using a mask to form a gate line 22 on the substrate 10. The gate wiring including the gate pad 24 and the gate electrode 26 is formed.

Next, as shown in FIGS. 31A and 31B, each of the semiconductors such as the gate insulating film 30, the hydrogenated amorphous silicon, and the amorphous silicon doped at a high concentration with n-type impurities such as phosphorus (P) are respectively used by chemical vapor deposition. Continuous deposition is performed at a thickness of 1,500 5,000 to 5,000 Å, 500 Å to 2,000 Å, 300 Å to 600 Å, and patterned by a photolithography process using a mask to sequentially pattern the amorphous silicon layer and the doped amorphous silicon layer to form a semiconductor pattern (40 ) And the ohmic contact layer 50.

32A and 32B, a conductive layer such as a metal is deposited to a thickness of 1,500 Å to 3,000 Å by a sputtering method, and then patterned by a photolithography process using a mask to form a data line 62, a source. A data wiring including an electrode 65, a drain electrode 66, a data pad 68, and a conductor pattern 64 for a storage capacitor is formed. Subsequently, the ohmic contact layer 50 that is not covered by the source electrode 65 and the drain electrode 66 is etched to expose the semiconductor layer 40 between the source electrode 65 and the drain electrode 66 and the ohmic contact layer 55. , 56) into two parts. Subsequently, silicon nitride or silicon oxide can be laminated to form an interlayer insulating film (not shown).

Next, after forming the data wirings 62, 64, 65, 66, and 68 and an interlayer insulating film (not shown), a photosensitive organic material including red, green, and blue pigments is formed as shown in FIGS. 33A to 33B. Each is applied in turn, and the red, green, and blue color filters (R, G, and B) are sequentially formed through a photographic process. In this case, when the red, green, and blue color filters R, G, and B are formed in the photolithography process, the openings C1 and C2 that expose the drain electrode 66 and the conductive capacitor pattern 64 for the storage capacitor are also formed. . This is because a good profile is formed later when forming a contact hole between the drain electrode 66 and the storage capacitor conductor pattern 64 in the protective film 70.

34A and 34B, a protective film 70 is formed of a film (low dielectric insulating film) containing polyorganosilsesquioxane or polyorganosilsesquioxane with pores formed therein. And patterned together with the gate insulating film 30 by a photolithography process using a mask to form contact holes 72, 74, 76, and 78. At this time, the contact holes 76 and 74 exposing the drain electrode 66 and the conductor pattern 64 for the storage capacitor are formed inside the openings C1 and C2 formed in the color filters R, G, and B. do. As described above, in the present invention, the openings C1 and C2 are formed in advance in the color filters R, G, and B, and then the protective film 70 is patterned to form the drain electrode 66 and the conductive capacitor pattern 64 for the storage capacitor. The profile of the contact holes 76, 74 can be formed satisfactorily by forming the contact holes 76, 74 exposing the light.

Finally, as shown in FIGS. 1 to 3, the ITO or IZO layer having a thickness of 400 μs to 500 μs is deposited and etched by a photolithography process using a mask using a mask to etch the pixel electrode 82 and the auxiliary gate pad. 84 and auxiliary data pad 88 are formed.

As described above, the method can be applied to a manufacturing method using five masks, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings, and the manufacturing method has been described with reference to the second and fourth embodiments and will be omitted.

First, a structure of a thin film transistor array substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 35 to 37.

35 is a layout view of a thin film transistor substrate for a liquid crystal display according to a fifth exemplary embodiment of the present invention, and FIGS. 36 and 37 are lines XXXVI-XXXVI 'and XXXVII-XXXVII', respectively, of the thin film transistor substrate illustrated in FIG. 35. A cross-sectional view taken along the line.

35 to 36, most of the structure is the same as the structure according to the second embodiment.

However, as in the fourth embodiment, red, green, and blue color filters R and G having openings C1 and C2 exposing a drain electrode 66 and a conductive capacitor conductor 68 on the top of the thin film transistor array. , B) is formed thereon, and a protective film 70 made of a polyorganosilsesquioxane or a polyorganosilsesquioxane formed with pores (low dielectric insulating film) is formed by chemical vapor deposition. have.

The present invention can be applied in various ways, as well as the embodiments shown. For example, the present invention may be usefully applied to a display requiring low temperature processing conditions, such as a plastic liquid crystal display device that has emerged to reduce weight and improve impact resistance. The same applies to the thin film transistor substrate for reflective liquid crystal display device which displays an image using external light.

In addition, the gate insulating film must maintain a dense film quality in consideration of the interface characteristics with the semiconductor layer 40 made of amorphous silicon. However, the denser the film quality, the slower the deposition rate has a disadvantage of longer process time. On the other hand, when the dense film quality is maintained only to a thickness of about 500 kPa from the surface in contact with the semiconductor layer 40, it is known that there is no problem in the operation of the thin film transistor. Therefore, in the embodiment of the present invention, when the lower portion of the gate insulating film is formed of the low dielectric constant insulating film of the present invention having a high deposition rate, and the upper portion of the gate insulating film is formed of a silicon nitride film having a high film quality, the performance of the thin film transistor is not deteriorated. Process time can be shortened.

In the above embodiments, the low dielectric CVD film includes not only a single film of polyorganosilsesquioxane but also a double film of silicon nitride (SiN _x ) / polyorganosilsesquioxane.

In the present invention, by forming a protective film using a film containing polyorganosilsesquioxane or a film containing polyorganosilsesquioxane with pores (low dielectric insulating film), the parasitic capacitance problem can be solved to realize a high opening ratio structure. It is possible to shorten the process time, and to solve the problems such as the increase in the material cost generated when the organic insulating layer is used, the limitation of subsequent processes due to the lack of heat resistance, and the large etching error due to the lack of adhesion with neighboring films.

Claims (25)

Insulation board, A first signal line formed on the insulating substrate, A first insulating film formed on the first signal line, A second signal line formed on the first insulating film and crossing the first signal line; A thin film transistor connected to the first signal line and the second signal line, A second insulating film including a low dielectric insulating film containing polyorganosilsesquioxane or a polyorganosilsesquioxane having pores and formed on the thin film transistor and having a first contact hole exposing a predetermined electrode of the thin film transistor , A pixel electrode formed on the second insulating layer and connected to a predetermined electrode of the thin film transistor through the first contact hole; Thin film transistor substrate comprising a. In claim 1, The first insulating film is a thin film transistor substrate comprising a lower film of the low dielectric constant insulating film and an upper film made of silicon nitride. In claim 1, The pixel electrode is a thin film transistor substrate made of an opaque conductive material or a transparent conductive material that reflects light. In claim 3, The second insulating film has a concave-convex pattern on its surface. In claim 1, A thin film transistor substrate having a pore size of 5 to 500 GPa of the low dielectric insulating film. In claim 1, The low-k dielectric film polyorganosilsesquioxane thin film transistor substrate composition is in the range of _1.2-1.8 SiO _0.3-2.0 of the R. In claim 1, A thin film transistor substrate having a dielectric constant of 2 to 3 of the low dielectric insulating film including the polyorganosilsesquioxane. In claim 1, The low dielectric insulating film has a structure of a single film of polyorganosilsesquioxane or a double film of silicon nitride (SiN _x ) / polyorganosilsesquioxane. A data wiring including a data line formed on the insulating substrate, Red, green and blue color filters formed on the insulating substrate, A buffer layer having a low dielectric constant insulating film and formed over the data line and the color filter and having a first contact hole for exposing a predetermined portion of the data line; A gate line formed on the buffer layer and including a gate line crossing the data line to define a pixel and a gate electrode connected to the gate line; A gate insulating film formed on the gate wiring and having a second contact hole exposing at least a portion of the first contact hole, A semiconductor layer formed on the gate insulating film on the gate electrode; A source electrode connected to the data line through the first contact hole and the second contact hole and at least partially contacting the semiconductor layer, a drain electrode facing the source electrode on the semiconductor layer, and the drain A pixel wiring including a pixel electrode connected to the quoted electrode Thin film transistor substrate comprising a. In claim 9, The semiconductor layer pattern includes a double layer structure of a first amorphous silicon film and a second amorphous silicon film having a band gap lower than that of the first amorphous silicon film. In claim 10, And a light blocking part formed of the same material as the data line and positioned in a portion corresponding to the semiconductor layer pattern. In claim 11, The light blocking unit extends in the gate line direction. In claim 1, The thin film transistor substrate of which the dielectric constant of the buffer layer has a value between 1.5 and 4. Insulation board, A gate wiring formed on the substrate and including a gate line, a gate electrode, and a gate pad; A gate insulating film formed on the gate wiring and having at least a contact hole exposing the gate pad; A semiconductor layer pattern formed on the gate insulating film, A contact layer pattern formed on the semiconductor layer pattern, A data line formed on the contact layer pattern and having substantially the same shape as the contact layer pattern and including a source electrode, a drain electrode, a data line, and a data pad; A protective film pattern formed on the data line and having a contact hole for exposing the gate pad, the data pad and the drain electrode, the protective film pattern comprising a low dielectric constant insulating film, A transparent electrode layer pattern electrically connected to the exposed gate pad, data pad, and drain electrode, respectively Thin film transistor substrate for a liquid crystal display device comprising a. The method of claim 14, A storage capacitor line formed in the same layer as the gate wiring on the insulating substrate, A semiconductor pattern for a storage capacitor, which overlaps with the storage capacitor and is formed on the same layer as the semiconductor pattern; A contact layer pattern for a storage capacitor formed on the semiconductor pattern for the storage capacitor and having the same planar shape as the semiconductor pattern for the storage capacitor; And a conductor pattern for a storage capacitor formed on the contact layer pattern for the storage capacitor and having the same planar shape as the semiconductor pattern for the storage capacitor. The conductive capacitor pattern for the storage capacitor is connected to a portion of the transparent electrode pattern. The method of claim 14, The dielectric constant of the low dielectric constant insulating film has a value between 1.5 and 4. Forming a gate line on the insulating substrate, the gate line including a gate line, a gate electrode connected to the gate line, and a gate pad connected to the gate line; Forming a gate insulating film, Forming a semiconductor layer, Stacking and patterning a conductive material to cross the gate line, a data pad connected to the data line, a source electrode connected to the data line and adjacent to the gate electrode, and the source electrode opposite to the gate electrode. Forming a data line including a drain electrode positioned at Depositing a low dielectric constant insulating film to form a protective film, Patterning the passivation layer together with the gate insulating layer to form contact holes exposing the gate pad, the data pad, and the drain electrode, respectively; Stacking and patterning a transparent conductive layer to form an auxiliary gate pad, an auxiliary data pad, and a pixel electrode respectively connected to the gate pad, the data pad, and the drain electrode through the contact hole; Method of manufacturing a thin film transistor substrate comprising a. The method of claim 17, Forming the protective film Method for producing a thin film transistor substrate consisting of spin coating with a coating solution containing a polyorganosilsesquioxane of the formula (1) or (2): [Formula 1] [Formula 2] In formulas (1) and (2), R is hydrogen, a hydroxy group, an alkyl having 1 to 5 carbon atoms, or an aryl group; X is ethylene or propylene and n is 2 to 1,000. The method of claim 17, Forming the protective film A method of manufacturing a thin film transistor substrate in which a pore-forming film is formed by mixing and decomposing a SiO ₂ -based cage compound into a molecule of the polyorganosilsesquioxane of Formula 1 or Formula 2 by bonding or decomposing a porogen. The method of claim 17, The data line and the semiconductor layer may be formed together in a photolithography process using a photoresist pattern having a first portion, a second portion thicker than the first portion, and a third portion thinner than the first thickness. Method of manufacturing a substrate. The method of claim 20, In the photolithography process, the first portion is formed to be positioned between the source electrode and the drain electrode, and the second portion is formed to be positioned above the data line. The method of claim 17, Forming the gate insulating film A first step of depositing a low dielectric constant insulating film and a second step of depositing a silicon nitride film, wherein the first step and the second step is a method of manufacturing a thin film transistor substrate in a vacuum is maintained. A first step of forming a data line including a data line on an insulating substrate, A second step of forming a color filter of red, green, and blue on the substrate; A third step of forming a buffer layer covering the data line and the color filter with a low dielectric constant insulating film, A fourth step of forming a gate wiring including a gate line and a gate electrode on the insulating layer; A fifth step of forming a gate insulating film covering the gate wiring; Forming a ohmic contact layer and a semiconductor layer pattern on the gate insulating layer and forming a first contact hole in the gate insulating layer and the buffer layer to expose a portion of the data line; A seventh step of forming a pixel wiring on the island-shaped ohmic contact layer pattern that is separated from each other and includes a source electrode and a drain electrode formed of the same layer, and a pixel electrode connected to the drain electrode; An eighth step of removing the exposed portion of the ohmic contact layer pattern positioned between the source electrode and the drain electrode to separate the ohmic contact layer pattern on both sides; Method of manufacturing a thin film transistor substrate comprising a. The method of claim 23, The sixth step, Sequentially depositing an amorphous silicon film and an amorphous silicon film doped with impurities on the gate insulating film, Forming a photoresist pattern including a first portion covering a predetermined area on the gate electrode and a second portion covering a remaining portion except for a portion in which the first contact hole is to be formed and thinner than the first portion; Etching the amorphous silicon film, the amorphous silicon film, the gate insulating film, and the buffer layer doped with the impurities below the first and second portions of the photosensitive film as a mask to form the first contact hole; Removing the second portion of the photoresist pattern. Forming the semiconductor layer pattern and the ohmic contact layer pattern by etching the amorphous silicon film and the amorphous silicon film doped with the impurities below the first photoresist pattern as a mask; Removing a first portion of the photoresist pattern Method of manufacturing a thin film transistor substrate comprising a. The method of claim 17, A method of manufacturing a thin film transistor substrate having a dielectric constant of the low dielectric constant insulating film has a value between 2 and 3.