KR100864608B1 - Manufacturing method of thin film transistor substrate for liquid crystal display device - Google Patents

Abstract

A method of manufacturing a thin film transistor substrate for a liquid crystal display device including a metal double layer pattern is disclosed. First, the first metal layer and the second metal layer are laminated on the substrate. Thereafter, the passivation layer is formed on the second metal layer by using nitrogen or oxygen plasma generated by injecting nitrogen or oxygen gas while maintaining a vacuum. A photoresist pattern is formed on the passivation layer, and the passivation layer, the second metal layer, and the first metal layer are etched to form a gate pattern including a gate line, a gate pad, and a gate electrode. After stripping and removing the photoresist pattern, the gate insulating film is laminated. After forming the semiconductor layer and the doped amorphous silicon layer and performing a photolithography process to form the semiconductor layer pattern and the ohmic contact layer pattern, the wiring material is applied and photo-etched to form data lines and source / drain electrodes. After stacking a passivation layer on the data line and the source / drain electrodes, a contact hole is formed in the passivation layer so that a part of the drain electrode is exposed, a transparent conductive material is laminated, and then etched to form a pixel electrode. Defects such as wet etching of the metal double layer, etching of the upper layer generated during the strip process for removing the photoresist pattern after etching, and residue of the lower layer may be improved to form a good pattern.

Description

Method of manufacturing thin film transistor substrate for liquid crystal display device {Method Of Manufacturing Thin Film Transistor For Liquid Crystal Display}

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1;

3 to 6 are cross-sectional views illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention according to a process sequence thereof.

7 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

8 and 9 are cross-sectional views taken along lines VII-VII 'and IX-IX' of FIG. 7, respectively.

10A and 10B to 17A and 17B are cross-sectional views illustrating a process of manufacturing the thin film transistor substrate illustrated in FIGS. 8 and 9, respectively.

18 is a layout view of a thin film transistor substrate according to a third exemplary embodiment of the present invention.

19 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 18 along a cutting line XIX-XIX ′,

20 to 27 are cross-sectional views for describing a manufacturing process of the thin film transistor substrate illustrated in FIG. 19.

The present invention relates to a method for manufacturing a thin film transistor substrate for a liquid crystal display device, and more particularly, to a method of forming a metal double layer pattern capable of reducing defects caused by a wet process such as a wet etching process or a photoresist strip process. The present invention relates to a method for manufacturing a thin film transistor substrate for a liquid crystal display device having improved quality.

In general, a display device is an electro-optical device used to convert an electrical signal into a visual image so that a human can directly recognize information. Among such display devices, a liquid crystal display device is a display device that uses an optical property of a liquid crystal by changing an arrangement of liquid crystal molecules by applying an electric field.

The manufacturing method of the thin film transistor substrate of a liquid crystal display device consists of forming the metal wiring, forming the protective film which covers the wiring, laminating and patterning an ITO film, and forming a transparent electrode.

On the other hand, when the thin film transistor is used in a large display substrate, the gate resistance should be small in order to prevent signal delay or flicker of the image. Metals with low resistance and high conductivity include copper or aluminum. However, these materials are subject to process constraints. In particular, in the case of copper, there is a disadvantage that the adhesion to the substrate or the insulating film is inferior and natural oxidation easily occurs.                         

Recently, metal double membranes have been introduced to simplify the manufacturing process and overcome limitations of various materials. For example, in the case of a gate, many Al / Cr double film structures are adopted, where Al is selected for good contact property with ITO and Cr for good adhesion with a glass substrate.

However, when the metal double layer is etched by a wet etching method or a strip process using a solution to remove the photoresist pattern after etching is completed, the lower portion may be formed due to a difference in electromotive force (standard electromotive force reduction potential) between the upper metal and the lower metal. There is a problem that an etching residue of the metal occurs or corrosion of the upper metal occurs. Otherwise, the problem caused by the material used as the lower layer and the upper layer may change.

Various methods have been applied to solve this problem. First, there is an ashing process using an oxygen plasma. This is a method of forming a passivation on the surface of the upper metal layer by performing oxygen plasma ashing before etching the lower metal. According to this method, the passivation film is formed by performing an oxygen plasma ashing process after part of the wet etching process or after the photoresist strip process. Therefore, when the passivation film is formed, a pollutant such as polymer or impurities contained in the air is included, so that the formed film is not dense and does not sufficiently function as a passivation film. In addition, a separate plasma ashing equipment is required, which is cumbersome and expensive.

Alternatively, there are methods using chemicals for photoresist strips. This is a method of forming a passivation on the surface of the upper metal using the oxidizing strip chemicals when the photoresist strip proceeds after etching the lower metal layer. However, according to this method, since the passivation film is formed after the wet etching process and the photoresist strip process as in the above method, there is a problem that the film is not sufficiently dense and does not function properly as a passivation film.

Meanwhile, in Korean Patent Publication No. 2000-3179, in the method of forming a data line of a liquid crystal display device, a molybdenum metal film and an aluminum metal film are sequentially deposited, a photosensitive film is formed to be etched, and an aluminum oxide film is formed through annealing. Is starting.

According to this method, an oxide film is formed on the metal film to obtain the effect of protecting the upper metal film, but the process is complicated because a separate annealing process has to be performed.

An object of the present invention is to meet the above-mentioned recent demands, and in particular, by forming a dense passivation oxide film by an easy method without containing a source of contamination after the formation of the upper metal film, it is possible to prevent the residue or corrosion of the metal film after etching. It is to provide a method of forming a metal double layer pattern.

In the present invention to achieve the above object

Depositing a first metal layer and a second metal layer on the substrate;

Forming a passivation layer on top of the second metal layer using nitrogen or oxygen plasma generated by injecting nitrogen or oxygen gas while maintaining a vacuum;

Forming a photoresist pattern on the passivation film;

Etching the passivation layer, the second metal layer, and the first metal layer to form a gate pattern including a gate line, a gate pad, and a gate electrode;

Stripping and removing the photoresist pattern;

Stacking a gate insulating layer on the gate pattern;

Forming a semiconductor layer and a doped amorphous silicon layer on the gate insulating layer, and then performing a photolithography process to form a semiconductor layer pattern and an ohmic contact layer pattern;

Applying a wiring material and then etching the photo to form a data line and a source / drain electrode;

Forming a contact hole in the passivation layer so that a portion of the drain electrode is exposed after stacking the passivation layer on the data line and the source / drain electrode;

Stacking an ITO film which is a transparent conductive material; And

A method of manufacturing a thin film transistor substrate for a liquid crystal display device, the method including forming a pixel electrode by etching the ITO film.

In particular, the first metal layer is formed of at least one selected from the group consisting of chromium, aluminum, copper, molybdenum and tungsten, and the second metal layer is preferably formed from at least one selected from the group consisting of aluminum, molybdenum and copper, and more preferably. Preferably, the first metal layer is formed of chromium, and the second metal layer is formed of aluminum.

In addition, the passivation film is preferably formed as an oxide film or a nitride film in a thickness of about 100 ± 50 kPa, the plasma treatment conditions using nitrogen or oxygen gas has a power range of 0.3 ~ 1.5kw / cm ² , the treatment time is 5 ~ The passivation film can be easily formed in the 25 second range.

The object of the invention described above is also

Depositing a first metal layer and a second metal layer on the substrate;

Forming a passivation layer on top of the second metal layer using nitrogen or oxygen plasma generated by injecting nitrogen or oxygen gas while maintaining a vacuum;

Forming a photoresist pattern on the passivation film;

Etching the passivation layer, the second metal layer, and the first metal layer to form a gate pattern including a gate line, a gate pad, and a gate electrode;

Stripping and removing the photoresist pattern;

Stacking a gate insulating film on the gate pattern;

Forming a semiconductor layer, an intermediate layer, and a conductor layer on the gate insulating film;

Forming a photoresist film, and then exposing and developing the photoresist film to form a thickness of a channel portion located between a source electrode and a drain electrode to be formed later than a thickness of a data wiring portion to be formed later, and removing the remaining portion of the photoresist pattern. ;                     

The conductor layer, the intermediate layer, and the semiconductor layer are etched using the obtained photoresist pattern, leaving the semiconductor layer in the channel portion, leaving all of the lower layer in the data wiring portion, and all of the conductor layer, the intermediate layer, and the semiconductor layer in the remaining portions. Removing;

Forming a contact hole in the passivation layer so that a part of the drain electrode is exposed after laminating a passivation layer on the obtained data line and source / drain electrodes;

Stacking an ITO film which is a transparent conductive material; And

A method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising etching the ITO film to form a pixel electrode.

The object of the invention described above is also

Forming a data line including data lines on the insulating substrate;

Forming a color filter of red, green, and blue on the substrate;

Depositing a buffer material to form a buffer layer covering the data line and the color filter;

Stacking a first metal layer and a second metal layer on the buffer layer;

Forming a passivation layer on top of the second metal layer using nitrogen or oxygen plasma generated by injecting nitrogen or oxygen gas while maintaining a vacuum;

Forming a photoresist pattern on the passivation film;

Etching the passivation layer, the second metal layer, and the first metal layer to form a gate pattern including a gate line, a gate pad, and a gate electrode;                     

Stripping and removing the photoresist pattern;

Forming a gate insulating film covering the gate wiring;

Forming an island-like ohmic contact layer and a semiconductor layer pattern on the gate insulating layer, and simultaneously forming a first contact hole in the gate insulating layer and the buffer layer to expose a portion of the data line;

Forming a pixel wiring on the island-shaped resistive contact layer pattern, the pixel wiring including a source electrode and a drain electrode formed of the same layer and a pixel electrode connected to the drain electrode; And

And removing the exposed portion of the ohmic contact layer pattern disposed between the source electrode and the drain electrode to separate the ohmic contact layer pattern on both sides. Is also achieved.

Hereinafter, the present invention will be described in more detail.

In the present invention, a technique that is particularly preferably applied when there is a wet etching process for forming a metal double layer pattern or a process for stripping a photoresist pattern after the formation of the metal double layer pattern is provided. After the formation of the film, oxygen or nitrogen gas is injected while maintaining a vacuum, and plasma is generated to form a dense passivation film made of an oxide film or a nitride film on the upper film, thereby preventing etching residues of the lower film, corrosion of the upper film, or the like. It is to be done.                     

As described above, the method of the present invention can be applied without exception in the case of forming the metal double layer pattern, and in particular, it can be easily applied in the formation of the metal double layer pattern for forming the gate, the source, the drain, and the like. .

Hereinafter, a thin film transistor substrate to which a structure of a low resistance wiring according to an exemplary embodiment of the present invention is applied and a method of manufacturing the same may be easily performed by those skilled in the art. Please explain in detail. In the following embodiment, a case where the gate is formed of a metal double layer will be described as an example.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II of the thin film transistor substrate shown in FIG.

The first gate wiring layers 221, 241, and 261 made of chromium, aluminum, copper, molybdenum, tungsten, and the like and the second gate wiring layers 222, 242, and 262 made of aluminum, molybdenum, copper, and the like are disposed on the insulating substrate 10. A double layer gate wiring is formed. Passive films 223, 243, and 263 formed of an oxide film or a nitride film are formed on the second gate wiring layers 222, 242, and 262. The gate wire is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24 in an island shape, and silicide or n-type impurities are doped with high concentration on the semiconductor layer 40. Resistive contact layers 54 and 56 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.

On the ohmic contacts 54 and 56 and the gate insulating film 30, data wiring layers 62, 65, 66 and 68 made of a molybdenum film or a molybdenum-tungsten alloy film are formed. The data lines 62, 65, 66, and 68 are formed in the vertical direction and intersect with the gate line 22 to define the pixel, the branch of the data line 62, the data line 62, and the resistive contact layer 54. It is connected to one end of the source electrode 65 and the data line 62 extending to the upper portion, and separated from the data pad 68 and the source electrode 65 to which an image signal from the outside is applied, and the gate electrode 26. And a drain electrode 66 formed over the ohmic contact layer 56 opposite the source electrode 65. The passivation layer 70 is formed on the data wires 62, 65, 66, and 68 and the semiconductor layer 40 not covered by the data lines 62.

In the passivation layer 70, contact holes 76 and 78 are formed to expose the drain electrode 66 and the data pad 68, respectively. The contact hole 74 exposing the gate pad 24 together with the gate insulating layer 30 is formed. Is formed. At this time, the contact holes (74, 78) exposing the pads (24, 68) can be formed in a variety of angles or circular shape, the area is not more than 2mm × 60㎛, 0.5mm × 15㎛ or more desirable.

On the passivation layer 70, a pixel electrode 82, which is electrically connected to the drain electrode 66 and positioned in the pixel, is formed through the contact hole 76. In addition, the auxiliary gate pad 86 and the auxiliary data pad 88, which are connected to the gate pad 24 and the data pad 68, respectively, are formed on the passivation layer 70 through the contact holes 74 and 78. Here, the pixel electrode 82, the auxiliary gates, and the data pads 86 and 88 are made of indium tin oxide (ITO).

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate lines 22, 24, and 26. It is also possible to add a storage capacitor wiring.

The pixel electrode 82 is also formed to overlap the data line 62 to maximize the aperture ratio. As such, even when the pixel electrode 82 is overlapped with the data line 62 in order to maximize the aperture ratio, the dielectric constant of the passivation layer 70 is low, so that the parasitic capacitance formed therebetween is small.

Next, a method of manufacturing the thin film transistor substrate for a liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3 to 7.

First, as shown in FIG. 3, the first gate wiring layers 221, 241, and 261 are stacked by depositing a metal having excellent physicochemical properties such as chromium, aluminum, copper, molybdenum, tungsten, and the like on the substrate 10. The second gate wiring layers 222, 242, and 262 are laminated by depositing a metal having a low resistance and excellent contact characteristics with ITO such as aluminum, molybdenum, copper, and the like. Preferred metal double film pairs include Cr / Al, Mo / Al, Mo / Cu, Cu / Mo, Cu / W, and the like as the first gate wiring layer / second gate wiring layer, and most preferably a Cr / Al double film. It can be applied with a thickness of about 500Å / 2500Å.

The deposition of the metal is performed in a vacuum chamber. After the upper metal deposition is completed for the formation of the second gate wiring layer, oxygen or nitrogen is injected in-situ in a vacuum state, and then, the oxygen or nitrogen plasma is injected. A passivation film is formed. Oxygen plasma will form an oxide film, and nitrogen plasma will form a nitride film.

As a result of repeated experiments by the present inventors, the level of significance by pressure was almost no difference, but the level of significance by power and treatment time was found to be quite large. Plasma treatment conditions for forming the passivation film may vary depending on the size of the glass to be treated. Preferably, the range is about 0.3 to 1.5 kw / cm ² , and the lower the power, the more preferable it was confirmed. The treatment time was found to be in the range of about 5 to 25 seconds. Since the power and the processing time are complementary to each other and are optimized values in consideration of mutual ranges, the above conditions may vary slightly as necessary.

Argon gas is preferably used as the flow gas used for the injection of the oxygen gas or the nitrogen gas injected for the plasma generation, and the ratio of the preferred injection amount is 5: 1 to 5 in the ratio of argon gas to oxygen gas or nitrogen gas. It is preferable to make it into the range of. Plasma treatment in accordance with the above-described preferred conditions can be seen that the passivation film is formed to a thickness of about 100 ± 50Å.

 Subsequently, the gate lines extending in the horizontal direction including the gate line 22, the gate electrode 26, and the gate pad 24 are formed by wet patterning using a photoresist pattern. The double layer of metal exhibits different etching characteristics by chemicals including water used in wet etching or photoresist stripping processes. As in the present invention, the double layer of metal is formed into a single layer of the lower layer by forming a passivation layer on the surface of the upper metal layer. You can get the same effect as it exists. In particular, when the passivation film is formed in the vacuum state after the formation of the upper metal layer as in the present invention, since there is no room for polymer or impurities to flow in the surroundings, it is obtained as a pure film containing no contaminant and the film quality is also dense. In this way, the passivation film sufficiently functions as a passivation film.

Next, as shown in FIG. 4, a three-layer film of a gate insulating film 30 made of silicon nitride, a semiconductor layer 40 made of amorphous silicon, and a doped amorphous silicon layer is successively laminated, and the semiconductor layer 40 and doped The amorphous silicon layer is etched to form island-like semiconductor layers 40 and ohmic contacts 55 and 56 on the gate insulating layer 30 on the gate electrode 24.

Next, as shown in FIG. 5, the data line 62 and the data intersecting the gate line 22 are laminated by depositing molybdenum or molybdenum-tungsten alloy and stacking the data wiring layers 65, 66, and 68. The source electrode 65 and the data line 62 connected to the line 62 and extending to the upper portion of the gate electrode 26 are separated from the data pad 68 and the source electrode 64 connected to one end thereof. A data line including a drain electrode 66 facing the source electrode 65 is formed around the electrode 26.

The data pattern may be formed of a single film of molybdenum or molybdenum alloy or a double film in combination thereof. The above-described method of the present invention can also be applied when the data pattern is formed into a double layer. That is, after the upper metal film is deposited, oxygen or nitrogen gas is injected while maintaining a vacuum to form an oxide film or a nitride film as a passivation film as a passivation film on the upper metal film, thereby improving subsequent etching and photoresist strip properties. It will be possible.

Subsequently, the doped amorphous silicon layer pattern not covered by the data lines 62, 65, 66, and 68 is etched and separated on both sides of the gate electrode 26, while the doped amorphous silicon layers 55 and 56 are formed on both sides. The semiconductor layer pattern 40 between the layers is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma. Next, a protective film as shown in FIG. 6 is formed.

Subsequently, the passivation layer is patterned together with the gate insulating layer 30 by a photolithography process to form contact holes 74, 76, and 78 that expose the gate pad 24, the drain electrode 66, and the data pad 68. Here, the contact holes 74, 76, 78 may be formed in an angled shape or a circular shape, the area of the contact holes 74, 78 exposing the pads 24, 68 is greater than 2mm x 60㎛. It is preferable that it is 0.5 mm x 15 micrometers or more.

Next, as shown in FIGS. 1 and 2, second and third contacts with the pixel electrode 82 connected to the drain electrode 66 through the first contact hole 76 by depositing and photolithography the ITO film. The auxiliary gate pad 86 and the auxiliary data pad 88 are formed to be connected to the gate pad 24 and the data pad 68 through the holes 74 and 78, respectively. It is preferable to use nitrogen as the gas used in the pre-heating process before laminating ITO. This is to prevent the metal oxide film from being formed on the upper portions of the metal films 24, 66, and 68 exposed through the contact holes 74, 76, and 78.

When the metal double layer pattern is formed in accordance with the method of the present invention, the passivation layer formed on the upper metal layer may cause the upper layer to be partially etched or the lower layer, which is a problem caused by performing the wet etching process or the strip process after etching. This will solve the problem of residue. In particular, it was confirmed that the problem that the upper layer is corroded by the composition containing water and part of the lower layer is almost completely eliminated.

Although the method of the present invention as described above can be applied to a manufacturing method using five masks as in the above-described embodiment, the same method can be applied to the manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. Can be. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 7 to 9.                     

FIG. 7 is a layout view of a thin film transistor substrate for a liquid crystal display device according to a second exemplary embodiment of the present invention, and FIGS. 8 and 9 are lines VIII-VIII 'and IX-IX', respectively, of the thin film transistor substrate shown in FIG. The cross section for

First, the first gate wiring layers 221, 241 and 261 made of chromium and the like and the second gate wiring layers 222, 242 and 262 made of aluminum and the like on the insulating substrate 10 and the upper portion thereof are the same as in the first embodiment. Gate wirings formed of the passivation films 223, 243, and 263 are formed. The gate wiring includes a gate line 22, a gate pad 24, and a gate electrode 26.

The storage electrode line 28 is formed on the substrate 10 in parallel with the gate line 22. The storage electrode line 28 also includes a double layer of the first gate wiring layer 281 and the second gate wiring layer 282 and a passivation film 283 formed thereon. The storage electrode line 28 overlaps the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor which improves charge storage capability of the pixel. The pixel electrode 82 and the gate line to be described later will be described. It may not be formed if the holding capacity generated by the overlap of (22) is sufficient. The same voltage as that of the common electrode of the upper substrate is usually applied to the storage electrode line 28.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and the storage electrode line 28 to cover the gate wirings 22, 24, 26, and 28.

On the gate insulating layer 30, semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed, and on the semiconductor patterns 42 and 48, n-type impurities such as phosphorus (P) have a high concentration. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56, and 58, data wiring layers 62, 64, 65, 66, and 68 formed of a molybdenum or molybdenum alloy film or a metal double layer are formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 68 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And data line portions 62, 68, and 65 made up of a source electrode 65, and are separated from the data line portions 62, 68, and 65, and formed on the gate electrode 26 or the channel portion C of the thin film transistor. On the other hand, the drain electrode 66 of the thin film transistor positioned on the opposite side of the source electrode 65 and the conductor pattern 64 for the storage capacitor located on the storage electrode line 28 are also included. When the storage electrode line 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor. The passivation layer 70 is formed on the data lines 62, 64, 65, 66, and 68.

The protective film 70 has contact holes 76, 78, and 72 that expose the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor, and also the gate along with the gate insulating film 30. It has a contact hole 74 which exposes the pad 24.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material of ITO, and is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor pattern 64 through the contact hole 72 to transmit an image signal to the conductor pattern 64. On the other hand, an auxiliary gate pad 86 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively, are formed. 68) and to protect the pads and the adhesion of the external circuit device, and is not essential, their application is optional.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 7 to 9 using four masks will be described in detail with reference to FIGS. 8 to 10 and 10A to 17B. .

First, as shown in FIGS. 10A and 10B, the first gate wiring layers 221, 241, 261, and 281 are laminated by depositing chromium or the like having excellent physicochemical properties as in the first embodiment, and having low resistance and ITO. The second gate wiring layers 222, 242, 262, and 282 are stacked by depositing aluminum having excellent contact properties with the film, and then using a nitrogen or oxygen plasma while maintaining a vacuum, and the passivation films 223, 243, 263, and 283. ) To form. The photoresist pattern is etched with a mask to form a metal double layer pattern, and then the photoresist is stripped and removed, and the gate wiring and the storage electrode line including the gate line 22, the gate pad 24, and the gate electrode 26 are formed. 28).

Next, as shown in FIGS. 11A and 11B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kPa and 500 kPa to 2,000 using chemical vapor deposition. Å, 300 600 to 600 연속 of continuous deposition, and then MoW is deposited by a method such as sputtering to form a conductor layer 60. In this case, the conductor layer may be formed of a double layer of metal, in which case the method of the present invention is applied to form a passivation layer under vacuum on the upper metal layer. Next, the photosensitive film 110 is applied on the metal film to a thickness of 1 μm to 2 μm.

Thereafter, the photosensitive film 110 is irradiated with light through a mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 12A and 12B. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure, and in the case of using a translucent film, the transmittance is different in order to control the transmittance when fabricating a mask. A thin film having a thickness or a thin film may be used.                     

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 13A and 13B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

In this way, as shown in FIGS. 13A and 13B, only the conductor layers of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 68 for the storage capacitor, are provided. All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 67 and 64 have the same shape as the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 14A and 14B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 thereunder are simultaneously removed by the dry etching method together with the first portion 114 of the photosensitive film. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions where the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 14A and 14B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductor patterns 64, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as illustrated in FIGS. 15A and 15B, the source / drain conductor pattern 67 of the channel part C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under the condition that the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, and it is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in C). In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include a mixture gas of CF ₄ and HCl or a mixture gas of CF ₄ and O ₂ , and CF ₄ and O ₂ . The semiconductor pattern 42 may be left at a uniform thickness. In this case, as shown in FIG. 15B, a part of the semiconductor pattern 42 may be removed to reduce the thickness, and the second part 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching should be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used, or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter. Next, as shown in FIGS. 16A and 16B, a protective film 70 is formed.

17A and 17B, the protective film 70 is etched together with the gate insulating film 30 to form a drain electrode 66, a gate pad 24, a data pad 68, and a conductor for a storage capacitor. Contact holes 76, 74, 78, and 72 are formed to expose the pattern 64, respectively. At this time, the area of the contact holes 74 and 78 exposing the pads 24 and 68 does not exceed 2 mm x 60 m, and is preferably 0.5 mm x 15 m or more.

Finally, as shown in FIGS. 8 to 10, a pixel electrode 82 connected to the drain electrode 66 and the conductive pattern conductor 64 for the storage capacitor is deposited by depositing and photolithography an ITO layer having a thickness of 400 kV to 500 kV. ), An auxiliary gate pad 86 connected to the gate pad 24, and an auxiliary data pad 88 connected to the data pad 68 are formed.

On the other hand, it is preferable to use nitrogen as the gas used in the pre-heating process before laminating the ITO, which is the metal film 24, 64, which is exposed through the contact holes 72, 74, 76, 78, This is to prevent the metal oxide film from being formed on the upper portions 66 and 68.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48 may be formed using a single mask, and the manufacturing process may be simplified by separating the source electrode 65 and the drain electrode 66 in this process.

The method according to the present invention can be easily applied to an array on color filter (AOC) structure in which a thin film transistor array is formed on a color filter.

18 is a layout view of a thin film transistor substrate according to a third exemplary embodiment of the present invention, and FIG. 19 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 18 along a cutting line XIX-XIX ′. 19 illustrates a lower substrate as a thin film transistor substrate and an upper substrate facing the same.

First, data wirings 120, 121, and 124 made of molybdenum or molybdenum-tungsten alloy are formed on the lower substrate. The data wires 120, 121, and 124 are connected to the data lines 120 and the data lines 120 extending in the vertical direction, and receive data signals from the outside and transmit them to the data lines 120. And a light blocking unit 121 for blocking light incident to the semiconductor layer 170 of the thin film transistor formed later from the lower portion of the substrate 100 by the branch of the data line 120. Here, the light blocking unit 121 also has a function of a black matrix that blocks light leakage, and may be formed by disconnecting the data line 120 and disconnected wiring.

Here, the data wirings 120, 121, and 124 are formed of a molybdenum-tungsten alloy layer having a low resistance, considering that the pixel wirings 410, 411, 412 and the auxiliary pads 413, 414 formed thereafter are ITO. It is preferable to manufacture, or to manufacture with a metal double film.                     

On the lower insulating substrate 100, color filters 131, 132, and 133 of red (R), green (G), and blue (B), whose edges overlap the edges of the data lines 120 and 121, are respectively formed. Formed. The color filters 131, 132, and 133 may be formed to cover all of the data lines 120.

The buffer layer 140 is formed on the data lines 120, 121, 124, and the color filters 131, 132, and 133. Here, the buffer layer 140 is a layer for preventing outgassing from the color filters 131, 132, and 133 and preventing the color filter itself from being damaged by heat and plasma energy in a subsequent process. In addition, since the buffer layer 140 separates the lowermost data lines 120, 121, and 124 from the thin film transistor array, the lower the dielectric constant and the thicker the thickness, the more advantageous it is to reduce the parasitic capacitance therebetween.

On the buffer layer 140, a gate line having a structure including a lower layer 501 made of a material such as chromium and an upper layer 502 made of a material such as aluminum and a passivation layer 503 is formed.

The gate line extends in the horizontal direction and is connected to the gate line 150 and the gate line 150 defining the unit pixel by crossing the data line 120 to receive the scan signal from the outside to the gate line 150. And a gate electrode 151 of the thin film transistor which is a part of the gate pad 152 and the gate line 150 to transfer.

Here, the gate line 150 overlaps with the pixel electrode 410 to be described later to form a storage capacitor that improves the charge storage capability of the pixel, and the sustain is generated by overlapping the pixel electrode 410 and the gate line 150 to be described later. If the capacitance is not sufficient, a common electrode for the storage capacitance may be formed.

As described above, when the gate wiring is formed in two or more layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials. Bilayers are an example.

The low temperature deposition gate insulating layer 160 is formed on the gate lines 150, 151, and 152 and the buffer layer 140. In this case, the low temperature deposition gate insulating film 160 may be formed of an organic insulating film, a low temperature amorphous silicon oxide film, a low temperature amorphous silicon nitride film, or the like. In the thin film transistor structure according to the present embodiment, since the color filter is formed on the lower substrate, the gate insulating film may be deposited at a low temperature, not a normal insulating film that is deposited at a high temperature. For example, the gate insulating film may be deposited at a low temperature of 250 ° C. or lower. A vapor deposition insulating film is used.

The double layer semiconductor layer 171 is formed in an island shape on the gate insulating layer 160 of the gate electrode 151. In the double layer semiconductor layer 171, the lower semiconductor layer 701 is made of amorphous silicon having a high band gap, and the upper semiconductor layer 702 is made of ordinary amorphous silicon having a lower band gap than the lower semiconductor 701. . For example, the band gap of the lower semiconductor layer 701 may be 1.9 to 2.1 eV, and the band gap of the upper semiconductor layer 702 may be 1.7 to 1.8 eV. Here, the lower semiconductor layer 701 is formed to a thickness of 50 to 200 GPa, and the upper semiconductor layer 702 is formed to a thickness of 1000 to 2000 GPa.

As such, a band offset corresponding to the difference between the band gaps of the two layers is formed between the upper semiconductor layer 702 and the lower semiconductor layer 701 having different band gaps. At this time, when the TFT is turned on, a channel is formed in the band offset region located between the two semiconductor layers 701 and 702. Since this band offset region has basically the same atomic structure, there are few defects and favorable TFT characteristics can be expected. The semiconductor layer 171 may be formed as a single layer.

On the semiconductor layer 171, ohmic contact layers 182 and 183 including amorphous silicon or microcrystalline silicon or metal silicide doped with a high concentration of n-type impurities such as phosphorus (P) are mutually formed. It is formed separately.

On the ohmic contacts 182 and 183, pixel wirings 410, 411 and 412 including source and drain electrodes 412 and 411 and pixel electrodes 410 made of ITO are formed. The source electrode 412 is connected to the data line 120 through the contact hole 161 formed in the gate insulating layer 160 and the buffer layer 140. The drain electrode 411 is connected to the pixel electrode 410 and receives an image signal from the thin film transistor and transmits the image signal to the pixel electrode 410. The pixel wirings 410, 411 and 412 are made of a transparent conductive material of ITO.

In addition, the auxiliary gate pad 413 and the auxiliary data pad connected to the gate pad 152 and the data pad 124 through the contact holes 162 and 164 in the same layer as the pixel wirings 410, 411, and 412, respectively. 414 is formed. Here, the auxiliary gate pad 413 is in direct contact with the molybdenum-tungsten alloy film, which is the upper film 502 of the gate pad 152, and the auxiliary data pad 414 is also in the upper film 202 of the data pad 124. It is in direct contact with the phosphorus molybdenum-tungsten alloy film. The pixel electrode 410 also overlaps the neighboring gate line 150 and the data line 120 to increase the aperture ratio, but may not overlap.

A passivation layer 190 is formed on the source and drain electrodes 412 and 411 to protect the thin film transistor, and a photosensitive colored organic layer 430 having a dark color having excellent light absorption is formed thereon. have. In this case, the colored organic layer 430 serves to block light incident to the semiconductor layer 171 of the thin film transistor, and adjusts the height of the colored organic layer 430 to face the lower insulating substrate 100. It is used as a spacer to maintain the gap between the insulating substrate 200. Here, the passivation layer 190 and the organic layer 430 may be formed along the gate line 150 and the data line 120, and the organic layer 430 blocks light leaking around the gate line and the data line. It can have a role.

Meanwhile, the upper substrate 200 is made of ITO or IZO, and the common electrode 210 for generating an electric field together with the pixel electrode 410 is formed on the entire surface.

Next, a method of manufacturing the thin film transistor substrate according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 20 to 27 and FIGS. 18 and 19.

First, as shown in FIG. 20, a conductive material having excellent contact properties with ITO, such as MoW, is deposited by a method such as sputtering, and dry or wet etched by a photolithography process using a mask, on the lower insulating substrate 100. Data lines 120, 121, and 124 including the data line 120, the data pad 124, and the light blocking unit 121 are formed.                     

Next, as shown in FIG. 21, a photosensitive material including pigments of red (R), green (G), and blue (B) is sequentially applied, and patterned by a photo process using a mask to form red (R) and green (G). ), And the color filters 131, 132, and 133 of blue (B) are sequentially formed. At this time, the red (R), green (G), and blue (B) color filters 131, 132, and 133 are formed using three masks, but they are formed by moving one mask to reduce manufacturing costs. It may be. In addition, using a laser transfer method or a print method can be formed without using a mask, thereby minimizing the manufacturing cost. At this time, as shown in the figure. The edges of the color filters 131, 132, and 133 of red (R), green (G), and blue (B) may be formed to overlap the data line 120. Subsequently, as shown in FIG. 22, a buffer layer 140 is formed on the insulating substrate 100.

Subsequently, a conductive material such as chromium and aluminum is continuously deposited by a method such as sputtering and oxygen or nitrogen gas is injected while maintaining a vacuum to form a passivation film by plasma. Subsequently, the photolithography process is patterned using a mask, and the photoresist pattern is removed by a strip process, thereby forming a gate line including a first metal layer 501, a second metal layer 502, and a passivation layer 503 on the buffer layer 140. Gate wirings 150, 151, and 152 including 150, gate electrodes 151, and gate pads 152 are formed.

Next, as shown in FIG. 23, the low-temperature deposition gate insulating layer 160, the first amorphous silicon film 701, and the second amorphous silicon film 702 on the gate wirings 150, 151, and 152 and the organic insulating film 140. And an amorphous silicon film 180 doped with impurities.

The low temperature deposition gate insulating layer 160 may be formed using an organic insulating layer, a low temperature amorphous silicon oxide film, a low temperature amorphous silicon nitride film, or the like, which may be deposited even at a deposition temperature of 250 ° C. or lower.

The first amorphous silicon film 701 is formed of an amorphous silicon film having a high band gap, for example, a band gap of 1.9 to 2.1 eV, and the second amorphous silicon film 702 has a band gap of the first amorphous silicon film. For example, it is formed of a conventional amorphous silicon film having a band gap of less than 701, for example, 1.7 to 1.8 eV. In this case, the first amorphous silicon film 701 may be deposited by CVD by adding an appropriate amount of CH ₄ , C ₂ H ₂ , or C ₂ H ₆ to SiH _{4, which} is a raw material gas of the amorphous silicon film. . For example, when SiH ₄ : CH ₄ is added to a CVD apparatus at a ratio of 1: 9, and the deposition process is performed, an amorphous silicon film containing about 50% of C and having a band gap of 2.0 to 2.3 eV is deposited. can do. As such, the band gap of the amorphous silicon layer is affected by the deposition process conditions, and the band gap can be easily adjusted in the range of 1.7 to 2.5 eV, depending on the amount of carbon compound added.

In this case, the low temperature deposition gate insulating layer 160, the first amorphous silicon film 701, the second amorphous silicon film 702, and the amorphous silicon film 180 doped with impurities are continuous without breaking the vacuum in the same CVD apparatus. Can be deposited.

Next, as shown in FIG. 24, the first amorphous silicon film 701, the second amorphous silicon film 702, and the amorphous silicon film 180 doped with impurities are patterned by a photolithography process using a mask to form an island shape. Forming the semiconductor layer 171 and the ohmic contact layer 181, and simultaneously forming the data line 120, the gate pad 152, and the data pad 124 on the low temperature deposition gate insulating layer 160 and the organic insulating layer 140. Respective contact holes 161, 162, and 164 are formed, respectively.

In this case, except for the upper portion of the gate electrode 151, all of the first and second amorphous silicon layers 701 and 702 and the amorphous silicon layer 180 doped with impurities should be removed, and the upper portion of the gate pad 152 may be removed. Along with the first and second amorphous silicon films 701 and 702 and the amorphous silicon film 180 doped with impurities, the gate insulating layer 160 should be removed, and the upper portion of the data line 120 and the data pad 124 may be removed. The organic insulating layer 140 should be removed along with the first and second amorphous silicon layers 701 and 702, the amorphous silicon layer 180 doped with impurities, and the low temperature deposition gate insulating layer 160.

In order to form this in a photolithography process using one mask, a photoresist pattern having a different thickness is used as an etching mask. This will be described with reference to FIGS. 25 and 26 together.

First, as shown in FIG. 25, after the photoresist film is coated on the impurity doped amorphous silicon film 180 to a thickness of 1 μm to 2 μm, the photoresist film is irradiated with light through a photolithography process. The photoresist patterns 312 and 314 are formed.

In this case, the first portion 312 positioned above the gate electrode 151 among the photoresist patterns 312 and 314 is formed to have a thickness greater than that of the remaining second portions 314, and the data line 120 and the data pad are formed. The photoresist may not exist on the portion 124 and the gate pad 152. It is preferable to make the thickness of the 2nd part 314 into 1/2 or less of the thickness of the 1st part 312, for example, it is good that it is 4,000 Pa or less.

As described above, there may be various ways of varying the thickness of the photosensitive film according to the position. Here, the case of using the positive photosensitive film will be described.

When the light is irradiated to the photosensitive film through a mask 1000 that can control the amount of light by forming a pattern smaller than the resolution of the exposure machine, for example, a slit or lattice pattern in the B region or a semi-transparent film, Depending on the amount or intensity of light irradiated, the degree of decomposition of the polymers is different. At this time, if the exposure is stopped at a time when the polymers of the C region completely exposed to light are completely decomposed, the amount of light passing through the B region where the slit or translucent film is formed is smaller than that of the portion completely exposed to the light. Part of the photoresist in the region is decomposed and the rest remains undecomposed. The longer exposure time decomposes all the molecules, so it should be avoided.

When the photoresist is developed, the first portion 312 in which the molecules are not decomposed remains almost intact, and the second portion 314 which is irradiated with less light remains in a thinner thickness than the first portion 312, and is completely exposed to light. The photosensitive film is almost removed at the portion corresponding to the exposed C region. Through this method, photoresist patterns having different thicknesses are formed according to positions.

Next, as shown in FIG. 26, the amorphous silicon film 180, the second amorphous silicon film 702, and the first amorphous silicon film doped with impurities using the photoresist patterns 312 and 314 as an etching mask are used. 702 and the low temperature deposition gate insulating layer 160 are dry etched to complete the contact hole 162 exposing the gate pad 152, and expose the buffer layer 140 in the C region. Subsequently, dry etching the buffer layer 140 in the C region using the photoresist patterns 312 and 314 as an etching mask to complete the contact holes 161 and 164 exposing the data line 120 and the data pad 124. .

Subsequently, the operation of completely removing the second portion 314 of the photoresist film is performed. In this case, an ashing process using oxygen may be added to completely remove the photoresist residue of the second portion 314.

In this way, the second portion 314 of the photoresist pattern is removed, and the amorphous silicon film 180 doped with impurities is exposed, and the first portion 312 of the photoresist pattern is formed on the second portion 312 of the photoresist pattern. It remains reduced by thickness.

Next, the amorphous silicon film 180 doped with impurities and the first and second amorphous silicon films 701 and 702 below are etched and removed using the first portion 312 of the remaining photoresist pattern as an etching mask. As a result, an island-like semiconductor layer 171 and an ohmic contact layer 181 are left on the low temperature deposition gate insulating layer 160 on the gate electrode 151.

Finally, the remaining first portion 312 of the photoresist film is removed. Here, an ashing process using oxygen may be added to completely remove the photoresist residue of the first portion 312.

Next, as shown in FIG. 27, a pixel electrode 410, a source electrode 412, a drain electrode 411, an auxiliary gate pad 413 and the ITO layer are deposited and patterned by a photolithography process using a mask. An auxiliary data pad 414 is formed.

Subsequently, the resistive contact layer 181 is etched between the source electrode 412 and the drain electrode 411 as an etching mask to form a resistive contact layer pattern separated into two parts 182 and 183. The semiconductor layer 171 is exposed between the source electrode 412 and the drain electrode 411.

Finally, as shown in FIGS. 18 and 19, an insulating material such as silicon nitride or silicon oxide and an insulating material such as a photosensitive organic material including black pigment are sequentially stacked on the lower insulating substrate 100, and a mask is applied. The exposure process is performed using the photolithography process to form the colored organic layer 430, and the protective layer 190 is formed by etching the insulating material under the substrate using the colored organic layer 430 as an etching mask. In this case, the colored organic layer 430 may block light incident to the thin film transistor, and may be formed on the gate line or the data line to provide a function of blocking light leaking around the wire. In addition, as in the embodiment of the present invention, the height of the organic layer 430 may be adjusted to be used as a spacer.

Meanwhile, the common electrode 210 is formed by stacking a transparent conductive material of ITO or IZO on the upper insulating substrate 200.

As described above, when the metal double layer pattern is formed in accordance with the method of the present invention, since the passivation layer formed on the upper metal layer has a pure structure and is formed in a dense structure, the double layer pattern can sufficiently serve as a passivation layer. The problem caused by wet etching the film or stripping the photoresist pattern after the formation of the double layer pattern can be improved.

That is, problems such as etching residue of the lower layer, corrosion of the upper layer, and the like caused by the difference in electromotive force between the upper layer and the lower layer can be solved, thereby forming a metal double layer pattern having good quality.

Since the method of the present invention can be performed by injecting nitrogen gas or oxygen gas in a vacuum state after performing the metal deposition process for forming the upper metal film, the process is not required without any separate equipment. Since this is easy, it can be said that the application is very easy.

Although the above has been described with reference to the preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated.

Claims (21)

Depositing a first metal layer and a second metal layer on the substrate; Forming a passivation layer on top of the second metal layer using nitrogen or oxygen plasma generated by injecting nitrogen or oxygen gas while maintaining a vacuum; Forming a photoresist pattern on the passivation film; Etching the passivation layer, the second metal layer, and the first metal layer to form a gate pattern including a gate line, a gate pad, and a gate electrode; Stripping and removing the photoresist pattern; Stacking a gate insulating layer on the gate pattern; Forming a semiconductor layer and a doped amorphous silicon layer on the gate insulating layer, and then performing a photolithography process to form a semiconductor layer pattern and an ohmic contact layer pattern; Applying a wiring material and then etching the photo to form a data line and a source / drain electrode; Forming a contact hole in the passivation layer so that a portion of the drain electrode is exposed after stacking the passivation layer on the data line and the source / drain electrode; Stacking an ITO film which is a transparent conductive material; And Forming a pixel electrode by etching the ITO film; and manufacturing a thin film transistor substrate for a liquid crystal display device. The method of claim 1, wherein the first metal layer is formed of at least one selected from the group consisting of chromium, aluminum, copper, molybdenum, and tungsten, and the second metal layer is formed from at least one selected from the group consisting of aluminum, molybdenum, and copper. The manufacturing method of the thin film transistor substrate for liquid crystal display devices characterized by the above-mentioned. The method of claim 2, wherein the first metal layer is formed of chromium, and the second metal layer is formed of aluminum. The method of claim 1, wherein the passivation layer is an oxide film or a nitride film having a thickness in a range of 100 ± 50 μs. The plasma processing conditions of claim 1, wherein the plasma treatment conditions using nitrogen or oxygen gas have a power in a range of 0.3 to 1.5 kw / cm ² and a processing time in a range of 5 to 25 seconds. Manufacturing method. The method of claim 1, wherein etching the passivation layer, the second metal layer, and the first metal layer is performed by a wet etching method. The method of claim 1, wherein forming the data line and the source / drain electrodes by photolithography after applying the wiring material is performed. Stacking the third metal layer and the fourth metal layer; Forming a second passivation layer on top of the second metal layer by using nitrogen or oxygen plasma generated by injecting nitrogen or oxygen gas while maintaining a vacuum; Forming a photoresist pattern on the second passivation film; Etching the second passivation layer, the fourth metal layer, and the third metal layer to form a gate pattern including a gate line, a gate pad, and a gate electrode; And Stripping the photoresist pattern to remove the thin film transistor substrate. The method of claim 7, wherein the third metal layer is formed of at least one selected from the group consisting of chromium, aluminum, copper, molybdenum, and tungsten, and the fourth metal layer is formed from at least one selected from the group consisting of aluminum, molybdenum, and copper. The manufacturing method of the thin film transistor substrate for liquid crystal display devices characterized by the above-mentioned. The method of claim 8, wherein the third metal layer is formed of chromium, and the fourth metal layer is formed of aluminum. The method of claim 7, wherein the second passivation film is an oxide film or a nitride film having a thickness in a range of 100 ± 50 μs. Depositing a first metal layer and a second metal layer on the substrate; Forming a passivation layer on top of the second metal layer using nitrogen or oxygen plasma generated by injecting nitrogen or oxygen gas while maintaining a vacuum; Forming a photoresist pattern on the passivation film; Etching the passivation layer, the second metal layer, and the first metal layer to form a gate pattern including a gate line, a gate pad, and a gate electrode; Stripping and removing the photoresist pattern; Stacking a gate insulating film on the gate pattern; Forming a semiconductor layer, an intermediate layer, and a conductor layer on the gate insulating film; Forming a photoresist film, and then exposing and developing the photoresist film to form a thickness of a channel portion located between a source electrode and a drain electrode to be formed later than a thickness of a data wiring portion to be formed later, and removing the remaining portion of the photoresist pattern. ; The conductor layer, the intermediate layer, and the semiconductor layer are etched using the obtained photoresist pattern, leaving the semiconductor layer in the channel portion, leaving all of the lower layer in the data wiring portion, and all of the conductor layer, the intermediate layer, and the semiconductor layer in the remaining portions. Removing; Forming a contact hole in the passivation layer so that a part of the drain electrode is exposed after laminating a passivation layer on the obtained data line and source / drain electrodes; Stacking an ITO film which is a transparent conductive material; And Forming a pixel electrode by etching the ITO film; and manufacturing a thin film transistor substrate for a liquid crystal display device. The method of claim 11, wherein the first metal layer is formed of at least one selected from the group consisting of chromium, aluminum, copper, molybdenum, and tungsten, and the second metal layer is formed of at least one selected from the group consisting of aluminum, molybdenum, and copper. The manufacturing method of the thin film transistor substrate for liquid crystal display devices characterized by the above-mentioned. The method of claim 11, wherein the passivation layer is an oxide film or a nitride film having a thickness in a range of 100 ± 50 μs. The thin film transistor substrate of claim 11, wherein the plasma treatment condition using nitrogen or oxygen gas has a power in a range of 0.3 to 1.5 kw / cm ² and a processing time in a range of 5 to 25 seconds. Manufacturing method. The method of claim 11, wherein the forming of the data line and the source / drain electrode by photolithography after applying the wiring material is performed. Stacking the third metal layer and the fourth metal layer; Forming a second passivation layer on top of the second metal layer by using nitrogen or oxygen plasma generated by injecting nitrogen or oxygen gas while maintaining a vacuum; Forming a photoresist pattern on the second passivation film; Etching the second passivation layer, the fourth metal layer, and the third metal layer to form a gate pattern including a gate line, a gate pad, and a gate electrode; And Stripping the photoresist pattern to remove the thin film transistor substrate. The method of claim 15, wherein the third metal layer is formed of at least one selected from the group consisting of chromium, aluminum, copper, molybdenum, and tungsten, and the fourth metal layer is formed from at least one selected from the group consisting of aluminum, molybdenum, and copper. The manufacturing method of the thin film transistor substrate for liquid crystal display devices characterized by the above-mentioned. The method of claim 15, wherein the second passivation film is an oxide film or a nitride film having a thickness in a range of 100 ± 50 μs. Forming a data line including data lines on the insulating substrate; Forming a color filter of red, green, and blue on the substrate; Depositing a buffer material to form a buffer layer covering the data line and the color filter; Stacking a first metal layer and a second metal layer on the buffer layer; Forming a passivation layer on top of the second metal layer using nitrogen or oxygen plasma generated by injecting nitrogen or oxygen gas while maintaining a vacuum; Forming a photoresist pattern on the passivation film; Etching the passivation layer, the second metal layer, and the first metal layer to form a gate pattern including a gate line, a gate pad, and a gate electrode; Stripping and removing the photoresist pattern; Forming a gate insulating film covering the gate wiring; Forming an island-like ohmic contact layer and a semiconductor layer pattern on the gate insulating layer, and simultaneously forming a first contact hole in the gate insulating layer and the buffer layer to expose a portion of the data line; Forming a pixel wiring on the island-shaped ohmic contact layer pattern, the pixel wiring including a source electrode and a drain electrode formed of the same layer and a pixel electrode connected to the drain electrode; And removing the exposed portion of the ohmic contact layer pattern disposed between the source electrode and the drain electrode to separate the ohmic contact layer pattern on both sides. The method of claim 18, wherein the first metal layer is formed of at least one selected from the group consisting of chromium, aluminum, copper, molybdenum, and tungsten, and the second metal layer is formed from at least one selected from the group consisting of aluminum, molybdenum, and copper. The manufacturing method of the thin film transistor substrate for liquid crystal display devices characterized by the above-mentioned. 19. The method of claim 18, wherein the passivation film is an oxide film or a nitride film having a thickness in a range of 100 ± 50 GPa. 19. The liquid crystal display device of claim 18, wherein the plasma treatment conditions using nitrogen or oxygen gas have a power in a range of 0.3 to 1.5 kw / cm ² and a processing time in a range of 5 to 25 seconds. Manufacturing method.

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