KR100913306B1 - Method for forming molybdenum thin film pattern and method for manufacturing thin film transistor substrate of liquid crystal display device using same - Google Patents

Abstract

A method of forming a Mo thin film pattern having excellent etching characteristics and a method of manufacturing a thin film transistor substrate of a liquid crystal display using the same are disclosed. First, a power in the range of 12,000 to 16,000 Watts is applied at a temperature in the range of 80 to 150 ° C., and Mo is deposited to form a Mo thin film at a deposition rate of 100 to 120 mW / sec. Next, the Mo thin film to be formed is etched to form a Mo thin film pattern. The Mo thin film pattern to be formed is free from residues or stains, does not produce interlayer differences of the double film, and is produced in a clean pattern. Therefore, when the Mo thin film pattern deposited and etched according to such deposition conditions is applied in the manufacture of the thin film transistor substrate for a liquid crystal display device, it is possible to manufacture a substrate with reduced defects and improved quality.

Description

Method of forming a molybdenum thin film pattern and a method of manufacturing a thin film transistor substrate of the liquid crystal display using the same {Method Of Forming Mo Thin Film Pattern And Method Of Manufacturing Thin Film Transistor Of Liquid Crystal Display Device Using The Same}

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1;

3 to 6 are cross-sectional views illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention according to a process sequence thereof.

7A to 7C are photographic views illustrating etching characteristics of Mo thin films deposited according to Comparative Examples;

8A to 8C are photographic diagrams illustrating etching characteristics of a Mo thin film deposited during a manufacturing process of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention;

9 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

10 and 11 are cross-sectional views taken along lines VII-VII 'and IX-IX' of FIG. 9, respectively.                 

12A and 12B to 19A and 19B are cross-sectional views illustrating a process of manufacturing the thin film transistor substrate illustrated in FIGS. 10 and 11, respectively.

20 is a layout view of a thin film transistor substrate according to a third exemplary embodiment of the present invention.

FIG. 21 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 20 along a cutting line XIX-XIX ′,

22 to 29 are cross-sectional views for describing a manufacturing process of the thin film transistor substrate illustrated in FIG. 21.

The present invention relates to a method of forming a Mo thin film pattern and a method of manufacturing a thin film transistor substrate of a liquid crystal display device using the same, and in detail, by applying a new deposition condition to improve the etching characteristics to form a good quality Mo thin film pattern The present invention relates to a method for manufacturing a thin film transistor substrate of a liquid crystal display device using the same.

In general, a display device is an electro-optical device used to convert an electrical signal into a visual image so that a human can directly recognize information. Among such display devices, a liquid crystal display device is a display device that uses an optical property of a liquid crystal by changing an arrangement of liquid crystal molecules by applying an electric field.

On the other hand, when the thin film transistor is used in a large display substrate, the gate resistance should be small in order to prevent signal delay or flicker of the image. It is common to use a material such as aluminum or an aluminum alloy for a metal having low resistance and high conductivity. However, when aluminum or aluminum alloys are used, it is necessary to add anodization processes to reinforce the weak physical properties of aluminum. In addition, in the case of reinforcing aluminum by using ITO at the end portion, there is a problem in that the contact property between aluminum or an aluminum alloy and ITO is not good, and another metal must be interposed.

Chromium, on the other hand, is mainly used as a data line because the resistive contact with amorphous silicon and ITO is better than aluminum, although the resistance is rather large. However, when the chromium film is patterned, a pattern in which the inclination angle of the chromium film reaches almost 90 ° is formed due to strong adhesion to the photosensitive film. Accordingly, the protective film and the ITO film formed thereon also have an inclination angle close to the vertical, so that the films have a weak structure. In addition, since the chromium film is difficult to control the stress according to the deposition thickness, there is a limit to lower the resistance of the wiring by forming a thick with a narrow width.

In the case of copper, there is a disadvantage that the adhesion to the substrate or the insulating film is inferior and natural oxidation easily occurs. Therefore, metals such as molybdenum have been used a lot recently. In the case of applying Mo as the wiring, the resistance can be reduced due to the reduction of the specific resistance due to the material properties of the material itself.

As a result, a material such as aluminum, an aluminum alloy, molybdenum, copper, or the like having a low resistivity of 15 µΩcm or less is suitable for wiring of the display device. On the other hand, the wiring should have an end for receiving a signal from the outside or transmitting a signal to the outside. The material for the end has a resistivity below a certain level, but of course, it should not oxidize well and should not easily break in the manufacturing process. Aluminum and aluminum alloys have very low resistivity but are not suitable for finishing materials. In contrast, materials such as chromium, tantalum, titanium, molybdenum and alloys thereof are suitable for finishing but have a higher resistivity than aluminum. Therefore, when making wiring, use a metal having both characteristics or use a conductive film having low resistance and an end conductive film so that the resistance can be used as a low end.

In the case where the wiring is a multilayer film, the multilayer conductive film is simultaneously etched under one etching condition and processed into a tapered shape having a gentle inclination angle. To this end, it is preferable to select a conductive film having a small etching ratio in order to have a taper angle in a range of about 20 ° to 70 ° with respect to the same etching condition.

The multilayer conductive film may be used as a gate line for applying a scan signal or a data line for applying a data signal in the display device.

It is an object of the present invention to meet the above-mentioned recent demands, and it is possible to form an Mo thin film which is easy for etching, noting that the Mo film, which is attracting attention as a metal wiring material, has different results upon etching depending on the conditions of the forming process. It is an object of the present invention to provide a method for forming a pattern of an Mo thin film prepared according to the optimum conditions.

Another object of the present invention is to provide a method of manufacturing a thin film transistor substrate for a liquid crystal display device by which the optimum etching characteristics can be obtained and the occurrence of defects in a subsequent process can be reduced by employing the Mo thin film pattern.

In order to achieve the above object, in the present invention, in the temperature range of 80 to 150 ° C., power is applied in the range of 12,000 to 16,000 Watts, and the deposition rate is 100 to 120 mW / sec to form Mo to form a Mo thin film. And it provides a method for forming a Mo thin film pattern comprising the step of etching the Mo thin film formed.

In particular, the formation of the Mo thin film is preferably carried out by a single-leaf type, and the size of the target when forming the Mo thin film is preferably applied in the range of 144 ± 10 x 660 ± 10 (mm x mm).

The etching step may be performed using an etching solution containing phosphoric acid / nitric acid / acetic acid / stabilizer.

Another object of the present invention described above

Applying a power in the range of 12,000 to 16,000 Watts at a temperature range of 80 to 150 DEG C and a first gate wiring layer on the substrate, and depositing Mo at a deposition rate of 100 to 120 mA / sec to form a second gate wiring layer. step;

Etching the first and second gate wiring layers to form a gate pattern including a gate line, a gate end, and a gate electrode;

Stacking a gate insulating film;

Forming a semiconductor layer pattern and an ohmic contact layer pattern;

Forming and patterning a MoW thin film, a data line intersecting the gate line, a data end connected to the data line, a source electrode connected to the data line and adjacent to the gate electrode, and opposite to the source electrode with respect to the gate electrode. Forming a data line including a drain electrode positioned at the second electrode;

Forming a protective film;

Patterning the passivation layer together with the gate insulating layer to form contact holes exposing the gate line end, the data line end, and the drain electrode, respectively;

Stacking a transparent conductive film; And

Etching the transparent conductive layer to form an auxiliary gate line end, an auxiliary data line end, and a pixel electrode connected to the gate line end, the data line end, and the drain electrode, respectively, of the thin film transistor substrate for a liquid crystal display device. It is achieved by the manufacturing method.

In particular, the first gate wiring layer is preferably an Al-Nd layer, and the second gate wiring layer is preferably formed in a single leaf type.

Another object of the present invention described above

Applying a power in the range of 12,000 to 16,000 Watts at a temperature range of 80 to 150 DEG C and a first gate wiring layer on the substrate, and depositing Mo at a deposition rate of 100 to 120 mA / sec to form a second gate wiring layer. step;

Etching the first and second gate wiring layers to form a gate pattern including a gate line, a gate line end, and a gate electrode;                     

Stacking a gate insulating film;

Stacking a semiconductor layer, an ohmic contact layer and a conductor layer of MoW;

Forming a photoresist pattern having a first portion, a second portion thicker than the first portion, and a third portion thinner than the first thickness;

Forming a data line including a data line, an end of the data line connected to the data line, a data line including a source electrode and a drain electrode, and an ohmic contact layer pattern and a semiconductor layer pattern using the photoresist pattern;

Forming a protective film;

Patterning the passivation layer together with the gate insulating layer to form contact holes exposing the gate line end, the data line end, and the drain electrode, respectively;

Stacking a transparent conductive film; And

Etching the transparent conductive layer to form an auxiliary gate line end, an auxiliary data line end, and a pixel electrode connected to the gate line end, the data line end, and the drain electrode, respectively; It is also achieved by the production method.

In particular, the first portion may be formed to be positioned between the source electrode and the drain electrode, and the second portion may be formed to be positioned above the data line.

Another object of the present invention described above                     

Forming a data line including MoW data lines on the insulating substrate;

Forming a color filter of red, green, and blue on the substrate;

Depositing a buffer material to form a buffer layer covering the data line and the color filter;

The second gate wiring layer is formed by applying Mo to the first gate wiring layer and the temperature in the temperature range of 80 to 150 ° C. and the deposition rate of 100 to 120 mA / sec. Making;

Etching the first and second gate wiring layers to form a gate wiring including a gate line and a gate electrode;

Forming a gate insulating film covering the gate wiring;

Forming an island-like ohmic contact layer and a semiconductor layer pattern on the gate insulating layer, and simultaneously forming a first contact hole in the gate insulating layer and the buffer layer to expose a portion of the data line;

A pixel including a source electrode and a drain electrode formed on the island-like ohmic contact layer pattern and then etched and separated from each other and formed of the same layer, and a pixel electrode connected to the drain electrode Forming a wiring;

And removing the exposed portion of the ohmic contact layer pattern disposed between the source electrode and the drain electrode to separate the ohmic contact layer pattern on both sides. Is also achieved.

Hereinafter, a thin film transistor substrate and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. In describing the manufacturing process of the substrate, the deposition and etching portions of the Mo thin film will be described in detail, and the general process method will be described for the remaining processes.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II of the thin film transistor substrate shown in FIG.

The first gate wiring layers 221, 241 and 261 made of aluminum or an aluminum alloy such as aluminum-odium (Al-Nd) and the second gate wiring layers 222, 242 and 262 made of molybdenum on the insulating substrate 10. A gate wiring formed of a double layer of is formed. The gate line is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate line end 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. And a gate electrode 26 of the thin film transistor connected thereto.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate lines 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24 in an island shape, and silicide or n-type impurities are doped with high concentration on the semiconductor layer 40. Resistive contact layers 54 and 56 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.

On the ohmic contacts 54 and 56 and the gate insulating film 30, data wiring layers 62, 65, 66 and 68 made of a molybdenum-tungsten alloy film or the like are formed. The data lines 62, 65, 66, and 68 are formed in the vertical direction and intersect with the gate line 22 to define the pixel, the branch of the data line 62, the data line 62, and the resistive contact layer 54. It is connected to one end of the source electrode 65 and the data line 62 extending to the upper part, and is separated from the data line end 68 and the source electrode 65 to which an image signal from the outside is applied, and the gate electrode 26. ) And a drain electrode 66 formed over the ohmic contact layer 56 opposite the source electrode 65. The passivation layer 70 is formed on the data wires 62, 65, 66, and 68 and the semiconductor layer 40 not covered by the data lines 62.

In the passivation layer 70, contact holes 76 and 78 exposing the drain electrode 66 and the data line end 68 are formed, respectively, and the contact hole exposing the gate line end 24 together with the gate insulating layer 30 ( 74 is formed. At this time, the contact holes (74, 78) exposing the ends 24, 68 may be formed in a variety of angles or circular shape, the area is not more than 2mm × 60㎛, preferably 0.5mm × 15㎛ or more Do.

On the passivation layer 70, a pixel electrode 82, which is electrically connected to the drain electrode 66 and positioned in the pixel, is formed through the contact hole 76. In addition, the auxiliary gate line end 86 and the auxiliary data line end 88, which are connected to the gate line end 24 and the data line end 68, respectively, through the contact holes 74 and 78 on the passivation layer 70. Formed. Here, the pixel electrode 82, the auxiliary gates, and the data line ends 86 and 88 are made of indium tin oxide (ITO).

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring.

The pixel electrode 82 is also formed to overlap the data line 62 to maximize the aperture ratio. As such, even when the pixel electrode 82 is overlapped with the data line 62 in order to maximize the aperture ratio, the dielectric constant of the passivation layer 70 is low, so that the parasitic capacitance formed therebetween is small.

Next, a method of manufacturing the thin film transistor substrate for a liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3 to 6.

First, as shown in FIG. 3, the first gate wiring layers 221, 241, and 261 are laminated by depositing aluminum or an aluminum alloy having excellent physicochemical properties on the substrate 10, and by depositing molybdenum having a low resistance. The two gate wiring layers 222, 242, and 262 are stacked and then patterned to form a gate wiring extending in the horizontal direction including the gate line 22, the gate electrode 26, and the gate line end 24.                     

At this time, preferred conditions for depositing the Mo are as shown in Table 1 below. The target is fed in a sheet-fed fashion to achieve deposition.

Thickness Pressure (mTorr)  Watt Temperature (℃) Watt Deposition Rate (Å / sec) Speed {1scan = 5.6s} Target size (mm x mm) 2000 3.15 2550 100 14000 111.11 6scan 144 x 660

And the etching solution for the patterning of the Mo thin film formed in accordance with the conditions shown in Table 1 is to use a solution of phosphoric acid / nitric acid / acetic acid / stabilizer in a ratio of 70% / 2% / 10.5% / 3%. When the gate double layer is formed to have a thickness of Mo 500Å / Al-Nd 2500Å, the whole glass is immersed in a 35 ° C solution, etched for 70 to 90 seconds, and then washed with distilled water.

According to the method described above, it was confirmed that the gate wiring obtained by depositing and etching the Mo thin film was etched cleanly without residue or stain with a taper of 40 to 50 °.

Next, as shown in FIG. 4, a three-layer film of a gate insulating film 30 made of silicon nitride, a semiconductor layer 40 made of amorphous silicon, and a doped amorphous silicon layer is successively laminated, and the semiconductor layer 40 and doped The amorphous silicon layer is etched to form island-like semiconductor layers 40 and ohmic contacts 55 and 56 on the gate insulating layer 30 on the gate electrode 24.

Next, as shown in FIG. 5, the molybdenum-tungsten alloy is deposited to stack the data wiring layers 65, 66, and 68, and photoetched to cross the gate line 22 and the data line 62 and the data line 62. ), The source electrode 65 and the data line 62 connected to the gate electrode 26 and extending above the gate electrode 26 are separated from the data line end 68 and the source electrode 64 connected to one end. A data line including a drain electrode 66 facing the source electrode 65 is formed around 26. It is preferable to use a molybdenum-tungsten alloy containing about 10 wt% of tungsten as the data pattern.

Subsequently, the doped amorphous silicon layer pattern not covered by the data lines 62, 65, 66, and 68 is etched and separated on both sides of the gate electrode 26, while the doped amorphous silicon layers 55 and 56 are formed on both sides. The semiconductor layer pattern 40 between the layers is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma. Next, a protective film as shown in FIG. 6 is formed.

Subsequently, the passivation layer is patterned together with the gate insulating layer 30 by a photolithography process to form contact holes 74, 76, and 78 that expose the gate line end 24, the drain electrode 66, and the data line end 68. do. Here, the contact holes 74, 76, 78 may be formed in an angled or circular shape, the area of the contact holes 74, 78 exposing the ends 24, 68 is not more than 2mm × 60㎛ It is preferable that it is 0.5 mm x 15 micrometers or more.

Next, as shown in FIGS. 1 and 2, second and third contacts with the pixel electrode 82 connected to the drain electrode 66 through the first contact hole 76 by depositing and photolithography the ITO film. Through holes 74 and 78, the auxiliary gate line end 86 and the auxiliary data line end 88 which are connected to the gate line end 24 and the data line end 68, respectively, are formed. It is preferable to use nitrogen as the gas used in the pre-heating process before laminating ITO. This is to prevent the metal oxide film from being formed on the upper portions of the metal films 24, 66, and 68 exposed through the contact holes 74, 76, and 78.

Mo thin film prepared under the conditions shown in Table 1 after forming the Mo thin film in-line by the conditions as shown in Table 2 to compare the characteristics with the gate wiring layer prepared according to the embodiment of the present invention described above Etching was performed under the same conditions as for etching.

Thickness Pressure (mTorr)  Watt Temperature (℃) Watt Deposition Rate (Å / sec) Speed {1scan = 5.6s} Target size (mm x mm) 2000 3 2550 50 3650 41.67 180mm / min 144 x 660

7A to 7C are photographic diagrams showing etching characteristics of Mo thin films deposited according to comparative examples, and FIGS. 8A to 8C are depositions in a manufacturing process of a thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention. It is a photograph figure which shows the etching characteristic of the Mo thin film. The first gate wiring layer pattern 21 and the second gate wiring layer pattern 23 are formed on the substrate 10 by depositing the first gate wiring layer and the second gate wiring layer and then etching them.

7A corresponds to a case where the Mo film is deposited according to a conventional condition and then etched with end point detection (EPD) + 50% O / E (over etch), and FIG. 7B shows an EPD + 75% O / E. This corresponds to the case of etching, and Figure 7c corresponds to the case of etching under EPD + 100% O / E conditions. In the figure, in particular, it can be seen that the upper layer is not completely etched to be a cause of the defect generation. This phenomenon becomes more severe as the over-etching time increases, and it can be seen that FIG. 7B is more severe than FIG. 7A and FIG. 7C is more severe than FIG. 7B. If such a taper profile is poor, a step coverage problem occurs during the post-stage process, resulting in a data open failure.

Meanwhile, FIG. 8A corresponds to a case where the Mo film is deposited according to the conditions of the present invention and then etched with end point detection (EPD) + 50% O / E (over etch), and FIG. 8B shows EPD + 75% O / E. Corresponds to the case of etching under conditions, and FIG. 8C corresponds to the case of etching under EPD + 100% O / E conditions. In the drawings, the Mo film formed according to the deposition conditions of the present invention is etched to achieve a gentle taper angle without a difference between the lower layer and the upper layer, and it can be seen that a good profile is maintained without any effect even if the overetch time is increased.

As described above, the method can be applied to a manufacturing method using five masks, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings.

First, the unit pixel structure of the thin film transistor substrate for a liquid crystal display device completed using the four masks according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 9 to 11.

FIG. 9 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 10 and 11 are lines VIII-VIII 'and IX-IX', respectively, of the thin film transistor substrate shown in FIG. Is a cross-sectional view.                     

First, similarly to the first embodiment, the first gate wiring layers 221, 241, and 261 made of aluminum or an aluminum-neo alloy and the second gate wiring layers 222, 242, and 262 formed of molybdenum are formed on the insulating substrate 10. The gate wiring which consists of a double layer of () is formed. The gate wiring includes a gate line 22, a gate line end 24, and a gate electrode 26.

The storage electrode line 28 is formed on the substrate 10 in parallel with the gate line 22. The storage electrode line 28 also includes a double layer of the first gate wiring layer 281 and the second gate wiring layer 282. The storage electrode line 28 overlaps the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor which improves charge storage capability of the pixel. The pixel electrode 82 and the gate line to be described later will be described. It may not be formed if the holding capacity generated by the overlap of (22) is sufficient. The same voltage as that of the common electrode of the upper substrate is usually applied to the storage electrode line 28.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and the storage electrode line 28 to cover the gate wirings 22, 24, 26, and 28.

On the gate insulating layer 30, semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed, and on the semiconductor patterns 42 and 48, n-type impurities such as phosphorus (P) have a high concentration. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56, and 58, data wiring layers 62, 64, 65, 66, and 68 made of molybdenum-tungsten alloy films are formed. The data line is a thin film that is a branch of the data line 62 formed in the vertical direction, the data line end 68 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion 62, 68, 65 made of the source electrode 65 of the transistor, and separated from the data line portions 62, 68, 65, and the channel portion C of the gate electrode 26 or the thin film transistor. In addition, the drain electrode 66 of the thin film transistor positioned on the opposite side of the source electrode 65 and the conductor pattern 64 for the storage capacitor located on the storage electrode line 28 are also included. When the storage electrode line 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor. The passivation layer 70 is formed on the data lines 62, 64, 65, 66, and 68.

The protective film 70 has contact holes 76, 78, and 72 that expose the drain electrode 66, the data line end 64, and the conductive pattern 68 for the storage capacitor, and together with the gate insulating film 30. It has a contact hole 74 that exposes the gate line end 24.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material of indium tin oxide (ITO), and is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor pattern 64 through the contact hole 72 to transmit an image signal to the conductor pattern 64. On the other hand, an auxiliary gate line end 86 and an auxiliary data line end 88 are formed on the gate line end 24 and the data line end 68 through the contact holes 74 and 78, respectively. They are not essential to serve to protect the ends and to protect adhesion between the ends 24 and 68 and external circuit devices, and their application is optional.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 9 to 11 using four masks will be described in detail with reference to FIGS. 12A and 12B to 19A and 19B.

First, as shown in FIGS. 12A and 12B, the first gate wiring layers 221, 241, 261, and 281 are stacked by depositing aluminum or an aluminum-neodium alloy having excellent physicochemical properties as in the first embodiment. The second gate wiring layers 222, 242, 262, and 282 are stacked by depositing molybdenum having a low resistance, and then photoetched to include the gate line 22, the gate line end 24, and the gate electrode 26. The gate wiring and the sustain electrode line 28 are formed. At this time, the deposition conditions of molybdenum were the same as the conditions shown in Table 1 and the etching was carried out under the same conditions as shown in the first embodiment.

Next, as shown in FIGS. 13A and 13B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kPa and 500 kPa to 2,000 using chemical vapor deposition. Å, 300 600 to 600 연속 of continuous deposition, and then MoW was deposited by the sputtering method as shown in the first embodiment to form the conductor layer 60, and then the photoresist film 110 on the surface of 1㎛ 2 Apply to a thickness of 탆.

Thereafter, the photosensitive film 110 is irradiated with light through a mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 14A and 14B. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure, and in the case of using a translucent film, the transmittance is different in order to control the transmittance when fabricating a mask. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 15A and 15B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

In this way, as shown in Figs. 15A and 15B, only the conductor layers of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 68 for the storage capacitor, are shown. All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 67 and 64 have the same shape as the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 16A and 16B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 below it are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions where the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 16A and 16B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductor patterns 64, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as illustrated in FIGS. 17A and 17B, the source / drain conductor pattern 67 of the channel portion C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in Fig. 2). In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include a mixture gas of CF ₄ and HCl or a mixture gas of CF ₄ and O ₂ , and CF ₄ and O ₂ . The semiconductor pattern 42 may be left at a uniform thickness. In this case, as shown in FIG. 17B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching should be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter. Next, as shown in FIGS. 18A and 18B, a protective film 70 is formed.

19A and 19B, the protective film 70 is etched together with the gate insulating film 30 to drain the electrode 66, the gate line end 24, the data line end 68, and the storage capacitor. Contact holes 76, 74, 78, and 72 are formed to expose the conductor pattern 64, respectively. At this time, the areas of the contact holes 74 and 78 exposing the ends 24 and 68 do not exceed 2 mm x 60 m, and are preferably 0.5 mm x 15 m or more.

9 to 11, a pixel electrode 82 connected to the drain electrode 66 and the conductive capacitor conductor 64 for the storage capacitor is deposited by depositing and photolithography an ITO layer having a thickness of 400 kHz to 500 kHz. ), An auxiliary gate line end 86 connected to the gate line end 24 and an auxiliary data line end 88 connected to the data line end 68 are formed.

On the other hand, it is preferable to use nitrogen as the gas used in the pre-heating process before laminating the ITO, which is the metal film 24, 64, which is exposed through the contact holes 72, 74, 76, 78, This is to prevent the metal oxide film from being formed on the upper portions 66 and 68.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48 may be formed using a single mask, and the manufacturing process may be simplified by separating the source electrode 65 and the drain electrode 66 in this process.

The method according to the present invention can be easily applied to an array on color filter (AOC) structure in which a thin film transistor array is formed on a color filter.

20 is a layout view of a thin film transistor substrate according to a third exemplary embodiment of the present invention, and FIG. 21 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 20 along a cutting line XIX-XIX '. FIG. 21 also shows a lower substrate as a thin film transistor substrate and an upper substrate facing the same.

First, data wirings 120, 121, and 124 made of molybdenum-tungsten alloy are formed on the lower substrate.

Data lines 120, 121, and 124 are connected to data lines 120 and data lines 120 extending in a vertical direction, and receive data signals from the outside and transmit data lines 120 to data lines 120. 124 and a light blocking unit 121 for blocking light incident to the semiconductor layer 170 of the thin film transistor formed later from the lower portion of the substrate 100 by the branch of the data line 120. Here, the light blocking unit 121 also has a function of a black matrix that blocks light leakage, and may be formed by disconnecting the data line 120 and disconnected wiring.

Here, the data wirings 120, 121, and 124 are formed of a molybdenum-tungsten alloy layer of a material having a low resistance, considering that the pixel wirings 410, 411, 412 and the auxiliary ends 413, 414 formed thereafter are ITO. To manufacture.

On the lower insulating substrate 100, color filters 131, 132, and 133 of red (R), green (G), and blue (B), whose edges overlap the edges of the data lines 120 and 121, are respectively formed. Formed. The color filters 131, 132, and 133 may be formed to cover all of the data lines 120.

The buffer layer 140 is formed on the data lines 120, 121, 124, and the color filters 131, 132, and 133. Here, the buffer layer 140 is a layer for preventing outgassing from the color filters 131, 132, and 133 and preventing the color filter itself from being damaged by heat and plasma energy in a subsequent process. In addition, since the buffer layer 140 separates the lowermost data lines 120, 121, and 124 from the thin film transistor array, the lower the dielectric constant and the thicker the thickness, the more advantageous it is to reduce the parasitic capacitance therebetween.

On the buffer layer 140 is formed a double layer gate wiring including a lower layer 501 made of a material such as aluminum and an aluminum alloy and an upper layer 502 made of molybdenum.

The gate line extends in the horizontal direction and is connected to the gate line 150 and the gate line 150 defining the unit pixel by crossing the data line 120 to receive the scan signal from the outside to the gate line 150. And a gate electrode 151 of the thin film transistor which is a part of the gate line end 152 and the gate line 150 to transmit.

Here, the gate line 150 overlaps with the pixel electrode 410 to be described later to form a storage capacitor that improves the charge storage capability of the pixel, and the sustain is generated by overlapping the pixel electrode 410 and the gate line 150 to be described later. If the capacitance is not sufficient, a common electrode for the storage capacitance may be formed.

As described above, in the case where the gate wiring is formed in two or more layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials. Bilayers are an example.

The low temperature deposition gate insulating layer 160 is formed on the gate lines 150, 151, and 152 and the buffer layer 140. In this case, the low temperature deposition gate insulating film 160 may be formed of an organic insulating film, a low temperature amorphous silicon oxide film, a low temperature amorphous silicon nitride film, or the like. In the thin film transistor structure according to the present invention, since the color filter is formed on the lower substrate, the gate insulating film may be deposited at a low temperature, not a normal insulating film deposited at a high temperature, for example, low temperature deposition capable of depositing at a low temperature of 250 ° C. or less. An insulating film is used.

The double layer semiconductor layer 171 is formed in an island shape on the gate insulating layer 160 of the gate electrode 151. In the double layer semiconductor layer 171, the lower semiconductor layer 701 is made of amorphous silicon having a high band gap, and the upper semiconductor layer 702 is made of ordinary amorphous silicon having a lower band gap than the lower semiconductor 701. . For example, the band gap of the lower semiconductor layer 701 may be 1.9 to 2.1 eV, and the band gap of the upper semiconductor layer 702 may be 1.7 to 1.8 eV. Here, the lower semiconductor layer 701 is formed to a thickness of 50 to 200 GPa, and the upper semiconductor layer 702 is formed to a thickness of 1000 to 2000 GPa.

As such, a band offset corresponding to the difference between the band gaps of the two layers is formed between the upper semiconductor layer 702 and the lower semiconductor layer 701 having different band gaps. At this time, when the TFT is turned on, a channel is formed in the band offset region located between the two semiconductor layers 701 and 702. Since this band offset region has basically the same atomic structure, there are few defects and favorable TFT characteristics can be expected. The semiconductor layer 171 may be formed as a single layer.

On the semiconductor layer 171, ohmic contact layers 182 and 183 including amorphous silicon or microcrystalline silicon or metal silicide doped with a high concentration of n-type impurities such as phosphorus (P) are mutually formed. It is formed separately.

On the ohmic contacts 182 and 183, pixel wirings 410, 411 and 412 including source and drain electrodes 412 and 411 and pixel electrodes 410 made of ITO are formed. The source electrode 412 is connected to the data line 120 through the contact hole 161 formed in the gate insulating layer 160 and the buffer layer 140. The drain electrode 411 is connected to the pixel electrode 410 and receives an image signal from the thin film transistor and transmits the image signal to the pixel electrode 410. The pixel wirings 410, 411 and 412 are made of a transparent conductive material of ITO.

In addition, an auxiliary gate line end 413 connected to the gate line end 152 and the data line end 124 through contact holes 162 and 164 in the same layer as the pixel lines 410, 411 and 412, and An auxiliary data line end 414 is formed. Here, the auxiliary gate line end 413 is in direct contact with the molybdenum film, which is the upper layer 502 of the gate line end 152, and the auxiliary data line end 414 is also the upper layer 202 of the data line end 124. Is in direct contact with the molybdenum-tungsten alloy film. The pixel electrode 410 also overlaps the neighboring gate line 150 and the data line 120 to increase the aperture ratio, but may not overlap.

A passivation layer 190 is formed on the source and drain electrodes 412 and 411 to protect the thin film transistor, and a photosensitive colored organic layer 430 having a dark color having excellent light absorption is formed thereon. have. In this case, the colored organic layer 430 serves to block light incident to the semiconductor layer 171 of the thin film transistor, and adjusts the height of the colored organic layer 430 to face the lower insulating substrate 100. It is used as a spacer to maintain the gap between the insulating substrate 200. Here, the passivation layer 190 and the organic layer 430 may be formed along the gate line 150 and the data line 120, and the organic layer 430 blocks light leaking around the gate line and the data line. It can have a role.

Meanwhile, the common substrate 210 for generating an electric field together with the pixel electrode 410 is formed on the entire upper surface of the upper substrate 200.

Next, a method of manufacturing the thin film transistor substrate according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 22 to 29 and FIGS. 20 and 21.

First, as shown in FIG. 22, the MoW conductive material is deposited by a sputtering method, and is dry or wet etched by a photolithography process using a mask. The data line 120 and the data line end ( The data wires 120, 121, and 124 including the 124 and the light blocking unit 121 are formed.

Subsequently, as shown in FIG. 23, a photosensitive material including pigments of red (R), green (G), and blue (B) is sequentially applied, and patterned by a photo process using a mask to form red (R) and green (G). ), And the color filters 131, 132, and 133 of blue (B) are sequentially formed. At this time, the red (R), green (G), and blue (B) color filters 131, 132, and 133 are formed using three masks, but they are formed by moving one mask to reduce manufacturing costs. It may be. In addition, using a laser transfer method or a print method can be formed without using a mask, thereby minimizing manufacturing costs. At this time, as shown in the figure. The edges of the color filters 131, 132, and 133 of red (R), green (G), and blue (B) may be formed to overlap the data line 120. Subsequently, as shown in FIG. 24, a buffer layer 140 is formed on the insulating substrate 100.

Subsequently, the aluminum-neodium alloy and the molybdenum conductive material are continuously deposited by a method such as sputtering and patterned by a photolithography process using a mask, and the gate line 150, the gate electrode 151, and the gate line ends on the buffer layer 140. Gate wirings 150, 151, and 152 including 152 are formed. The deposition conditions of molybdenum were the same as those shown in Table 1 and the etching thereof was performed under the same conditions as those shown in the first embodiment.

Subsequently, as shown in FIG. 25, the low-temperature deposition gate insulating layer 160, the first amorphous silicon layer 701, and the second amorphous silicon layer 702 are disposed on the gate wirings 150, 151, and 152 and the organic insulating layer 140. And an amorphous silicon film 180 doped with impurities.

The low temperature deposition gate insulating layer 160 may be formed using an organic insulating layer, a low temperature amorphous silicon oxide film, a low temperature amorphous silicon nitride film, or the like, which may be deposited even at a deposition temperature of 250 ° C. or lower.

The first amorphous silicon film 701 is formed of an amorphous silicon film having a high band gap, for example, a band gap of 1.9 to 2.1 eV, and the second amorphous silicon film 702 has a band gap of the first amorphous silicon film. For example, it is formed of a conventional amorphous silicon film having a band gap of less than 701, for example, 1.7 to 1.8 eV. In this case, the first amorphous silicon film 701 may be deposited by CVD by adding an appropriate amount of CH ₄ , C ₂ H ₂ , or C ₂ H ₆ to SiH _{4, which} is a raw material gas of the amorphous silicon film. . For example, when SiH ₄ : CH ₄ is added to a CVD apparatus at a ratio of 1: 9, and the deposition process is performed, an amorphous silicon film containing about 50% of C and having a band gap of 2.0 to 2.3 eV is deposited. can do. As such, the band gap of the amorphous silicon layer is affected by the deposition process conditions, and the band gap can be easily adjusted in the range of 1.7 to 2.5 eV, depending on the amount of carbon compound added.

In this case, the low temperature deposition gate insulating layer 160, the first amorphous silicon film 701, the second amorphous silicon film 702, and the amorphous silicon film 180 doped with impurities are continuous without breaking the vacuum in the same CVD apparatus. Can be deposited.

Next, as shown in FIG. 26, the first amorphous silicon film 701, the second amorphous silicon film 702, and the doped amorphous silicon film 180 are patterned by a photolithography process using a mask to form an island shape. The semiconductor layer 171 and the ohmic contact layer 181 at the same time, and at the same time, the data line 120, the gate line end 152, and the data line end 124 on the low temperature deposition gate insulating layer 160 and the organic insulating layer 140. Contact holes 161, 162, and 164 are respectively formed.

In this case, except for the upper portion of the gate electrode 151, all of the first and second amorphous silicon layers 701 and 702 and the amorphous silicon layer 180 doped with impurities should be removed, and the upper portion of the gate line end 152 is removed. In addition, the gate insulating layer 160, along with the first and second amorphous silicon films 701 and 702 and the doped amorphous silicon film 180, must also be removed, and the data line 120 and the data line end 124 may be removed. The organic insulating layer 140 may be removed along with the first and second amorphous silicon layers 701 and 702, the amorphous silicon layer 180 doped with impurities, and the low temperature deposition gate insulating layer 160.

In order to form this in a photolithography process using one mask, a photoresist pattern having a different thickness is used as an etching mask. This will be described with reference to FIGS. 27 and 28 together.

First, as shown in FIG. 27, after the photoresist film is applied on the upper surface of the amorphous silicon film 180 doped with impurities to a thickness of 1 μm to 2 μm, the photoresist film is irradiated with light through a photo process using a mask. The photoresist patterns 312 and 314 are formed.

At this time, the first portion 312 of the photoresist patterns 312 and 314 located above the gate electrode 151 is formed to have a thickness greater than that of the remaining second portions 314, and the data line 120 and the data line The photoresist may not exist on the end 124 and the portion of the gate line end 152. It is preferable to make the thickness of the 2nd part 314 into 1/2 or less of the thickness of the 1st part 312, for example, it is good that it is 4,000 Pa or less.

As described above, there may be various ways of varying the thickness of the photosensitive film according to the position. Here, the case of using the positive photosensitive film will be described.

When the light is irradiated to the photosensitive film through a mask 1000 that can control the amount of light by forming a pattern smaller than the resolution of the exposure machine, for example, a slit or lattice pattern in the B region or a semi-transparent film, The degree to which the polymers decompose depends on the amount or intensity of light being irradiated. At this time, if the exposure is stopped at a time when the polymers of the C region completely exposed to light are completely decomposed, the amount of light passing through the B region where the slit or translucent film is formed is smaller than that of the portion completely exposed to the light. Part of the photoresist in the region is decomposed and the rest remains undecomposed. The longer exposure time decomposes all the molecules, so it should be avoided.

When the photoresist is developed, the first portion 312 in which the molecules are not decomposed remains almost intact, and the second portion 314 which is irradiated with less light remains in a thinner thickness than the first portion 312, and is completely exposed to light. The photosensitive film is almost removed at the portion corresponding to the exposed C region. Through this method, photoresist patterns having different thicknesses are formed according to positions.

Next, as shown in FIG. 28, the amorphous silicon film 180, the second amorphous silicon film 702, and the first amorphous silicon film doped with impurities using the photoresist patterns 312 and 314 as etching masks are used. 702 and the low temperature deposition gate insulating layer 160 are dry etched to complete the contact hole 162 exposing the gate line end 152, and expose the buffer layer 140 in the C region. Subsequently, dry etching the buffer layer 140 in the C region using the photoresist patterns 312 and 314 as an etching mask to complete the contact holes 161 and 164 exposing the data line 120 and the data line end 124. do.

Subsequently, the operation of completely removing the second portion 314 of the photoresist film is performed. Here, an ashing process using oxygen may be added to completely remove the photoresist residues of the second portion 314.

In this way, the second portion 314 of the photoresist pattern is removed, and the amorphous silicon film 180 doped with impurities is exposed, and the first portion 312 of the photoresist pattern is formed on the second portion 312 of the photoresist pattern. It remains reduced by thickness.

Next, the amorphous silicon film 180 doped with impurities and the first and second amorphous silicon films 701 and 702 below are etched and removed using the first portion 312 of the remaining photoresist pattern as an etching mask. As a result, an island-like semiconductor layer 171 and an ohmic contact layer 181 are left on the low temperature deposition gate insulating layer 160 on the gate electrode 151.

Finally, the remaining first portion 312 of the photoresist film is removed. Here, an ashing process using oxygen may be added to completely remove the photoresist residue of the first portion 312.

Next, as shown in FIG. 29, the ITO layer is deposited and patterned by a photolithography process using a mask to form a pixel electrode 410, a source electrode 412, a drain electrode 411, and an auxiliary gate line end 413. And the auxiliary data line end 414 is formed.

Subsequently, the resistive contact layer 181 is etched between the source electrode 412 and the drain electrode 411 as an etching mask to form a resistive contact layer pattern separated into two parts 182 and 183. The semiconductor layer 171 is exposed between the source electrode 412 and the drain electrode 411.

Finally, as shown in FIGS. 20 and 21, an insulating material such as silicon nitride or silicon oxide and an insulating material such as a photosensitive organic material including black pigment are sequentially stacked on the lower insulating substrate 100 and then masked. The exposure process is performed by using a photo process to form a colored organic layer 430, and the protective layer 190 is formed by etching the insulating material under the substrate using the colored organic layer 430 as an etching mask. In this case, the colored organic layer 430 may block light incident to the thin film transistor, and may be formed on the gate line or the data line to provide a function of blocking light leaking around the wire. In addition, as in the embodiment of the present invention, the height of the organic layer 430 may be adjusted to be used as a spacer.

Meanwhile, the common electrode 210 is formed by stacking a transparent conductive material of ITO on the upper insulating substrate 200.

As described above, when the Mo thin film is deposited and etched according to the method of the present invention, there are no residues or stains, no interlayer difference between the double layers, and a clean pattern can be produced, thereby improving the etching characteristics of the Mo thin film. .

Therefore, when the Mo thin film pattern deposited and etched according to such deposition conditions is applied in the manufacture of the thin film transistor substrate for a liquid crystal display device, it is possible to manufacture a substrate having reduced quality and improved quality.

Although the above has been described with reference to the preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated.

Claims (14)

Applying a power in the range of 12,000 to 16,000 Watts in a temperature range of 80 to 150 ° C., and depositing a single layer of Mo at a deposition rate in the range of 100 to 120 mA / sec to form a Mo thin film; And Forming the Mo thin film; etching the Mo thin film formed in the step of forming the Mo thin film. The method of claim 1, wherein the Mo thin film is formed by a single sheet. The method of claim 1, wherein a size of the target when forming the Mo thin film is in a range of 144 ± 10 × 660 ± 10 (mm × mm). The method of claim 1, wherein the etching step is performed using an etchant including phosphoric acid / nitric acid / acetic acid / stabilizer. The second gate by applying a first gate wiring layer and a power in the range of 12,000 to 16,000 Watts in the temperature range of 80 to 150 ° C., and depositing a single layer of Mo at a deposition rate in the range of 100 to 120 mA / sec. Forming a wiring layer; Etching the first and second gate wiring layers to form a gate pattern including a gate line, a gate line end, and a gate electrode; Stacking a gate insulating film on the gate pattern; Sequentially forming a semiconductor layer pattern and an ohmic contact layer pattern on the gate insulating layer; Forming and patterning a MoW thin film, a data line intersecting the gate line, an end of the data line connected to the data line, a source electrode connected to the data line and adjacent to the gate electrode, and the source electrode is aligned with respect to the gate electrode. Forming a data line including a drain electrode positioned on a side; Forming a protective film on the data line; Patterning the passivation layer together with the gate insulating layer to form contact holes exposing the gate line end, the data line end, and the drain electrode, respectively; Stacking a transparent conductive film to overlap the data line; And Etching the transparent conductive layer to form an auxiliary gate line end, an auxiliary data line end, and a pixel electrode connected to the gate line end, the data line end, and the drain electrode, respectively, of the thin film transistor substrate for a liquid crystal display device. Manufacturing method. The method of manufacturing a thin film transistor substrate for a liquid crystal display device according to claim 5, wherein the first gate wiring layer is an Al—Nd layer. The method of manufacturing a thin film transistor substrate for a liquid crystal display device according to claim 5, wherein the second gate wiring layer is formed in a single sheet type. The method of claim 5, wherein the etching is performed using an etchant including phosphoric acid / nitric acid / acetic acid / stabilizer. The second gate by applying a first gate wiring layer and a power in the range of 12,000 to 16,000 Watts in the temperature range of 80 to 150 ° C., and depositing a single layer of Mo at a deposition rate in the range of 100 to 120 mA / sec. Forming a wiring layer; Etching the first and second gate wiring layers to form a gate pattern including a gate line, a gate line end, and a gate electrode; Stacking a gate insulating film on the formed gate pattern; Sequentially stacking a semiconductor layer, an ohmic contact layer, and a conductive layer of MoW on the gate insulating film; Forming a photoresist pattern having a first portion, a second portion thicker than the first portion, and a third portion thinner than the first thickness; Forming a data line including a data line, an end of the data line connected to the data line, a data line including a source electrode and a drain electrode, and an ohmic contact layer pattern and a semiconductor layer pattern using the photoresist pattern; Forming a protective film on the data line; Patterning the passivation layer together with the gate insulating layer to form contact holes exposing the gate line end, the data line end, and the drain electrode, respectively; Stacking a transparent conductive film to overlap the data line; And Etching the transparent conductive layer to form an auxiliary gate line end, an auxiliary data line end, and a pixel electrode connected to the gate line end, the data line end, and the drain electrode, respectively; Method of preparation. The method of manufacturing a thin film transistor substrate for a liquid crystal display device according to claim 9, wherein the first gate wiring layer is an Al—Nd layer. The method of manufacturing a thin film transistor substrate for a liquid crystal display device according to claim 9, wherein the second gate wiring layer is formed in a single sheet type. The method of claim 9, wherein the etching is performed using an etchant including phosphoric acid / nitric acid / acetic acid / stabilizer. The thin film transistor of claim 9, wherein the first portion is formed to be positioned between the source electrode and the drain electrode, and the second portion is formed to be positioned above the data line. Method of manufacturing a substrate. Forming a data line including MoW data lines on the insulating substrate; Forming a color filter of red, green, and blue on the substrate; Depositing a buffer material to form a buffer layer covering the data line and the color filter; Applying a power in the range of 12,000 to 16,000 Watts in the first gate wiring layer and a temperature range of 80 ~ 150 ℃ over the buffer layer, and depositing a single layer made of Mo at a deposition rate of 100 ~ 120 Å / second Forming a gate wiring layer; Etching the first and second gate wiring layers to form a gate wiring including a gate line and a gate electrode; Forming a gate insulating film covering the gate wiring; Forming a island-like ohmic contact layer and a semiconductor layer pattern on the gate insulating film and forming a first contact hole exposing a portion of the data line corresponding to the gate insulating film and the buffer layer formed under the gate insulating film; A pixel including a source electrode and a drain electrode formed on the island-like ohmic contact layer pattern and then etched and separated from each other and formed of the same layer, and a pixel electrode connected to the drain electrode Forming a wiring; And removing the exposed portion of the ohmic contact layer pattern disposed between the source electrode and the drain electrode to separate the ohmic contact layer pattern on both sides.

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