[go: up one dir, main page]

KR20000003475A - Production method for memory device - Google Patents

Production method for memory device Download PDF

Info

Publication number
KR20000003475A
KR20000003475A KR1019980024717A KR19980024717A KR20000003475A KR 20000003475 A KR20000003475 A KR 20000003475A KR 1019980024717 A KR1019980024717 A KR 1019980024717A KR 19980024717 A KR19980024717 A KR 19980024717A KR 20000003475 A KR20000003475 A KR 20000003475A
Authority
KR
South Korea
Prior art keywords
logic
dram
mask
forming
nitrogen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1019980024717A
Other languages
Korean (ko)
Inventor
이정엽
이길호
Original Assignee
김영환
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업 주식회사 filed Critical 김영환
Priority to KR1019980024717A priority Critical patent/KR20000003475A/en
Publication of KR20000003475A publication Critical patent/KR20000003475A/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A production method for a semiconductor device is provided to form so a gate insulation film in a logic unit as to be thinner than a gate insulation film in the DRAM unit at producing an EML(Embedded Memory in Logic) device, and to be able to improve the characteristics of the gate isolation films of the DRAM unit and the logic unit. CONSTITUTION: The production method of the EML element having the DRAM unit and the logic unit comprises: a first step of forming a mask(23) to cover the DRAM unit and to open the logic unit on a semiconductor substrate(21); a second step of forming a nitric injection area in the lower part of surface of the semiconductor substrate of the logic unit; a third step of removing the mask and of operating an oxidation for forming a gate isolation film.

Description

메모리소자 제조방법Memory Device Manufacturing Method

본 발명은 반도체 제조 분야에 관한 것으로, 특히 EML(Embedded Memory in Logic) 소자의 게이트절연막 형성방법에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method of forming a gate insulating film of an embedded memory in logic (EML) device.

잘 알려진 바와 같이, EML 소자는 특정한 기능을 갖는 로직(logic)부와 DRAM부가 혼합된 소자이다. 이 소자를 이상적으로 구현하기 위해서는 고집적화(High density)된 DRAM와 고속(High speed)의 로직이 요구된다.As is well known, an EML device is a device in which a logic part and a DRAM part having a specific function are mixed. Ideally, the device will require high density DRAM and high speed logic.

따라서 로직부는 소자의 동작속도 향상을 위해 DRAM부보다 게이트절연막(통상 산화막을 적용한다)의 두께가 얇아야 한다.Therefore, in order to improve the operation speed of the device, the thickness of the gate insulating film (usually an oxide film is applied) should be smaller than that of the DRAM part.

도1a 내지 도1c에는 종래의 EML 소자의 게이트절연막 형성방법이 공정 순서에 따라 도시되어 있다.1A to 1C show a method of forming a gate insulating film of a conventional EML device according to a process sequence.

먼저, 도1a를 참조하면 기판(11) 상에 국부적으로 다수의 필드산화막(12)을 형성하고, 세정후 1차 게이트 산화(oxidation)을 실시하여 제1게이트산화막(13)을 형성한다.First, referring to FIG. 1A, a plurality of field oxide films 12 are locally formed on a substrate 11, and first gate oxidation is performed after cleaning to form a first gate oxide film 13.

이어서, 도1b에 도시된 바와 같이, DRAM부를 마스크(3)로 막은 뒤 습식식각하여 로직부의 상기 제1게이트산화막(13)을 제거한다.Subsequently, as shown in FIG. 1B, the DRAM portion is covered with a mask 3 and wet-etched to remove the first gate oxide layer 13 of the logic portion.

계속해서, 도1c 와 같이, DRAM부의 마스크(3)를 벗겨내고 세정 후 다시 2차 게이트산화를 실시하여 제2 게이트산화막(15)을 형성한다.Subsequently, as shown in Fig. 1C, the mask 3 of the DRAM portion is removed, and after the cleaning, secondary gate oxidation is performed again to form the second gate oxide film 15.

이렇게하여, DRAM부는 제1 및 제2 산화에 의해 형성된 상대적으로 두꺼운 게이트절연막(게이트산화막)을 가지게되며, 로직부는 제2산화에 의해 형성된 상대적으로 얇은 게이트절연막(게이트산화막)을 가지게 된다.In this way, the DRAM portion has a relatively thick gate insulating film (gate oxide film) formed by the first and second oxidation, and the logic portion has a relatively thin gate insulating film (gate oxide film) formed by the second oxidation.

그러나, 이러한 종래기술에서, DRAM부는 두 번의 산화공정에 의해 성장된 게이트산화막을 갖기 때문에 양질의 게이트산화막을 얻을 수 없게 된다.However, in this conventional technique, since the DRAM portion has a gate oxide film grown by two oxidation processes, it is impossible to obtain a high quality gate oxide film.

본 발명은 상기 문제점을 해결하기 위하여 안출된 것으로써, EML 소자를 제조함에 있어 로직부의 게이트절연막을 DRAM부의 게이트절연막 보다 얇게 형성하면서, DRAM부 및 로직부의 게이트절연막 특성을 개선할 수 있는 반도체소자 제조방법을 제공함을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in manufacturing an EML device, a semiconductor device fabrication capable of improving the gate insulating film characteristics of the DRAM section and the logic section while forming the gate insulating film of the logic section is thinner than the gate insulating film of the DRAM section. Its purpose is to provide a method.

도1a 내지 도1c는 종래기술에 따른 EML 소자의 게이트절연막 형성방법을 나타내는 공정 단면도.1A to 1C are cross-sectional views illustrating a method of forming a gate insulating film of an EML device according to the prior art.

도2a 내지 도2c는 본 발명의 일실시예에 따른 EML 소자의 게이트절연막 형성방법을 나타내는 공정 단면도.2A to 2C are cross-sectional views illustrating a method of forming a gate insulating film of an EML device according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

21 : 실리콘기판 22 : 필드산화막21 silicon substrate 22 field oxide film

23 : 마스크 24 : 질소주입영역23 mask 24 nitrogen injection region

25A, 25B : 게이트산화막25A, 25B: gate oxide film

상기 목적을 달성하기 위한 본 발명은, DRAM부와 로직부를 갖는 EML 소자 제조방법에 있어서, DRAM부는 덮고 로직부는 오픈시킨 마스크를 반도체기판상에 형성하는 제1단계: 상기 로직부의 반도체기판 표면 하부에 질소주입영역을 형성하는 제2단계; 및 상기 마스크를 제거하고, 게이트절연막 형성을 위한 산화를 실시하는 제3단계를 포함하여 이루어진다.In accordance with another aspect of the present invention, there is provided a method of manufacturing an EML device having a DRAM portion and a logic portion, the method comprising: forming a mask on a semiconductor substrate on which the DRAM portion is covered and the logic portion is opened: A second step of forming a nitrogen injection region; And a third step of removing the mask and performing oxidation to form a gate insulating film.

바람직하게, 상기 제3단계에서, 상기 마스크를 제거한 후 세정을 실시하는 단계를 더 포함할수 있으며, 상기 질소주입영역의 형성은 질소이온주입 또는 질소플라즈마처리로 실시할 수 있다.Preferably, in the third step, it may further comprise the step of performing a cleaning after removing the mask, the formation of the nitrogen injection region may be carried out by nitrogen ion injection or nitrogen plasma treatment.

본 발명에서, 질소주입영역을 갖는 로직부의 기판에서는 산화율(oxidation rate)이 감소하게 되어 로직부의 게이트산화막이 DRAM부의 게이트산화막보다 얇게 형성되며, DRAM부 및 로직부가 공히 한번의 산화공정에 의해 형성된 산화막을 가지기 때문에 각각 양질의 게이트산화막을 얻을 수 있다.In the present invention, in the substrate of the logic section having the nitrogen injection region, the oxidation rate is reduced, so that the gate oxide film of the logic section is thinner than the gate oxide film of the DRAM section, and the oxide film and the logic section are formed by one oxidation process. Since it is possible to obtain a high quality gate oxide film, respectively.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도2a 내지 도2c에는 본 발명의 일실시예에 따른 EML 소자의 게이트절연막 형성방법이 도시되어 있다.2A to 2C illustrate a method of forming a gate insulating film of an EML device according to an embodiment of the present invention.

먼저, 도2a는 필드산화막(22)이 형성된 기판(21) 상에서 DRAM부를 마스크(23)로 막고 로직부를 오픈시킨다.First, FIG. 2A blocks the DRAM part with a mask 23 on the substrate 21 on which the field oxide film 22 is formed and opens the logic part.

이어서, 도2b와 같이, 오픈된 로직부의 기판 표면 하부에 질소이온주입에 의한 질소주입영역(24)을 형성한다. 여기서의 질소이온주입 조건은 다음과 같다. 질소이온주입시 도펀트는 N+, N2 +를 사용할 수 있다. 도펀트로14N+사용할 때, 0.5∼10keV의 에너지에서 주입량은 5×1013∼5×1015ions/cm2으로 이온주입하고, 도펀트로28N2 +사용할 때, 1∼20keV의 에너지에서 주입량은 3×1013∼3×1015ions/cm2으로 이온주입한다.Next, as shown in FIG. 2B, a nitrogen injection region 24 by nitrogen ion implantation is formed under the substrate surface of the open logic unit. Here, nitrogen ion injection conditions are as follows. In the case of nitrogen ion implantation, the dopant may be N + , N 2 + . When using 14 N + as a dopant, the implantation is carried out at an energy of 0.5 to 10 keV at 5 × 10 13 to 5 × 10 15 ions / cm 2 , and at an energy of 1 to 20 keV when used as a dopant, 28 N 2 +. Silver is ion implanted at 3 × 10 13 to 3 × 10 15 ions / cm 2 .

이어서, 도2c에 도시된 바와 같이, DRAM부의 마스크(23)를 벗겨내고 세정을 실시한 뒤 게이트 산화를 실시하면, 질소주입영역(24)을 갖는 로직부의 기판에서는 산화율(oxidation rate)이 감소하게 되어 로직부의 게이트산화막(25B)가 DRAM부의게이트산화막(25A)보다 얇게 형성된다. 질소이온주입량이 많을수록 산화율은 더욱 감소하게 된다.Subsequently, as illustrated in FIG. 2C, when the mask 23 of the DRAM part is removed, and the gate oxidation is performed after the cleaning, the oxidation rate is reduced in the substrate of the logic part having the nitrogen injection region 24. The gate oxide film 25B of the logic section is formed thinner than the gate oxide film 25A of the DRAM section. The higher the nitrogen ion injection amount, the lower the oxidation rate.

한편, 게이트 산화전 세정은 로직부와 DRAM부의 기판 표면에 성장된 자연산화막을 제거하며 마스크 제거시 남을 수 있는 잔류물을 제거하기 위한 것으로서 HF계 습식식각이 포함되어야 한다.On the other hand, the gate pre-oxidation cleaning is to remove the natural oxide film grown on the substrate surface of the logic section and the DRAM section and to remove residues that may remain when the mask is removed. HF-based wet etching should be included.

이상에서, 설명한 바와 같이 본 발명은 한번의 게이트 산화 공정으로 로직부와 DRAM부에 각각 다른 두께의 게이트산화막을 형성한다. 이에 의해 게이트산화막의 균일성(uniformity)이 향상되므로 게이트산화막과 기판 간의 계면을 더욱 균일하게 되어 소자의 열화를 방지할 수 있다.As described above, the present invention forms a gate oxide film having different thicknesses in the logic unit and the DRAM unit in one gate oxidation process. As a result, the uniformity of the gate oxide film is improved, thereby making the interface between the gate oxide film and the substrate more uniform, thereby preventing deterioration of the device.

본 실시예에서는 질소이온주입에 의해 질소주입을 실시하였으나, 질소플라즈마처리에 의해서도 로직부의 반도체기판에 질소주입영역을 형성하는 것이 가능하다.In this embodiment, although nitrogen is injected by nitrogen ion injection, it is possible to form a nitrogen injection region on the semiconductor substrate of the logic portion by nitrogen plasma treatment.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명에서는 EML(Embedded Memory in Logic) 소자를 제조함에 있어, 한번의 산화공정으로 로직부와 DRAM부의 각 게이트산화막을 다른 두께로 형성할 수 있으므로, 게이트산화막의 균일성을 개선하여 소자의 열화를 방지하며, 또한, 종래공정에 비해 공정 스텝수를 줄여주므로써 작업처리량(throughput) 증대 효과를 가져다 준다.In the present invention, in fabricating an embedded memory in logic (EML) device, since the gate oxide films of the logic and DRAM sections can be formed in different thicknesses by one oxidation process, the uniformity of the gate oxide films can be improved to reduce the deterioration of the devices. In addition, compared with the conventional process, the number of process steps is reduced, thereby increasing the throughput.

Claims (7)

DRAM부와 로직부를 갖는 EML 소자 제조방법에 있어서,In the EML device manufacturing method having a DRAM section and a logic section, DRAM부는 덮고 로직부는 오픈시킨 마스크를 반도체기판상에 형성하는 제1단계:A first step of forming a mask on a semiconductor substrate that covers the DRAM portion and the logic portion is open: 상기 로직부의 반도체기판 표면 하부에 질소주입영역을 형성하는 제2단계; 및Forming a nitrogen injection region under the semiconductor substrate surface of the logic unit; And 상기 마스크를 제거하고, 게이트절연막 형성을 위한 산화를 실시하는 제3단계A third step of removing the mask and performing oxidation to form a gate insulating film 를 포함하여 이루어진 EML 소자 제조방법.EML device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 제3단계에서, 상기 마스크를 제거한 후 세정을 실시하는 단계를 더 포함하는 EML 소자 제조방법.In the third step, the EML device manufacturing method further comprising the step of performing a cleaning after removing the mask. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 제2단계는 질소이온주입에 의해 이루어지는 EML 소자 제조방법.The second step is an EML device manufacturing method made by nitrogen ion implantation. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 제2단계는 질소플라즈마처리에 의해 이루어지는 EML 소자 제조방법.The second step is an EML device manufacturing method made by nitrogen plasma treatment. 제2항에 있어서,The method of claim 2, 상기 질소이온주입시 도펀트는 N+또는 N2 +를 사용하는 EML 소자 제조방법.The dopant is N + or N 2 + when the nitrogen ion injection method of manufacturing an EML device. 제5항에 있어서,The method of claim 5, 도펀트로 상기 N+를 사용할 때, 이온주입은 0.5∼10keV의 에너지와 5×1013∼5×1015ions/cm2의 도즈로 실시하는 EML 소자 제조방법.When using N + as a dopant, ion implantation is performed with an energy of 0.5 to 10 keV and a dose of 5 × 10 13 to 5 × 10 15 ions / cm 2 . 제5항에 있어서,The method of claim 5, 도펀트로 상기 N2 +를 사용할 때, 이온주입은 1∼20keV의 에너지와 3×1013∼3×1015ions/cm2의 도즈로 실시하는 EML 소자 제조방법.When using N 2 + as a dopant, ion implantation is performed using an energy of 1 to 20 keV and a dose of 3 × 10 13 to 3 × 10 15 ions / cm 2 .
KR1019980024717A 1998-06-29 1998-06-29 Production method for memory device Ceased KR20000003475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019980024717A KR20000003475A (en) 1998-06-29 1998-06-29 Production method for memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980024717A KR20000003475A (en) 1998-06-29 1998-06-29 Production method for memory device

Publications (1)

Publication Number Publication Date
KR20000003475A true KR20000003475A (en) 2000-01-15

Family

ID=19541246

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980024717A Ceased KR20000003475A (en) 1998-06-29 1998-06-29 Production method for memory device

Country Status (1)

Country Link
KR (1) KR20000003475A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100660831B1 (en) * 2001-03-07 2006-12-26 삼성전자주식회사 Manufacturing Method of Mixed Semiconductor Device with Logic and DRAM
KR101002046B1 (en) * 2003-07-30 2010-12-17 매그나칩 반도체 유한회사 Manufacturing method of semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03145160A (en) * 1989-10-31 1991-06-20 Toshiba Corp Manufacture of semiconductor device
JPH03177064A (en) * 1989-12-06 1991-08-01 Toshiba Corp Manufacturing method of semiconductor device
KR0136935B1 (en) * 1994-04-21 1998-04-24 문정환 Method of manufacturing memory device
KR19990046998A (en) * 1997-12-02 1999-07-05 구본준 Gate oxide film formation method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03145160A (en) * 1989-10-31 1991-06-20 Toshiba Corp Manufacture of semiconductor device
JPH03177064A (en) * 1989-12-06 1991-08-01 Toshiba Corp Manufacturing method of semiconductor device
KR0136935B1 (en) * 1994-04-21 1998-04-24 문정환 Method of manufacturing memory device
KR19990046998A (en) * 1997-12-02 1999-07-05 구본준 Gate oxide film formation method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100660831B1 (en) * 2001-03-07 2006-12-26 삼성전자주식회사 Manufacturing Method of Mixed Semiconductor Device with Logic and DRAM
KR101002046B1 (en) * 2003-07-30 2010-12-17 매그나칩 반도체 유한회사 Manufacturing method of semiconductor device

Similar Documents

Publication Publication Date Title
KR100824947B1 (en) Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure
KR100195846B1 (en) Manufacturing Method of Semiconductor Device
KR100293453B1 (en) How to Form Dual Gate Oxide
KR20000003475A (en) Production method for memory device
KR100244402B1 (en) Method of forming a trench isolation in a semiconductor device
KR100223736B1 (en) Method of manufacturing semiconductor device
KR100451320B1 (en) Method for fabricating dual gate of semiconductor device
KR100649817B1 (en) Manufacturing method of semiconductor device
KR100469760B1 (en) Method for forming gate oxide of merged semiconductor device
KR100244413B1 (en) Method for forming source/drain of semiconductor device
KR100712984B1 (en) Device Separating Method of Semiconductor Device
KR100237023B1 (en) Field oxide film formation method of a semiconductor device
KR100356784B1 (en) Method for manufacturing cmos fet having micro line width
KR0166888B1 (en) Thin film transistor & its making method
KR100514516B1 (en) Method for fabricating dual gate insulator
KR100935245B1 (en) Method of Improving Uniformity of Interlayer Insulating Film Using Dummy Poly
KR20020066585A (en) Method for forming the bit line contact in semiconductor device
KR100307540B1 (en) Fabricating method of semiconductor device
KR20030050595A (en) Method of fabricating semiconductor device with dual gate oxide
KR20020054644A (en) Manufacturing method for semiconductor device
KR100422519B1 (en) Method for manufacturing of semiconductor device
KR100439191B1 (en) Method of making salicide contact
JP2004507110A (en) Manufacturing method for forming shallow insulating region in integrated circuit and integrated circuit formed by the manufacturing method
KR19990030770A (en) Composite semiconductor device having an asymmetric gate oxide film structure and manufacturing method thereof
KR20050066899A (en) Method for fabricating the gate oxide layer in semiconductor device

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19980629

A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19990712

Comment text: Request for Examination of Application

Patent event code: PA02011R01I

Patent event date: 19980629

Comment text: Patent Application

PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20010510

Patent event code: PE09021S01D

E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 20020125

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 20010510

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I