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KR100712984B1 - Device Separating Method of Semiconductor Device - Google Patents

Device Separating Method of Semiconductor Device Download PDF

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KR100712984B1
KR100712984B1 KR1020010045985A KR20010045985A KR100712984B1 KR 100712984 B1 KR100712984 B1 KR 100712984B1 KR 1020010045985 A KR1020010045985 A KR 1020010045985A KR 20010045985 A KR20010045985 A KR 20010045985A KR 100712984 B1 KR100712984 B1 KR 100712984B1
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insulating film
forming
trench
film
semiconductor substrate
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KR20030012112A (en
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조직호
김창일
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

절연막 형성시 플라즈마 처리에 의해 디싱(Dishing) 현상이 방지되도록 하는 반도체 소자의 소자분리막 형성방법은, 반도체 기판 위에, 소자분리영역을 노출시키는 제1 절연막을 형성하는 단계와, 반도체 기판에 트렌치를 형성하는 단계와, 트렌치를 제2 절연막으로 매립하는 단계와, 제2 절연막 표면에 플라즈마 처리를 수행하여 밀도가 강화된 산화막상의 플라즈마 처리영역을 형성하는 단계, 및 제2 절연막을 평탄화하는 단계를 포함하여 이루어진다.In the method of forming an isolation layer of a semiconductor device such that dishing is prevented by plasma treatment when forming the insulation layer, a method of forming an isolation layer on a semiconductor substrate may include forming a first insulation layer exposing an isolation region on a semiconductor substrate, and forming a trench in the semiconductor substrate. And filling the trench with a second insulating film, performing a plasma treatment on the surface of the second insulating film to form a plasma processing region on the oxide film having a high density, and planarizing the second insulating film. Is done.

반도체, 소자분리막, 플라즈마, 트렌치, STI, 디싱현상Semiconductor, Device Separator, Plasma, Trench, STI, Dicing

Description

반도체 소자의 소자분리막 형성방법{Method for forming device isolation layer in semiconductor device}Method for forming device isolation layer in semiconductor device

도 1 및 도 2는 종래의 반도체 소자의 소자분리막 형성방법을 설명하기 위한 공정 단면도이다.1 and 2 are cross-sectional views illustrating a method of forming a device isolation film of a conventional semiconductor device.

도 3 내지 도 7은 본 발명에 의한 반도체 소자의 소자분리막 형성방법의 일 실시예를 설명하기 위한 공정 단면도이다.3 to 7 are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

20 : 반도체 기판 22 : 절연막20 semiconductor substrate 22 insulating film

24 : 절연막 26, 28 : 플라즈마 처리영역24: insulating film 26, 28: plasma treatment region

본 발명은 반도체 소자의 제조방법에 관한 것으로, 상세하게는 트렌치 영역을 형성한 후 절연막으로 매립할 때 플라즈마 처리를 함으로써 CMP 공정시 디싱(Dishing) 현상이 방지되도록 하는 반도체 소자의 소자분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device in which a dishing process is prevented during a CMP process by forming a trench region and then performing plasma treatment when filling the insulating film. It is about.

반도체 소자 제조공정 중 얕은 트렌치 소자분리(Shallow Trench Isolation) 공정에서 고밀도 플라즈마(High Density Plasma)막을 증착한 후 STI CMP 공정을 수행할 때 심한 디싱현상으로 인해 후속 공정의 질화막 스트립(Strip) 공정까지 진행되었을 경우 소자분리 영역이 활성 영역보다 낮아지게 된다.High Density Plasma film is deposited in shallow trench isolation process during semiconductor device manufacturing process, and then proceeds to nitride film strip process of subsequent process due to severe dishing when performing STI CMP process In this case, the device isolation region is lower than the active region.

즉, 도 1 내지 도 2를 참조하면, 반도체 기판(10)에 절연막(12)을 형성한 후 패터닝하고, 이를 마스크로 반도체 기판을 식각하여 형성된 트렌치(14) 내에 절연막(16)을 증착한다. 그러면, 트렌치(14)의 상층에 형성되는 절연막(16) 부분에서 CMP 공정 후에 디싱현상이 발생된다. 이러한 디싱현상은 절연막(12)을 연마할 때에도 여전히 발생된다.1 to 2, the insulating film 12 is formed on the semiconductor substrate 10, and then patterned, and the insulating film 16 is deposited in the trench 14 formed by etching the semiconductor substrate with the mask. Then, dishing occurs after the CMP process in the portion of the insulating layer 16 formed on the upper layer of the trench 14. This dishing phenomenon still occurs even when the insulating film 12 is polished.

이로 인해 트랜지스터의 문턱전압(Threshold Voltage) 값이 변하게 되고 상기 문턱전압에 대한 게이트 값이 달라지므로 안정적인 디바이스를 제조하는 데 많은 어려움이 있다. 또한, 하나의 다이(Die) 내에서도 디싱현상에 의한 함몰 정도가 패턴의 밀도에 따라 변화가 심하므로 타겟 설정이 어렵게 된다. 현재 디바이스 구조에서는 후속의 고온 어닐링 공정시 에지(Edge) 부분에 대한 스트레스(Stress)가 집중되므로 실리콘의 마이크로 구조(Micro-Structure)의 변형으로 인하여 디펙트(Defect) 중 디스로케이션(Dislocation)이 발생된다.As a result, a threshold voltage value of the transistor is changed and a gate value of the threshold voltage is changed, thereby making it difficult to manufacture a stable device. In addition, even in one die, the degree of depression caused by dishing is severely changed depending on the density of the pattern, making it difficult to set a target. In the current device structure, stress on the edge part is concentrated during the subsequent high temperature annealing process, so dislocation during defect occurs due to deformation of the micro-structure of silicon. do.

그리고, STI 구조에서 기생 코너 트랜지스터(Parasitic Corner Transistor)로 인한 서브스레스홀드(Subthreshold) 전류를 효과적으로 방지하지 못하고 많은 접합 누설전류가 발생되고 있다.In addition, many junction leakage currents are generated without effectively preventing subthreshold currents caused by parasitic corner transistors in the STI structure.

종합적으로 볼 때 종래에는 첫째로, STI CMP 공정을 수행시 심한 디싱현상으로 인해 후속 공정의 질화막 스트립(Strip) 공정까지 진행되었을 경우 소자분리 영역이 활성 영역보다 낮아지게 되므로 트랜지스터의 문턱전압 값이 변하는 문제점이 있다. 둘째로, 하나의 다이 내에서도 디싱현상에 의한 함몰 정도가 패턴의 밀도에 따라 다르고 CMP에 대한 변동이 심하여 타겟 설정이 어렵다. 셋째로, CMP 공정시 균일도가 좋지 못하여 각 디바이스에서 불량 다이가 많이 발생되고 있다. 넷째로, 고밀도 플라즈마 절연막 증착 이후에 후속공정의 고온 어닐링 공정을 진행함에 따라 에지에 대한 스트레스가 집중되므로 실리콘의 마이크로 구조의 변형이 발생되며, 디스로케이션(Dislocation)이 발생되는데 이로 인한 많은 디펙트가 발생되었다. 마지막으로, 디싱으로 인하여 얕은 트렌치 소자분리 구조의 기생 코너 트랜지스터로 인하여 서브스레스홀드 전류를 효과적으로 제어할 수 없는 등의 문제점이 있었다.In general, first, when the STI CMP process is severely plated, the device isolation region becomes lower than the active region due to severe dishing. Therefore, the threshold voltage of the transistor is changed. There is a problem. Second, even in one die, the degree of depression caused by dishing depends on the density of the pattern and the variation of CMP is severe, making it difficult to set a target. Third, in the CMP process, uniformity is not good, and many defective dies are generated in each device. Fourthly, as the high temperature annealing process of the subsequent process is performed after the deposition of the high-density plasma insulating film, stress on the edge is concentrated, so that deformation of the microstructure of silicon occurs and dislocation occurs, resulting in many defects. Occurred. Lastly, due to dishing, there is a problem in that the subthreshold current cannot be effectively controlled due to the parasitic corner transistor of the shallow trench isolation structure.

상기한 바와 같은 문제점을 해결하기 위한 본 발명의 목적은, CMP공정시 디싱현상이 발생되지 않는 평탄한 소자분리막을 형성하기 위한 반도체 소자의 소자분리막 형성방법을 제공하는 것이다.An object of the present invention for solving the above problems is to provide a method for forming a device isolation film of a semiconductor device for forming a flat device isolation film does not occur dishing phenomenon during the CMP process.

본 발명의 다른 목적은, 마이크로 구조의 변형이나 디스로케이션 등의 디펙트 발생이 방지되도록 하는 소자분리막을 형성하기 위한 반도체 소자의 소자분리막 형성방법을 제공하는 것이다.Another object of the present invention is to provide a method for forming a device isolation film of a semiconductor device for forming a device isolation film to prevent defects such as deformation and dislocation of microstructures.

상기 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 소자분리막 형성방법은, 반도체 기판 위에, 소자분리영역을 노출시키는 제1 절연막을 형성하는 단계와, 상기 반도체 기판에 트렌치를 형성하는 단계와, 상기 트렌치를 제2 절연막으로 매립하는 단계와, 상기 제2 절연막 표면에 플라즈마 처리를 수행하여 밀도가 강화된 산화막상의 플라즈마 처리영역을 형성하는 단계, 및 상기 제2 절연막을 평탄화하는 단계를 포함하는 것을 특징으로 한다.
상기 트렌치를 제2 절연막으로 매립하는 단계는, 상기 트렌치의 일부가 매립되도록 제2 절연막을 증착하는 단계와, 증착된 상기 제2 절연막의 표면을 플라즈마 처리하는 단계와, 상기 트렌치의 나머지 부분이 매립되도록 제2 절연막을 증착하는 단계를 포함할 수 있다.
상기 제2 절연막은 TEOS, HDP, SOG, O3-USG 중 어느 하나일 수 있다.
상기 제2 절연막 표면에 플라즈마 처리를 수행하는 단계에서, O2, N2O, NO, Ar 가스나 그 혼합물 중 어느 하나를 사용할 수 있다.According to an aspect of the present invention, there is provided a method of forming a device isolation film of a semiconductor device, the method including: forming a first insulating film exposing a device isolation region on a semiconductor substrate, forming a trench in the semiconductor substrate; Embedding the trench with a second insulating film, performing a plasma treatment on the surface of the second insulating film to form a plasma processing region on the oxide film having a high density, and planarizing the second insulating film. It is done.
The filling of the trench with a second insulating film may include depositing a second insulating film to fill a portion of the trench, plasma treating a surface of the deposited second insulating film, and filling the remaining portion of the trench. And depositing a second insulating film to make it possible.
The second insulating layer may be any one of TEOS, HDP, SOG, and O3-USG.
In the step of performing a plasma treatment on the surface of the second insulating film, any one of O 2, N 2 O, NO, Ar gas, or a mixture thereof may be used.

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이하, 본 발명의 실시예에 대한 설명은 첨부된 도면을 참조하여 더욱 상세하게 설명한다. 아래의 실시예는 본 발명의 기술적 사상을 반영하는 하나의 예에 불과한 것으로서, 이로부터 얼마든지 변경, 변형 및 수정이 가능함은 본 발명의 기술분야에서 통상의 지식을 가진 자에게 있어서 명백한 것이다.Hereinafter, an embodiment of the present invention will be described in more detail with reference to the accompanying drawings. The following embodiments are only examples reflecting the technical idea of the present invention, and it is apparent to those skilled in the art that modifications, variations, and modifications can be made therefrom.

도 3 내지 도 7을 참조하여 본 발명에 의한 반도체 소자의 소자분리막 형성방법의 실시예를 상세하게 설명한다.An embodiment of a method of forming a device isolation film of a semiconductor device according to the present invention will be described in detail with reference to FIGS. 3 to 7.

먼저, 도 3을 참조하면, 반도체 기판(20) 위에 질화막 등의 절연막(22)을 증착한 후, 절연막 위에 포토레지스트 패턴을 형성한다. 이 절연막(22)을 식각하여 트렌치 형성을 위한 마스크를 형성하고, 반도체 기판(20)을 식각하여 소자분리 영역을 형성하기 위한 트렌치를 형성한다.First, referring to FIG. 3, an insulating film 22 such as a nitride film is deposited on the semiconductor substrate 20, and then a photoresist pattern is formed on the insulating film. The insulating layer 22 is etched to form a mask for forming a trench, and the semiconductor substrate 20 is etched to form a trench for forming an isolation region.

다음, 트렌치가 형성된 반도체 기판(20) 위의 전면에 걸쳐서 고밀도 플라즈마 공정을 실시한다. 이 경우 도 4a 및 도 4b와 같이 여러번으로 나누어서 공정을 진행하거나, 도 5와 같이 한 번의 공정으로 소자분리용 절연막(24)을 형성할 수 있다.Next, a high density plasma process is performed over the entire surface of the trenched semiconductor substrate 20. In this case, the process may be divided into several times as illustrated in FIGS. 4A and 4B, or the insulating film 24 for device isolation may be formed in one process as illustrated in FIG. 5.

도 4a를 참조하면, 6000Å 두께로 막질을 증착하고자 하는 경우, 상기 두께 형성을 위해 3000 내지 4000Å 두께로 고밀도 플라즈마 공정이 반도체 기판(20)의 전면에 실시된 예이다. 절반 정도 높이로 상기 고밀도 플라즈마 공정이 실시된 후에 산소(O2) 플라즈마 처리를 하면 플라즈마 처리영역(26)이 형성되고, 고밀도 플라즈마 막의 벌크(Bulk) 내에 산화막이 형성되는 동안 막질의 밀도가 증가된다. 상기 산소 플라즈마 처리시의 챔버내부의 압력은 1 내지 20 Torr 정도로 유지하고, 플라즈마 전력은 1 내지 4㎾, 바이어스 전력은 1 내지 3㎾로 유지하는 것이 바람직하다. 이렇게 하는 것은 이후에 진행되는 CMP 공정시 단차가 낮은 부분이 제거되는 비율을 낮추어 줌으로써 디싱현상이 방지되도록 하기 위함이다.Referring to FIG. 4A, when the film quality is to be deposited to 6000 mW, a high density plasma process is performed on the entire surface of the semiconductor substrate 20 to a thickness of 3000 to 4000 mW to form the thickness. When the oxygen (O2) plasma treatment is performed after the high density plasma process is performed at about half the height, the plasma treatment region 26 is formed, and the density of the film quality is increased while the oxide film is formed in the bulk of the high density plasma film. The pressure inside the chamber during the oxygen plasma treatment is preferably maintained at about 1 to 20 Torr, the plasma power at 1 to 4 kW, and the bias power at 1 to 3 kPa. This is to prevent dishing by lowering the rate at which the low step portion is removed in a subsequent CMP process.

도 4b를 참조하면, 일차적인 산소 플라즈마 처리후 2차로 고밀도 플라즈마에 의해 최종적으로 원하는 6000Å 두께로 절연막(24)이 형성되는 예를 보여준다. 이와 같이 형성된 절연막(24)은 다시 산소 플라즈마 처리에 의해 플라즈마 처리영역(28)이 형성되며, 그 결과 막질의 밀도가 높아지게 된다.Referring to FIG. 4B, an example in which the insulating film 24 is finally formed to a desired thickness of 6000 Å by the second high-density plasma after the first oxygen plasma treatment is shown. The insulating film 24 thus formed is again formed by the plasma treatment region 28 by oxygen plasma treatment, resulting in a high film density.

도 5를 참조하면, 도 4a 및 도 4b와는 달리, 절연막(24)을 여러 번에 걸쳐 나누어서 형성하지 않고 단일공정에 의해 6000Å으로 형성한 예이다. 이 예에서도 산소 플라즈마 처리를 하여 플라즈마 처리영역(28)이 형성되도록 한다.Referring to FIG. 5, unlike FIG. 4A and FIG. 4B, the insulating film 24 is formed by 6000 mV in a single process without being divided into several times. In this example, the plasma treatment region 28 is formed by performing oxygen plasma treatment.

상기한 도 4a, 도 4b 및 도 5의 예에서 형성된 플라즈마 처리영역들(26, 28)은 절연막(24)이 반도체 기판 전면에 가해지는 강한 압축 스트레스(Compressive Stress)에 의해 반도체 기판이 휘게 되는 워페이지(Warpage)를 감소시킬 수 있다. 상기한 절연막(24)은 절연용 산화막으로 TEOS, HDP, SOG, O3-USG가 사용될 수 있다. 그리고, 플라즈마 처리영역들(26, 28)은 처리가스로서 산소 외에 N2O, NO, Ar가스나 이들의 혼합물을 사용할 수 있다.The plasma processing regions 26 and 28 formed in the examples of FIGS. 4A, 4B, and 5 described above are used to warp the semiconductor substrate due to the strong compressive stress applied to the entire surface of the semiconductor substrate. You can reduce the page (Warpage). As the insulating layer 24, TEOS, HDP, SOG, and O3-USG may be used as the insulating oxide layer. The plasma processing regions 26 and 28 may use N 2 O, NO, Ar gas, or a mixture thereof in addition to oxygen as the processing gas.

도 6을 참조하면, 절연막(24)이 형성된 후 CMP 공정이 중간정도 실시된 후의 웨이퍼의 단면이 도시되어 있다. 이 경우 어느 정도의 디싱현상이 발생된다. 그러나, CMP 공정이 원하는 두께로 진행이 완료되면, 도 7과 같이, 디싱현상이 발생되지 않고 평평한 반도체 기판이 단면이 얻어지는 것을 볼 수 있다.Referring to FIG. 6, there is shown a cross section of the wafer after the CMP process has been performed intermediately after the insulating film 24 is formed. In this case, some dishing phenomenon occurs. However, when the CMP process proceeds to the desired thickness, as shown in FIG. 7, it is seen that dishing does not occur and a cross section of a flat semiconductor substrate is obtained.

이와 같이, 본 발명의 실시예에 의하면, 트렌치 형성후 소자분리용 절연막 형성시 고밀도의 절연막을 형성할 수 있으며, 그에 따라 막질의 밀도가 증가되어 단차가 낮은 부분의 제거율이 낮아지므로 표면연마에 의한 디싱현상이 방지되는 이점이 있다.As described above, according to the embodiment of the present invention, a high-density insulating film can be formed when forming the insulating film for device isolation after forming the trench, and as a result, the density of the film is increased and the removal rate of the low step is lowered. There is an advantage that dishing phenomenon is prevented.

본 발명에 의하면, 고밀도 플라즈마 공정진행시 소자분리용 절연막이 형성되는 부분에 절연특성이 개선되고, 막질의 밀도가 증가되어서 단차가 낮은 부분의 제거율이 낮아지므로 디싱현상에 의한 디바이스의 손상을 감소시키는 효과가 있다. 즉, 트렌치가 형성된 소자분리 영역을 CMP할 때 토폴로지(Topology)가 낮은 영역의 제거율이 낮으므로 패턴의 균일도가 향상되는 효과가 있다. 그리고, 마이크로 구조의 변형이나 디스로케이션 및 워페이지 등의 디펙트 발생이 방지되는 효과가 있다.According to the present invention, the insulating property is improved in the portion where the device isolation insulating film is formed during the high density plasma process, and the density of the film is increased, so that the removal rate of the low step is lowered, thereby reducing damage to the device due to dishing. It works. That is, when the CMP of the device isolation region where the trench is formed, the removal rate of the region having a low topology is low, thereby improving the uniformity of the pattern. In addition, there is an effect that deformation of microstructures, defects such as dislocations and warpages can be prevented.

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Claims (4)

반도체 기판 위에, 소자분리영역을 노출시키는 제1 절연막을 형성하는 단계;Forming a first insulating film exposing the device isolation region on the semiconductor substrate; 상기 반도체 기판에 트렌치를 형성하는 단계;Forming a trench in the semiconductor substrate; 상기 트렌치를 제2 절연막으로 매립하는 단계;Filling the trench with a second insulating film; 상기 제2 절연막 표면에 플라즈마 처리를 수행하여 밀도가 강화된 산화막상의 플라즈마 처리영역을 형성하는 단계; 및Performing a plasma treatment on the surface of the second insulating film to form a plasma processing region on an oxide film having a high density; And 상기 제2 절연막을 평탄화하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.And planarizing the second insulating film. 제1항에 있어서,The method of claim 1, 상기 트렌치를 제2 절연막으로 매립하는 단계는,Filling the trench with a second insulating film, 상기 트렌치의 일부가 매립되도록 제2 절연막을 증착하는 단계와,Depositing a second insulating film to fill a portion of the trench; 증착된 상기 제2 절연막의 표면을 플라즈마 처리하는 단계와,Plasma treating the deposited surface of the second insulating film; 상기 트렌치의 나머지 부분이 매립되도록 제2 절연막을 증착하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.And depositing a second insulating film to fill the remaining portion of the trench. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 제2 절연막은 TEOS, HDP, SOG, O3-USG 중 어느 하나인 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.And the second insulating film is one of TEOS, HDP, SOG, and O3-USG. 제1항에 있어서,The method of claim 1, 상기 제2 절연막 표면에 플라즈마 처리를 수행하는 단계에서,In the step of performing a plasma treatment on the surface of the second insulating film, O2, N2O, NO, Ar 가스나 그 혼합물 중 어느 하나를 사용하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.A method for forming a device isolation film for a semiconductor device, using any one of O 2, N 2 O, NO, Ar gas, and mixtures thereof.
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KR0179554B1 (en) * 1995-11-30 1999-04-15 김주용 Device isolation insulating film formation method of semiconductor device
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