KR101265675B1 - High aperture ratio Liquid Crystal Display Device and the method for fabricating thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high aperture liquid crystal display device, and more particularly, to manufacturing a high quality flat panel display device by manufacturing a flattening panel having no wiring step difference.

To this end, in a bottom-gate type liquid crystal display array substrate having a gate wiring having a lower structure, a transparent organic film layer is formed in advance before forming a gate wiring and an electrode on the substrate. A portion of the organic layer is removed to form a bone. Next, when the gate electrode and the wiring are formed along the valleys of the organic layer, the step difference due to the wiring does not occur.

In addition, such a configuration can reduce the width of the wiring to maximize the opening ratio in the step of forming the wiring, and if the buried altitude of the wiring is sufficiently secured in response to the reduced width, a large area Problems such as signal delay in a liquid crystal display device can be solved.

Description

High aperture ratio liquid crystal display device and the method for fabricating

1 is a plan view showing a unit pixel of a conventional liquid crystal display device.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1. FIG.

3 is a schematic cross-sectional view taken along line III-III of FIG. 1;

4 is a plan view illustrating a unit pixel for a liquid crystal display according to a first exemplary embodiment of the present invention.

5A to 5H are cross-sectional views taken along the line VV of FIG. 4.

FIG. 6 is a schematic cross-sectional view taken along line VI-VI of FIG. 4. FIG.

7 is a plan view illustrating a unit pixel for a liquid crystal display according to a second exemplary embodiment of the present invention.

8 is a cross-sectional view taken along the line VII-VII of FIG. 7.

Description of the Related Art [0002]

100 substrate 115 transparent organic film layer

120: gate wiring 125: gate insulating film

132: source electrode 134: drain electrode

136: gate electrode 145, 146: pure and impurity amorphous silicon layer

150 pixel electrode 155 protective film

160: storage electrode CH2: drain contact hole

CH3: Storage Contact Hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high aperture liquid crystal display device, and more particularly, to manufacturing a high quality flat panel display device by manufacturing a flattening panel having no wiring step difference.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of the molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

In addition, the liquid crystal display includes a color filter substrate on which a common electrode is formed, an array substrate on which a pixel electrode is formed, and a liquid crystal filled between the two substrates. It is driven by the system and has excellent characteristics such as transmittance and aperture ratio.

Hereinafter, a conventional liquid crystal display device will be described with reference to the accompanying drawings.

1 is a plan view illustrating a unit pixel of a conventional liquid crystal display, and FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1, and will be described with reference to FIGS. 1 and 2.

As illustrated, the gate wiring 20 and the gate electrode 36 extending from the gate wiring 20 are formed on one side of the substrate 10.

A gate insulating film 25 is formed on the entire upper surface of the substrate 10 on which the gate wirings and the electrodes 20 and 36 are formed, and a pure amorphous silicon layer 45 and an impurity amorphous silicon layer 46 are formed on the gate insulating film 25. ) Is laminated.

A data line 30 on the pure and impurity amorphous silicon layers 45 and 46 and perpendicularly intersects the gate line 20 to define the pixel region P, and a source electrode extending from the data line 30. 32 and a drain electrode 34 spaced apart from each other are formed.

Here, the impurity amorphous silicon layer 46 positioned in the interval between the source and drain electrodes 32 and 34 is removed to expose the pure amorphous silicon layer 45.

The passivation layer 55 is formed on the entire upper surface of the substrate 10 on which the source and drain electrodes 32 and 34 are formed, and the drain is formed through the drain contact hole CH1 exposing a portion of the drain electrode 34. The electrode 34 is in contact with the pixel electrode 50.

However, in the conventional liquid crystal display device, a liquid crystal alignment non-uniformity region is generated due to the step difference of the wirings in the process of forming the array wirings, which will be described in detail with reference to FIG. 3.

FIG. 3 is a schematic cross-sectional view taken along the line III-III of FIG. 1 and simultaneously shows an array substrate and a color filter substrate.

As shown, the color filter substrate as the upper substrate 60 and the array substrate as the lower substrate 65 face each other, and the liquid crystal layer 80 is interposed between the upper and lower substrates 60 and 65.

In this case, a gate wiring 90 is formed on one surface of the transparent substrate 62 of the array substrate 65, and a gate insulating film and a protective film 95 of a transparent material are formed on the entire upper surface of the gate wiring 90. And pixel electrodes 83 on both sides adjacent to the gate line 90 as an upper portion of the passivation layer 95.

In addition, a black matrix 70 for blocking the non-display area is formed on one surface of the transparent substrate 61 of the color filter substrate 60 to correspond to the boundary area for each color, and the red, green, and blue color filters are applied to the display area. 75 is sequentially configured.

In addition, a common electrode 93 made of a transparent conductive metal is formed on the entire upper surface of the color filter 75 so that the vertical electrode is vertically caught between the common electrode 93 and the pixel electrode 83 formed on the array substrate 65. The liquid crystal 85 is driven by the electric field, and the non-pixel region except for the pixel electrode 83 is shielded by the black matrix 70.

However, in the conventional liquid crystal display, when the gate wiring 90 is formed on the upper surface of the transparent glass substrate 62, the side step inevitably occurs due to the thickness of the gate wiring 90.

Accordingly, the liquid crystal alignment non-uniformity region is generated at both sides of the gate wiring 90, which causes light leakage region.

In order to shield the light leakage region described above, the method of mainly blocking the light leakage region by sufficiently securing the width of the black matrix 70 is used. However, such a configuration has increased the width of the black matrix 70. This resulted in a reduction of the opening area.

In particular, large TV products in the 40 to 50-inch range have increased the size of the panel, and the wiring width has been widened to the level of 40 to 50 μm in response to problems such as signal delay.

In this case, it is possible to cope with the structure of increasing the opening ratio by increasing the thickness of the wiring to reduce the width of the wiring. It caused a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to manufacture a high-aperture rate liquid crystal display device by manufacturing a flattening panel in which wiring steps do not occur.

To this end, the transparent organic film layer is formed in advance before forming the electrode and the wiring on the substrate, and after forming the bone in the organic film layer, it is characterized in that the electrode and the wiring is formed on the bone.

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, the method including preparing a substrate, defining a switching region, a gate region, a data region, and a pixel region on the substrate; Forming a transparent organic film layer on the trench, and forming a valley having a predetermined depth in the transparent organic film layer corresponding to the gate region;

Coating a conductive metal along a valley formed in the organic layer, forming a gate wiring and a gate electrode in one direction by etching the conductive metal, and on the entire upper surface of the substrate on which the gate electrode and the gate wiring are formed Forming a gate insulating film;

Sequentially forming a pure and impurity amorphous silicon layer on the gate insulating film, a data line corresponding to the data region on the pure and impurity amorphous silicon layer, a source electrode extending from the data line, and the source electrode Forming a drain electrode spaced apart from the gap;

Forming a passivation layer on the entire upper surface of the substrate on which the source and drain electrodes and the data wiring are formed, and forming a pixel electrode in contact with the drain electrode corresponding to the pixel region through a drain contact hole exposing a portion of the drain electrode; Characterized in that it comprises a step.

In this case, the width of the gate wiring is in a range of 1 to 10 μm, and its buried altitude is in a range of 1 to 50 μm.

The conductive metal may be a copper paste or a silver paste, and the thin film transistor may include the gate electrode, the pure and impurity amorphous silicon layers, and the source and drain electrodes.

And a storage electrode formed of the same material as the data line and partially contacting the gate line, wherein the storage electrode is in contact with the pixel electrode.

A storage capacitor is formed using a portion of the gate wiring as a first electrode and the storage electrode as a second electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, including preparing a substrate, defining a switching region, a gate region, a data region, and a pixel region on the substrate; Forming a transparent organic layer on the entire upper surface of the substrate;

Forming a valley having a predetermined depth in the transparent organic layer corresponding to the gate region, applying a conductive metal along the valley formed in the organic layer, etching the conductive metal, and forming a gate wiring in one direction; Forming a gate electrode;

Forming a gate insulating film on the entire upper surface of the substrate on which the gate electrode and the gate wiring are formed, sequentially forming a pure and impurity amorphous silicon layer on the gate insulating film, and forming the data region on the pure and impurity amorphous silicon layer Forming a valley by removing a portion of the gate insulating layer corresponding to the gate insulating layer and a portion of the organic layer below;

Forming a data line along the valley corresponding to the data area, a source electrode extending from the data line, a drain electrode spaced apart from the source electrode, and an upper portion of the substrate on which the source and drain electrodes and the data line are formed; Forming a protective layer on the entire surface, and forming a pixel electrode in contact with the drain electrode corresponding to the pixel region through a drain contact hole exposing a portion of the drain electrode.

In this case, a buried structure is formed at the same time as the data line and includes a storage electrode in contact with the pixel electrode at a position overlapping the gate line.

A storage capacitor having a portion of the gate wiring as the first electrode and the storage electrode as the second electrode is formed, and the first electrode and the second electrode are perpendicular to the substrate. It features.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes: a substrate, a transparent organic film layer formed on the substrate, a gate wiring formed in a buried structure on the organic film layer, and a gate electrode connected to the gate wiring;

A gate insulating film formed on the gate electrode and the gate wiring, a pure and impurity amorphous silicon layer formed in an island shape on the gate insulating film, and a data line perpendicularly intersecting the gate wiring on the pure and impurity amorphous silicon layer. A source electrode extending from the data line and a drain electrode spaced apart from the source electrode;

And a pixel electrode configured to contact the drain electrode through a passivation layer formed on the source and drain electrodes and the data line, and a drain contact hole exposing a portion of the drain electrode.

The gate electrode and the gate wiring may include at least one selected from a copper paste or a silver paste, and include the gate electrode, a pure and impurity amorphous silicon layer, and a source and a drain electrode. Configure a thin film transistor.

The storage electrode may include a storage electrode formed of the same material as the data line and configured to contact the pixel electrode at a position partially overlapping the gate line.

A storage capacitor includes a portion of the gate wiring as a first electrode and a storage electrode as a second electrode, the data wiring and the storage electrode have a buried structure, and the first electrode and the first electrode The second electrode is characterized in that it is perpendicular to the substrate.

Hereinafter, a liquid crystal display according to the present invention will be described with reference to the accompanying drawings.

--- First Embodiment ---

4 is a plan view illustrating a unit pixel of a liquid crystal display according to a first exemplary embodiment of the present invention, and FIGS. 5A to 5H are cross-sectional views taken along the line VV of FIG. 4, and FIGS. 4 and 5H. It demonstrates with reference to.

As illustrated, a transparent organic film layer 115 is formed on the entire upper surface of the transparent substrate 100, and a portion of the transparent organic film layer 115 is removed to form a valley (not shown) of a buried structure. Next, the gate line 120 and the gate electrode 136 extending from the gate line 120 are formed in one direction along the valley (not shown).

A gate insulating layer 125 is formed on the entire upper surface of the substrate 100 on which the gate electrode 136 and the like are formed. In the upper portion of the gate insulating layer 125, a portion of the gate electrode 136 overlaps with a portion of the gate electrode 136 and is in an amorphous state. The silicon layer 145 and the impurity amorphous silicon layer 146 are laminated.

A data line 130 on the pure and impurity amorphous silicon layers 145 and 146 that vertically intersect the gate line 120 to define a pixel region P and an extension of the data line 130. The source electrode 132 and the drain electrode 134 spaced apart from each other are formed.

After forming a passivation layer 155 for protecting the upper surfaces of the source and drain electrodes 132 and 134, the drain electrode 134 is formed through the drain contact hole CH2 exposing a part of the drain electrode 134. And the pixel electrode 150 in contact with the pixel region P are configured to correspond to the pixel region P. FIG.

In addition, an upper pixel electrode 150 of the pixel region P is connected to a lower storage electrode 160 and between the storage electrode 160 and the adjacent front gate line 120 and therebetween. The storage capacitor Cst may be configured to include the interposed gate insulating layer 125.

Characteristic in the above-described configuration is that before forming the gate electrode and wiring on the substrate, the transparent organic film layer is formed in advance, and after forming a valley in a portion corresponding to the gate region in the organic film layer, the valley of the organic film layer is Therefore, the gate electrode and the wiring are formed. In this way, since the wiring and the electrode are formed in a buried structure, a stepless structure in which no step is generated by the array wiring can be realized.

In addition, such a configuration can eliminate the light leakage region due to the step difference of the wiring, thereby making it possible to manufacture a liquid crystal display device of high display quality by expanding the opening region.

Hereinafter, a method of manufacturing a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

5A through 5H are cross-sectional views taken along the line VV of FIG. 4 and will be described with reference to the drawings.

As shown in FIG. 5A, the step of defining the switching region S, the gate region G, the data region D, and the pixel region P on the substrate 100 is performed. Next, the transparent organic film layer 115 is formed on the entire upper surface of the substrate 100.

As shown in FIG. 5B, a negative type photosensitive layer 170 is coated on the entire upper surface of the substrate 100 on which the transparent organic layer 115 is formed, and then spaced apart from the substrate 100. The blocking part TB is formed in correspondence with the low gate area G, and the masks M formed of the transmissive part TB are aligned in the areas S, D, and P except this.

As shown in FIG. 5C, when the exposure process of irradiating light to the photosensitive layer 170 and the developing process of removing it by using a developer are performed on the mask M, the transmissive part TA corresponds to the transmission part TA. The photosensitive layer 170 remains as it is, the photosensitive layer 170 corresponding to the blocking part TB is completely removed, and the transparent organic layer 115 corresponding to the lower portion thereof is exposed.

Next, the transparent organic film layer 115 exposed to the blocking part TB is etched using the photosensitive layer 170 left in correspondence with the transmission part TA as an etching mask.

As shown in FIG. 5D, when the above-described etching process is performed, valleys 165 from which a portion of the organic layer 115 corresponding to the gate region G is removed are formed. Next, the photosensitive layer (170 of FIG. 5C) left corresponding to the transmission part TA is removed through a strip process.

Next, as shown in FIG. 5E, one selected from the group of conductive metals capable of being soluble along the valley 165 of FIG. 5D corresponds to the gate region G and the gate wiring 120. The gate electrode 136 is formed.

In this case, the gate wirings and the electrodes 120 and 136 are, for example, an ink-jet printing method or a spin coating method on the substrate 100 on which the valleys 165 of FIG. 5D are formed. After applying the conductive metal capable of solving to the entire surface of the substrate 100, and removing the conductive metal by dry etching, the gate of the buried structure along the shape of the valley (165 in Figure 5d) Wiring and electrodes 120 and 136 may be formed.

Here, the material used as the conductive metal may be, for example, copper paste or silver paste. In this case, a part of the gate wiring 120 may be partially replaced by the first electrode of the storage capacitor Cst. Can be used as

Therefore, as in the present invention, a portion of the organic layer (115 in FIG. 5D) is removed to form a valley (165 in FIG. 5D), and then gate gates and electrodes 120 and 136 are formed along the valley. As a result, a planarization structure in which a step with a wiring formed thereafter does not occur may be realized, thereby minimizing generation of light leakage regions.

In addition, when designing the width W of the gate wirings and the electrodes 120 and 136, the width W is reduced to secure an aperture ratio, and to prevent signal delay due to the reduction of the width W. If the buried altitude (D) of the gate wiring and the electrodes 120 and 136 is further increased, a sufficient area can be secured, thereby improving problems such as signal delay in a large area liquid crystal display panel.

As shown in FIG. 5F, the gate insulating layer is selected from a group of inorganic insulating materials such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) on the entire upper surface of the substrate 100 on which the gate wiring and the electrodes 120 and 136 are formed. After forming 125, a pure amorphous silicon layer and an impurity amorphous silicon layer are sequentially formed on the gate insulating layer 125, and then patterned to form island-like pure and impurity amorphous silicon layers 145 and 146. .

As shown in FIG. 5G, selected from among aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), and tungsten (W) on the substrate 100 on which the pure and impurity amorphous silicon layers 145 and 146 are formed. One or more layers are deposited and patterned to form data lines (130 in FIG. 4) and source and drain electrodes 132 and 134 corresponding to the data region D, and at the same time An island-shaped storage electrode 160 overlapping a portion of the gate line 120 is formed.

In this case, the source electrode 132 is formed in the form extending from the data line (130 of FIG. 4), and the drain electrode 134 is spaced apart from the source electrode 132, and the source electrode 132 and The pure amorphous silicon layer 145 is exposed by removing the impurity amorphous silicon layer 146 located in the interval between the drain electrodes 134.

Therefore, as described above, a storage capacitor Cst may be configured using the gate wiring 120 as the first electrode and the storage electrode 160 as the second electrode.

Next, the passivation layer 155 is formed of one selected from the group of inorganic insulating materials such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) on the upper surface of the substrate 100 on which the source and drain electrodes 132 and 134 are formed. do.

As illustrated in FIG. 5H, the drain contact hole CH2 exposing a part of the drain electrode 134 and the storage contact exposing a part of the storage electrode 160 are exposed on the substrate 100 on which the passivation layer 155 is formed. After the hole CH3 is formed, the pixel electrode 150 which contacts the drain electrode 134 and the storage electrode 160 through the drain contact hole CH2 and the storage contact hole CH3 is formed in the pixel region ( It forms corresponding to P).

The pixel electrode 150 may be formed of one selected from a group of transparent conductive metals such as indium tin oxide (ITO) or indium zinc oxide (IZO).

As described above, the liquid crystal display device according to the present invention can be manufactured through the above-described process.

FIG. 6 is a schematic cross-sectional view taken along line VI-VI of FIG. 4, and will be described in detail with reference to this. FIG.

As illustrated, the color filter substrate, which is the upper substrate 210, and the array substrate, which is the lower substrate 220, face each other, and the liquid crystal layer 230 is interposed between the upper and lower substrates 210 and 220.

A transparent organic film layer 265 is formed on one surface of the transparent substrate 201 of the array substrate 220, and the gate wiring 260 is formed along a valley of an organic film pattern (not shown) from which a portion of the transparent organic film layer 265 is removed. ) Is configured. The gate insulating film and the passivation layer 270 are sequentially formed on the entire upper surface of the gate wiring 260, and the pixel electrodes 290 on both sides of the gate insulating layer and the passivation layer 270 are adjacent to each other with the gate wiring 260 as a boundary portion. Are each configured.

As in the present invention, when the gate wiring 260 is formed in a buried structure, a step with the wiring formed thereafter does not occur, and the planarization effect can be maximized.

On one surface of the transparent substrate 200 of the color filter substrate 210, a black matrix 240 for blocking a non-display area is configured to correspond to a boundary area for each color, and red, green, and blue color filters correspond to the display area. 250 is configured sequentially.

In addition, a common electrode 280 made of a transparent conductive metal is formed on the entire upper surface of the color filter 250, and the liquid crystal 255 is formed by a vertical electric field applied up and down between the common electrode 280 and the pixel electrode 290. Will be driven. In this case, portions corresponding to the non-pixel regions except for the pixel electrode 290 are covered by the black matrix 240.

In the present invention, when the gate wiring 260 is formed in a buried structure, no step difference occurs due to the gate wiring 260, and a light leakage area due to the step difference does not occur, and the width W of the gate wire 260 is increased. The design can be reduced.

Therefore, the width of the black matrix 240 constituting the wiring can be greatly reduced, and the aperture ratio is increased by the reduced width of the black matrix 240.

In addition, in the forming of the gate wiring 260, the width W of the gate wiring 260 is decreased to increase the aperture ratio, and the buried height of the gate wiring 260 is corresponding to the reduced width W. By sufficiently securing (D), problems such as signal delay in a large area liquid crystal display can be solved.

--- Second Embodiment ---

Hereinafter, a liquid crystal display according to a second exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

The second embodiment of the present invention is a modification of the configuration of the first embodiment, and duplicated descriptions will be omitted.

The second embodiment of the present invention is characterized in that not only the gate electrode and the wiring, but also the data wiring and the storage electrode are formed in a buried structure to further improve the aperture ratio.

In addition, when the storage electrode is buried, the light leakage area due to the step can be removed, and the width of the storage electrode can be minimized, thereby improving the aperture ratio.

7 is a plan view illustrating a unit pixel of a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 8 is a cross-sectional view taken along the line VII-VII of FIG. 7, and is described in detail with reference to FIGS. 7 and 8. Explain.

As shown in the drawing, a step of defining a switching region S, a gate region G, a data region D, a storage region C, and a pixel region P on the substrate 300 is performed. Next, a transparent organic layer 315 is formed on the entire upper surface of the substrate 300.

Gate wirings and electrodes 320 and 336 are formed in a buried structure along a valley (not shown) in which a portion of the organic layer 315 corresponding to the gate region G is removed, and the gate wirings and electrodes 320 and 336 are formed. After the gate insulating layer 325 is formed on the entire upper surface, pure and impurity amorphous silicon layers 345 and 346 are formed on the gate electrode 336.

Corrugations (not shown) in the gate insulating layer 325 and the organic layer 315 under the same in the same manner as the gate wirings and the electrodes 320 and 336 corresponding to the data region D and the storage region C. After forming the data line 330, a data line 330, a source electrode 332 extending from the data line 330, and a drain electrode 334 spaced apart from each other are formed, and the storage area C is formed. The storage electrode 360 is formed on the substrate.

As described above, when the data line 330 and the storage electrode 360 are formed in a buried structure, the light leakage area due to the step can be removed, and the width of the data line 360 and the width of the storage electrode 360 can be removed. Since the width can be minimized, the aperture ratio can be improved.

A storage capacitor Cst may be configured using the gate line 320 as a first electrode and the storage electrode 360 as a second electrode.

Next, a passivation layer 355 is formed on the entire surface of the substrate 300 on which the source and drain electrodes 332 and 334 are formed, and a part of the drain electrode 334 and a part of the storage electrode 360 are formed. A drain contact hole CH4 and a storage contact hole CH5 are formed to expose each other.

A transparent conductive metal is deposited on the passivation layer 355 on which the drain and storage contact holes CH4 and CH5 are formed, and the pattern is patterned so that one side contacts the drain electrode 334 and the other side contacts the storage electrode 360. The pixel electrode 350 is formed in the pixel region P. FIG.

As described above, the array substrate for the liquid crystal display device according to the second embodiment of the present invention can be manufactured.

Therefore, in the liquid crystal display according to the present invention, if the organic film layer is formed in advance before forming the gate wiring, a portion of the organic film layer is removed to form a valley, and the gate wiring is formed along the valley. Since the width of the black matrix is reduced through the stepless structure with the wiring formed thereafter, high efficiency luminance can be obtained by maximizing the opening.

 However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

For example, the liquid crystal display device according to the present invention may be applied to an organic thin film transistor liquid crystal display device.

In the liquid crystal display according to the present invention, a transparent organic film layer is formed prior to forming the gate electrode and the wiring, and a valley is formed in the organic film layer, and then the gate electrode and the wiring are formed along the valley. A high aperture ratio liquid crystal display device employing a liquid crystal panel having a stepless structure in which no step occurs in the wiring can be manufactured.

In addition, if the width W of the gate wiring is decreased to increase the aperture ratio, and the buried height D of the gate wiring is sufficiently secured to correspond to the reduced width W, the signal delay in the large-area liquid crystal display device It has the effect of solving the same problem.

Claims (20)

delete delete delete delete delete delete delete delete delete Preparing a substrate; Defining a switching region, a gate region, a data region and a pixel region on the substrate; Forming a transparent organic layer on the entire upper surface of the substrate; Forming a valley having a predetermined depth in the transparent organic layer corresponding to the gate region; Applying a conductive metal along a valley formed in the organic layer; Etching the conductive metal to form a gate wiring and a gate electrode in one direction; Forming a gate insulating film on an entire upper surface of the substrate on which the gate electrode and the gate wiring are formed; Sequentially forming a pure and an impurity amorphous silicon layer on the gate insulating film; Removing a portion of the gate insulating layer corresponding to the data region and a portion of the organic layer below the pure and impurity amorphous silicon layer to form a valley; Forming a data line along the valley corresponding to the data area, a source electrode extending from the data line, and a drain electrode spaced apart from the source electrode; Forming a passivation layer on the entire upper surface of the substrate on which the source and drain electrodes and the data wiring are formed; Forming a pixel electrode in contact with the drain electrode corresponding to the pixel region through a drain contact hole exposing a portion of the drain electrode Liquid crystal display device manufacturing method comprising a. 11. The method of claim 10, And a storage electrode formed in a buried structure simultaneously with the data line and in contact with the pixel electrode at a position overlapping with the gate line. The method of claim 11, And a storage capacitor having a portion of the gate wiring as a first electrode and the storage electrode as a second electrode. 13. The method of claim 12, And the first electrode and the second electrode are perpendicular to the substrate. A substrate; A transparent organic film layer formed on the substrate; A gate wiring formed in the organic film layer in a buried structure, and a gate electrode connected to the gate wiring; A gate insulating film formed over the gate electrode and the gate wiring; A pure and impurity amorphous silicon layer formed in an island shape on the gate insulating layer; A data line intersecting the gate line vertically on the pure and impurity amorphous silicon layer, a source electrode extending from the data line, and a drain electrode spaced apart from the source electrode; A storage electrode formed in the organic layer and the gate insulating layer in a buried structure; A passivation layer formed on the source and drain electrodes and the data line; A pixel electrode configured to contact the drain electrode through a drain contact hole exposing a portion of the drain electrode; The storage electrode partially overlaps the gate wiring and is in contact with the pixel electrode, and a storage capacitor includes a portion of the gate wiring as a first electrode and the storage electrode as a second electrode. LCD display device. 15. The method of claim 14, And the gate electrode and the gate wiring are selected from copper paste or silver paste. Claim 16 has been abandoned due to the setting registration fee. 15. The method of claim 14, And a gate electrode, a pure and impurity amorphous silicon layer, and a source and a drain electrode to form a thin film transistor. 15. The method of claim 14, And the storage electrode is made of the same material as the data line. delete 15. The method of claim 14, And the data line has a buried structure. 15. The method of claim 14, And the first electrode and the second electrode are perpendicular to the substrate.

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