KR101172796B1 - Fabrication Method of Self-aligned Channel for Trench-gate Accumulation-mode SiC MOSFET - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the fabrication of metal oxide semiconductor field effect transistors (MOSFETs) for power used in inverters, converters, and various power supplies, and more particularly in trench-gate accumulation mode MOSFETs (Accumulation-mode MOSFETs). It is about a method for manufacturing a constant channel thickness that has a dominant influence on the breakdown voltage and on-resistance characteristics.
The present invention provides an n-type high density silicon carbide substrate in order to uniformize the thickness of the n-base layer in which a channel inducing a breakdown voltage and on-resistance characteristics in a trench-gate accumulation mode MOSFET (AccuFET) is formed. A thin film composed of a high performance n-type n-source layer 630 over an n-base layer 620 where a channel of a MOSFET will be formed over an n-type low concentration drift layer 610 that determines a specific breakdown voltage and on-resistance over 600. Depositing a silicon nitride film 650 on polysilicon 640 to serve as an ion implantation mask for self-alignment on a substrate; A second step of preparing an ion implantation region using the polysilicon 640 and the silicon nitride film 650 as the ion implantation mask; A third step of defining a p-base layer ion implantation region for oxidizing the ion implantation mask to form a silicon oxide film 660; A fourth step of ion implantation to form a p-base layer (680) and a p-source layer (690) in the region defined in the third step; A fifth step of forming an undercut 615 by etching the oxide layer 660 of the ion implantation mask to define the trench-gate region; Depositing an etch mask 625 for defining a trench-gate region; A seventh step of forming a trench-gate region by etching and removing a region in which the polysilicon is exposed in the ion implantation mask and forming a trench through dry etching (635); And an eighth step of removing the etching mask 625 through etching.

Description

Trench-Gate Accumulation Mode Silicon Carbide Metal Oxide Semiconductor Field Effect Method of Forming Self-Aligned N-Base Channel in Transistor {Fabrication Method of Self-aligned Channel for Trench-gate Accumulation-mode SiC MOSFET}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to the fabrication of power metal oxide semiconductor field effect transistors (MOSFETs) used in inverters, converters, and various power supplies, and more particularly, in trench-gate accumulation mode MOSFETs (Accumulation-mode MOSFETs). It is a process to make a constant thickness of n-base layer in which a channel is formed which has a major influence on breakdown voltage and on-resistance characteristics.

MOSFETs are typically energized through a channel formed between the drain and the source by applying a voltage between the gate and the source. Silicon-based MOSFETs are rapidly deteriorating device performance in high-voltage and high-temperature applications. Recently, MOSFETs are being manufactured based on silicon carbide (SiC).

However, silicon carbide MOSFETs have a lower electron mobility in the channel than silicon, and in particular, electron mobility obtained through inversion of the p-base layer formed through ion implantation is further lowered to increase the on-resistance of the device. To overcome these shortcomings, horizontal accumulation mode MOSFETs (AccuFETs) have been developed that utilize electron accumulation in n-type SiC thin film-based channels.

1 shows a cross section of a unit cell of a horizontal AccuFET. In the conventional MOSFET, the p-base (120) layer is in contact with the oxide film under the gate electrode 150 and the gate voltage is increased so that the conduction band of the p-base layer is sufficiently below the Fermi level at the p-base layer and the oxide contact surface. When falling, an electron layer is formed, whereas AccuFET has a p-base layer below the n-type channel. When no gate voltage is applied, a depletion layer is formed on the n-type channel by the p-base layer. This disappears and electrons accumulate so that the current 180 is energized from the drain to the source. However, the horizontal AccuFET has a disadvantage in that the current density cannot be increased because the JFET region 190 is indispensable for the channel to exist in a horizontal structure and electrons flowing from the horizontal channel (as opposed to current flow) to the drain. A trench-gate AccuFET as shown in FIG. 2 has been developed.

In the trench-gate structure of FIG. 2, since the current 280 flows in the same direction as the vertical direction of the n-type channel layer (n-base) 245, that is, the drain direction, unlike the horizontal structure AccuFET, there is no JFET region, and thus the on-resistance deterioration. There is an advantage that can reduce the unit cell size of the device without.

Figure 3 shows a first embodiment for fabricating a conventional trench-gate type MOSFET.

Conventional AccuFET is a photo operation for the etching mask for forming the trench-gate after forming the p-base layer 350 and p + -source (360) layer in the (b) step through the ion implantation step (c) Is needed. At this time, a small alignment error 380 between the substrate and the mask in the photo operation causes a change 395 of the channel thickness of the AccuFET, which affects the breakdown voltage and the on-resistance.

5 shows the change in the breakdown voltage (Maximum operating voltage) and the on-resistance (R _on ) of the AccuFET with the change in the thickness (W _N ) and the concentration of the n-base layer. In addition, in the above embodiment, the photo operation is required in steps (b) and (c).

Figure 4 shows a second embodiment for fabricating a conventional trench-gate type MOSFET. Unlike Example 1, the p-base layer 420 defines a trench region on the substrate in which the thin film is grown and performs dry etching, followed by ion implantation to form an n-type channel layer (n-base layer: 480). And b) defining and ion-implanting the region where the p ⁺ -source layer is to be formed.

In this case, since the thickness of the n-base layer is determined by ion implantation conditions in step (b), there is no problem as in Example 1, but since the n-base region is formed by ion implantation, electron mobility has been lowered. The disadvantage is that the resistance is high and also requires two photo works.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and to provide a process for uniformly forming an n-base layer thickness in which a channel having a dominant influence on breakdown voltage and on-resistance characteristics is formed in a trench-gate accumulation mode MOSFET. The purpose.

In order to solve the above problem in the present invention, the n-base region formation method of the AccuFET of the present invention has a leading influence on the breakdown voltage and on-resistance characteristics of the Accumulation-mode MOSFET (AccuFET). The channel of the MOSFET is formed on the n-type low concentration drift layer 610 which determines a specific breakdown voltage and on-resistance on the n-type high concentration silicon carbide substrate 600 to make the thickness of the n-base layer on which the channel is formed is constant. a first step of depositing a silicon nitride film 650 on a polysilicon 640 to serve as an ion implantation mask for self-alignment on a thin film substrate composed of a high performance n-type n-source layer 630 on a base layer 620; ;

A second step of preparing an ion implantation region using the polysilicon 640 and the silicon nitride film 650 as the ion implantation mask;

A third step of defining a p-base layer ion implantation region for oxidizing the ion implantation mask to form a silicon oxide film 660;

A fourth step of ion implantation to form a p-base layer (680) and a p-source layer (690) in the region defined in the third step;

A fifth step of forming an undercut 615 by etching the oxide layer 660 of the ion implantation mask to define the trench-gate region;

Depositing an etch mask 625 for defining a trench-gate region;

A seventh step of forming a trench-gate region by etching and removing a region in which the polysilicon is exposed in the ion implantation mask and forming a trench through dry etching (635);

And an eighth step of removing the etching mask 625 through etching.

According to a preferred embodiment, the ion implantation process for forming the p-base layer is first performed, followed by etching to remove the n ⁺ -source layer, followed by ion implantation for forming the p ⁺ -source layer.

According to a preferred embodiment, Ni is used as the etch mask material in the sixth step.

According to a preferred embodiment, when the etching mask has a height of 0.1 μm or more in the sixth step, Ti is deposited and Ni is deposited thereon.

According to another preferred embodiment, in the sixth step, using a W as an etching mask material, and performing a high temperature heat treatment process for ion activation without the need to remove W after etching to form a source ohmic layer simultaneously with ion activation .

The method self-aligns the gate trench and p-base layer in one photo operation, thus making it possible to obtain a constant thickness n-base layer in which the channel is formed. In addition, since the MOSFET fabricated by the above method can obtain uniform breakdown voltage and on-resistance characteristics, the wafer yield is improved and excellent device characteristics can be obtained because the thin film is not grown for channel layer formation during the process.

1 is a horizontal AccuFET structure
2 is a trench-gate AccuFET structure
FIG. 3 shows a conventional embodiment 1 for forming a channel layer of a trench-gate AccuFET. FIG.
FIG. 4 shows a conventional embodiment 2 for forming a channel layer of a trench-gate AccuFET. FIG.
5 is a breakdown voltage and on-resistance graph of the thickness and concentration of the n-base layer.
6 is a flow chart of a method for forming an n-base region of an AccuFET, in accordance with a preferred embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

6 shows a process sequence according to an embodiment of the present invention for forming an n-base layer of a constant thickness.

In the first step (FIG. 6A), the n-type low concentration drift layer 610 on the high concentration n-type substrate 600, the n-base layer 620 on which the channel of the MOSFET is to be formed, and the high concentration n-type n ⁺ − The thin film substrate composed of the source layer 630 may be prepared by giving a thin film growth standard in consideration of the breakdown voltage and the on resistance to the thin film growth foundry. For example, if you want to make a device having a breakdown voltage of 600V, the concentration of the n drift layer 610 is 5E15-1.5E16 cm ^-3 is appropriate and the thickness is about 6-8um. Care should be taken because the thickness and concentration of the n-base layer 620 and the p-base layer 680 have a great influence on the threshold voltage, on-resistance, and breakdown voltage of the MOSFET. The thickness of the p-base layer and the n-base layer is about 0.4-0.5um when the concentration of the p-base layer is determined to be 1E17 cm ^-3 , and the concentration of the n-base layer is about 1E15-5E15cm ^-3 . Is suitable. This process can be designed by those skilled in the art through computer simulation, etc., and detailed description is omitted since it is not highly related to the present invention. Hereinafter, the n ⁺ -source layer on the substrate is called an epiwafer.

A silicon nitride film 650 is deposited on the polysilicon 640 to serve as an ion implantation mask for self-alignment on the epi wafer. In this case, the thickness of the polysilicon is related to the thickness of the p-base layer, that is, the energy to be ion implanted, and may be a thickness such that the ion accelerated to the maximum energy does not pass through the polysilicon. For example, if the p-base layer thickness is 0.5um, the thickness of poly-Si is about 1.5um. In addition, since the silicon nitride film does not oxidize the upper end of the polysilicon so that the undercut 615 is sufficient after the oxide film is removed, about 0.1-0.2um is appropriate.

In the second step (b) of FIG. 6, the thickness of the n-base layer is an oxide layer as a preparation step for forming an ion implantation region using the polysilicon 640 and the silicon nitride layer 650 as the ion implantation mask. Since it is the same as the horizontal thickness and is not larger than the trench width, the pattern is formed to the width of the trench.

In the third step (FIG. 6C), the ion implantation mask is oxidized to define a p-base layer ion implantation region. At this time, the oxidation of poly-Si is usually performed at about 800-1000 hours to form an oxide film having the horizontal thickness of the n-base layer.

In the fourth step (D) and (E) of FIG. 6, doping is performed with the energy and dose necessary to form the p-base layer 680 and the p ⁺ -source layer 690 in the defined region. Do it. 0.4-0.5um is appropriate for p-base layer and 1E17 is appropriate for doping concentration. As p ⁺ -source layer is about n ⁺ -source layer depth, about 0.3um is appropriate and doping concentration is about 1E19. At this time, the ion implantation process for forming the p-base layer is first performed, followed by etching to remove the n ⁺ -source layer, followed by ion implantation for forming the p ⁺ -source layer.

In the fifth step (Fig. 6 (bar)) to form a trench-gate region by etching the oxide layer 660 of the ion implantation mask to form an undercut (615), mainly wet etching method using a buffered oxide etch (BOE) Use

In the sixth step (FIG. 6), dry etching is mainly used to form a trench for depositing an etching mask 625 for defining a trench-gate region. Ni, W, Pd, NiCr may be used as the dry etching mask, and Ni is particularly preferable. Ni is most preferred because it has a large etching selectivity during dry etching. On the other hand, since Ni is stressed, Ti may be deposited under Ni in order to deposit more thickly. If the trench depth is less than 1um, a Ni thickness of about 0.1um is sufficient for dry etching. However, if the trench depth is 1 μm or more, since there is a risk of peeling with Ni thickness of about 0.1 μm, when the etching mask has a height of 0.1 μm or more, Ti may be deposited and Ni may be deposited thereon.

In the seventh step (i) and (d), a trench-gate region is defined by etching and removing a polysilicon-exposed region from the ion implantation mask, and a trench is formed through dry etching 635. do. The polysilicon may be removed by wet etching in KOH at 80 ° C., wherein the silicon nitride film and Ni on the polysilicon are removed together with the polysilicon to define the trench region as in step (I). Dry etching to form a trench may be performed by mixing SF ₆ and CF ₄ with O ₂ .

Finally, in the eighth step (FIG. 6 (k)), the etching mask 625 is removed by etching.

After the eighth step (FIG. 6 (k)), a high temperature heat treatment process is generally performed at about 1650 ° C. to electrically activate the implanted ions. In addition, in order to form the source ohmic after the high temperature heat treatment, the metal layer is deposited at the same position as the position where the etching mask 625 metal is formed in the seventh step (FIG. .

However, when using the etching mask in the sixth step (Fig. 6 (G)), the high temperature heat treatment process for the ion activation without the need to remove the W after etching, the source ohmic layer is formed at the same time as the ion activation There is this. In this case, a photo process for depositing a source ohmic metal is reduced, and a separate heat treatment process for forming an ohmic layer can be omitted, thereby reducing process costs.

Through the above process, as shown in FIG. 6 (k) finally formed, it was possible to form the n-base layer 620 of a constant height.

Description of the Related Art [0002]
100: substrate 110: n-drift region
120: p-base layer 130: p + source
140: n-base layer channel 150: polysilicon layer
160: silicon oxide film
170: source pad metal 180: flow of current
190: JFET region
200: substrate 210: n-drift region
220: p-base layer 230: p + source
240: n + source
245: n-base layer channel 250: polysilicon layer
260 silicon oxide film
270: source pad metal 280: flow of current
300: substrate 310: n-drift region
320: n-base layer channel 330: n + source
340: polysilicon layer 350: p-base layer
360: p + source 375: ion implantation
380: misalign degree 390: dry etching
395: thick channel formed by misalign
400: substrate 410: n-drift region
420: p-base layer 425: p + -source
430: n + -source 470: ion implantation
480: n-base layer channel
600: substrate
610: n-drift region 615: undercut
620: n-base layer (channel) 625: etching mask
630: n + -source
640: polysilicon (poly Si) 650: silicon nitride film
660: silicon oxide film
670: ion implantation
680: p-base layer 690: p + -source

Claims (5)

N-type high density silicon carbide substrates (600) to make constant the thickness of the n-base layer where channels are formed that dominate the breakdown-voltage and on-resistance characteristics in trench-gate accumulation-mode MOSFETs (AccuFETs) On a thin film substrate composed of a high performance n-type n-source layer 630 on an n-base layer 620 on which an MOSFET channel will be formed on an n-type low concentration drift layer 610 that determines a specific breakdown voltage and on-resistance. Depositing a silicon nitride film 650 on polysilicon 640 to serve as an ion implantation mask for alignment;
A second step of preparing an ion implantation region using the polysilicon 640 and the silicon nitride film 650 as the ion implantation mask;
A third step of defining a p-base layer ion implantation region for oxidizing the ion implantation mask to form a silicon oxide film 660;
A fourth step of ion implantation to form a p-base layer (680) and a p-source layer (690) in the region defined in the third step;
A fifth step of forming an undercut 615 by etching the oxide layer 660 of the ion implantation mask to define the trench-gate region;
Depositing an etch mask 625 for defining a trench-gate region;
A seventh step of forming a trench-gate region by etching and removing a region in which the polysilicon is exposed in the ion implantation mask and forming a trench through dry etching (635);
And an eighth step of removing the etch mask (625) through etching.
The method of claim 1,
n-base region of AccuFET characterized by first performing ion implantation process for p-base layer formation, etching to remove n ⁺ -source layer, and ion implantation for p ⁺ -source layer formation Formation method.
2. The method of claim 1, wherein the etching mask material is Ni in a sixth step.
The method of claim 3, wherein in the sixth step, when the etching mask has a height of 0.1 μm or more, Ti is deposited and Ni is deposited thereon. 5.
The method of claim 1, wherein in the sixth step, using a W as an etching mask material, and performing a high temperature heat treatment process for ion activation without the need to remove W after etching to form a source ohmic layer simultaneously with ion activation N-base region formation method of AccuFET.

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