JPH11261061A - Silicon carbide semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To provide good carrier mobility even when a channel region is formed by ion implantation. SOLUTION: A silicon oxide film 30 is formed on the surface of an n ⁻ -type silicon carbide epi layer 2 including p ⁻ -type silicon carbide base regions 3a and 3b.
Is formed. Thereafter, a heat treatment is performed to externally diffuse the p-type impurities existing in the surface portions of p ⁻ -type silicon carbide base regions 3a and 3b into silicon oxide film 30. This allows
The surface layer portions of p ⁻ -type silicon carbide base regions 3a and 3b have less p-type impurities. Then, surface channel layer 5a is formed by ion-implanting into p ^- type silicon carbide base regions 3a and 3b. Thereby, the amount of neutral impurities formed by compensating for the p-type impurities can be reduced, and the carrier mobility can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device and a method of manufacturing the same, and more particularly, to an insulated gate field effect transistor, particularly a vertical power MOSF for high power.
It is about ET.

[0002]

2. Description of the Related Art The applicant of the present invention has filed a Japanese Patent Application No. 10-6027 for a planar MOSFET in which the channel mobility is improved and the on-resistance is reduced.
FIG. 9 is a cross-sectional view of the planar MOSFET, and the structure of the planar MOSFET will be described with reference to FIG.

An n ⁺ -type silicon carbide semiconductor substrate 1 has an upper surface as main surface 1a and a lower surface opposite to main surface 1a as back surface 1b.
And On main surface 1a of n ⁺ -type silicon carbide semiconductor substrate 1, n ⁻ -type silicon carbide epitaxial layer (hereinafter referred to as n ⁻ -type silicon carbide epi layer) 2 having a lower dopant concentration than substrate 1 is laminated. I have. At this time, n ⁺
-Type silicon carbide semiconductor substrate 1 and n ⁻ -type silicon carbide epilayer 2
Is formed as a (0001) Si plane, but the upper surfaces of n ⁺ -type silicon carbide semiconductor substrate 1 and n ⁻ -type silicon carbide epilayer 2 may be formed as a (112-0) a plane. That is, (000
1) A low surface state density can be obtained by using the Si surface, and (1)
When the 12-0) a plane is used, a crystal having a low surface state density and completely having no screw dislocation can be obtained.

[0004] n^-In the surface layer of silicon carbide epilayer 2
In a predetermined area, p having a predetermined depth ^-Type silicon carbide base
Regions 3a and p^-Type silicon carbide base region 3b is separated
It is formed. Further, in the base regions 3a and 3b,
Deep base layers 30a and 30b partially thickened
Are formed. The deep base layers 30a, 30
b is n⁺Formed on the part that does not overlap the mold source region
I have. The deep base layers 30a and 30b
The valanche breakdown allows the device
The withstand voltage is improved.

Further, an n ⁺ -type source region 4a shallower than base region 3a and a p ^- type silicon carbide base region 3b at a predetermined region in the surface layer portion of p ^-- type silicon carbide base region 3a. The predetermined area includes a base area 3
An n ⁺ type source region 4b shallower than b is formed. Further, n between the n ⁺ -type source region 4a and the n ⁺ -type source region 4b ^- -type silicon carbide epitaxial layer 2 and the p ^- type silicon carbide base region 3a, the surface portion of the 3b the n ^-
The mold SiC layer 5 extends. In other words, source region 4 is formed on the surface of p ⁻ -type silicon carbide base regions 3a and 3b.
An n-type SiC layer 5 is arranged to connect a, 4b and n ⁻ -type silicon carbide epilayer 2. This n ^- type SiC layer 5
Is formed by ion-implanting an n-type impurity into a predetermined region of the surface portion of p ⁻ -type silicon carbide base regions 3a and 3b and a predetermined region of the surface portion of n ⁻ -type silicon carbide epilayer 2. n-type SiC layer 5, p ^- type silicon carbide base region 3a, the carrier concentration in the surface layer portion of 3b is lower n ^- is composed of a type regions 5a, n ^- in a surface portion of the type silicon carbide epitaxial layer 2 It is composed of an n ⁺ -type region 5b having a high carrier concentration. Of these, the n ⁻ -type region 5 a having a low carrier concentration functions as a channel region. Hereinafter, n ⁻ type region 5a is referred to as a surface channel layer.

A gate insulating film (silicon oxide film) 7 is formed on the upper surface of the surface channel layer 5a and the upper surfaces of the n ⁺ type source regions 4a and 4b. Further, the gate insulating film 7
A polysilicon gate electrode 8 is formed thereon.
The polysilicon gate electrode 8 is covered with an insulating film 9. As the insulating film 9, LTO (Low Temperat)
ure oxide) film is used. A source electrode 10 is formed thereon, and the source electrode 10 includes n ⁺ -type source regions 4a and 4b and p ⁻ -type silicon carbide base region 3
a, 3b. Drain electrode layer 11 is formed on back surface 1b of n ⁺ -type silicon carbide semiconductor substrate 1.

Next, this power planar type MOSFET
Will be described. The MOSFET operates in a storage mode. In surface channel layer 5a, the carrier is the difference in electrostatic potential between p ⁻ -type silicon carbide base regions 3a, 3b and surface channel layer 5a, and the work function between surface channel layer 5a and polysilicon gate electrode 8. Depleted by the potential generated by the difference between Therefore, by adjusting the voltage applied to the polysilicon gate electrode 8, the work function difference between the surface channel layer 5a and the polysilicon gate electrode 8 and the potential difference caused by an externally applied voltage are changed. On / off of the MOSFET is controlled by controlling the state of the channel.

More specifically, in the off state, the depletion region is formed in surface channel layer 5a by the electric field created by p ^- type silicon carbide base regions 3a, 3b and polysilicon gate electrode 8. By supplying a positive bias to the polysilicon gate electrode 8, the gate insulating film (SiO ₂ ) 7 and the surface channel layer 5a are formed.
A channel region extending in the direction of n ⁻ type drift region 2 from n ⁺ type source regions 4a and 4b is formed at the interface between these regions and is switched on.

At this time, electrons are supplied to n ⁺ type source region 4.
a, 4b via the surface channel layer 5a, and from the surface channel layer 5a to the n ⁻ -type silicon carbide epilayer 2 including the JFET portion. Then, when reaching the n ⁻ -type silicon carbide epilayer (drift region) 2, electrons flow vertically to the n ⁺ -type silicon carbide semiconductor substrate (n ⁺ drain) 1. By applying a positive voltage to the gate electrode 8 as described above, a storage channel is induced in the surface channel layer 5a, and a current flows between the source electrode 10 and the drain electrode 11.

As described above, in the planar MOSFET, the operation mode is set to the accumulation mode in which the channel is induced without inverting the conductivity type of the channel forming layer. The on-resistance is reduced by increasing the mobility.

[0011]

The above conventional MO
In SFET, p ^- type silicon carbide base region 3a, by ion-implanting the n-type impurity to 3b, p ^- type silicon carbide base region 3a, a p-type impurity in the 3b compensated with the same amount of n-type impurity ( However, when the activation rate is low, the doping amount increases). Further, ion implantation of an n-type impurity is continued until a desired carrier concentration is reached, whereby the surface channel layer 5a is formed.
Is formed. Therefore, the surface channel layer 5a contains a large amount of neutral impurities other than the n-type impurities serving as carriers.

As described above, it has been found that since the surface channel layer 5a serving as a channel region contains a large amount of neutral impurities, a problem occurs in that carrier mobility is reduced. Also, as the amount of the p-type impurity increases,
The amount of ion implantation of n-type impurities required to compensate for the type impurities also increases. For this reason, defects due to ion implantation increase, a leak may occur, and there is also a problem that the breakdown voltage is reduced.

These problems are caused by the planar type M shown in FIG.
The same applies to all semiconductor devices in which a channel region is formed by injecting ions into a semiconductor containing an impurity having a different conductivity type, without being limited to the OSFET. The present invention has been made in view of the above points, and has a good carrier mobility even when a channel region is formed by ion implantation, and can prevent leakage from defects due to ion implantation, and a method of manufacturing the same. The second object is to provide

Another object of the present invention is to provide a semiconductor substrate suitable for reducing neutral impurities in a channel region when a channel region is formed by ion implantation.
The purpose of.

[0015]

In order to achieve the above object, the following technical means are employed. According to the first aspect of the present invention, the first conductivity type impurity is ion-implanted into the surface of the second conductivity type semiconductor layer (3a, 3b).
The semiconductor device has a surface channel layer (5) formed so as to connect the source region (4a, 4b) and the drain layer (2), and the concentration of the second conductivity type impurity interposed in the surface channel layer is:
The semiconductor layer (3a, 3b) is characterized in that the concentration thereof is lower than the concentration of the second conductivity type impurity interposed in a region located below the surface channel layer.

As described above, the concentration of the second conductivity type impurity interposed in the surface channel layer is lower than the concentration of the second conductivity type impurity interposed in the region of the semiconductor layer located below the surface channel layer. If the concentration of the second conductivity type impurity in the portion of the semiconductor layer where the surface channel layer is formed is lower than that of the other portion of the semiconductor layer, it is formed by ion implantation. Neutral impurities can be reduced. Further, since the amount of ion implantation is reduced, crystal defects of the surface channel layer are reduced. Thereby, even when the surface channel layer is formed by ion implantation, the carrier mobility can be improved.

According to the second aspect of the present invention, the semiconductor device has a second conductivity type channel layer formed by ion-implanting a second conductivity type impurity into a surface portion of the semiconductor layer. The concentration of the first conductivity type impurity is lower than the concentration of the first conductivity type impurity interposed in a region of the semiconductor layer located below the channel layer. Thereby, the same effect as the first aspect can be obtained.

According to the third aspect of the present invention, the second conductivity type impurity is ion-implanted into the surface layer portion of the first conductivity type semiconductor layer made of silicon carbide to reverse the conductivity type. In a silicon carbide semiconductor device in which a portion into which a conductivity type impurity is implanted is used as a channel region, a portion of the semiconductor layer where the concentration of the first conductivity type impurity interposed in the channel region is lower than the channel region. Is characterized by being lower than the concentration of the first conductivity type impurity interposed therebetween. Thereby, the same effect as the first aspect can be obtained.

According to a fourth aspect of the present invention, there is provided an external diffusion step for diffusing a second conductivity type impurity present in a surface portion of the semiconductor layer (3a, 3b) to the outside of the semiconductor layer; Forming a surface channel layer (5) serving as a channel region by ion-implanting the first conductive type in a predetermined region of a surface layer portion of the semiconductor layer. Source region (4a,
4b).

As described above, after diffusing the second conductivity type impurity present in the surface layer portion of the semiconductor layer to the outside of the semiconductor layer,
By performing ion implantation to form the surface channel layer, the surface channel layer can be formed after the compensated second conductivity type impurities are reduced, so that neutral impurities in the surface channel layer are reduced. And the amount of ion implantation can be reduced. Therefore, the carrier mobility of the surface channel layer can be improved, and the crystal defects of the surface channel layer can be reduced.

Also, in the invention according to claim 5,
An external diffusion step of diffusing a first conductivity type impurity present in a surface portion of the semiconductor layer to the outside of the semiconductor layer; and a step of performing ion implantation into the surface portion of the semiconductor layer to form a second conductivity type channel layer And the same effect as in claim 4 can be obtained. According to a sixth aspect of the present invention, there is provided an external diffusion step of diffusing a first conductivity type impurity interposed in a surface layer portion of the semiconductor layer to the outside of the semiconductor layer. , After the diffusion step.

As described above, by performing the ion implantation step for forming the channel region after the external diffusion step, the same effect as that of the fourth aspect can be obtained. As described in claim 7, the external diffusion step can be performed by forming a diffusion film on the semiconductor layer and diffusing impurities into the diffusion film. Specifically, as described in claim 8, silicon oxide can be used as the diffusion film.

In the ninth aspect, the external diffusion step can be performed by performing a heat treatment under a reduced pressure atmosphere and diffusing impurities into the atmosphere. Claim 10
In the invention described in (1), the semiconductor device has a semiconductor layer of the first conductivity type, and impurities of the first conductivity type in the surface layer portion of the semiconductor layer are diffused outside the semiconductor layer, and the first conductivity type interposed in the surface portion is provided. The semiconductor device is characterized in that the concentration of the type impurity is lower than the concentration of the first conductivity type impurity interposed inside the surface layer portion of the semiconductor layer.

As described above, using the silicon carbide semiconductor substrate in which the concentration of the first conductivity type impurity in the surface layer portion of the semiconductor layer is lower than that in the inside thereof, the surface layer of the semiconductor layer having the lower concentration is used. By forming the portion in the channel region, the carrier mobility in the channel region can be improved, and crystal defects due to ion implantation can be reduced.

According to an eleventh aspect of the present invention, the concentration of the first conductivity type impurity is low with a linear relationship with the depth from the surface of the semiconductor layer. I have. As described above, by making the depth from the surface of the semiconductor layer and the concentration of the first conductivity type impurity have a linear relationship, channel mobility can be increased. Such a relationship may be achieved by forming a film for external diffusion (for example, silicon oxide or silicon nitride) on the surface of the semiconductor layer, and then performing a high-temperature and long-time heat treatment.

In order to make the above relationship a relationship according to the error function, external diffusion may be performed by a low-temperature and short-time heat treatment. Then, external diffusion may be performed.

[0027]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 1 shows a normally-off n-channel planar MOSFET according to the present embodiment.
FIG. 1 shows a cross-sectional view of a (vertical power MOSFET). This device is suitable for application to a rectifier of an inverter or a vehicle alternator.

The structure of the vertical power MOSFET will be described with reference to FIG. However, the vertical power MOSFET according to the present embodiment is the same as the MOSFET shown in FIG.
Since it has a structure similar to that of T, only different parts will be described. Note that, in the vertical power MOSFET of the present embodiment, the same portions as those of the MOSFET shown in FIG. 9 are denoted by the same reference numerals.

In the MOSFET shown in FIG. 9, the channel region is constituted by the surface channel layer 5a containing a large amount of neutral impurities. In the vertical power MOSFET according to the present embodiment, however, the neutral region is more neutral. A channel region is constituted by the surface channel layer 5a having a small amount of impurities.
As described above, since the neutral impurities inside the surface channel layer 5a are reduced, carrier mobility in the surface channel layer 5a can be improved.

The vertical power unit shown in FIG.
-Manufacturing process of MOSFET will be described with reference to FIGS.
I do. [Step shown in FIG. 2 (a)] First, an n-type 4H or 6H
Or 3C-SiC substrate, ie, n⁺Type silicon carbide semiconductor
A substrate 1 is prepared. This n⁺Type silicon carbide semiconductor substrate 1
Is 1 × 10¹⁸cm ^-3N-type impurity at high concentration
Have been pinged. With such a high concentration, p
^-Of punch-through in silicon carbide base regions 3a and 3b
And the depletion of the surface channel layer 5a is easily performed.
I can get it. Where n⁺Type silicon carbide semiconductor base
The plate 1 has a thickness of 400 μm and a main surface 1 a of (0
(001) Si plane or (112-0) a plane. This
5 μm thick n on the main surface 1 a of the substrate 1^-Type silicon carbide
The layer 2 is epitaxially grown. In this example, n^-Type charcoal
The same crystal as that of the underlying substrate 1 is obtained from the silicon oxide epilayer 2,
It becomes an n-type 4H or 6H or 3C-SiC layer.

[Step shown in FIG. 2 (b)] An LTO film 20 is arranged in a predetermined region on the n ⁻ -type silicon carbide epitaxial layer 2, and B ⁺ (or aluminum) is ion-implanted using the LTO film 20 as a mask. P ^- type silicon carbide base regions 3a and 3b are formed. The ion implantation conditions at this time are such that the p ^- type silicon carbide base regions 3a and 3b have a p-type impurity concentration of 1 × 10 ¹⁸ cm.
^The temperature is 700 ° C. and the dose is 1 × 1 so as to be ^-3.
0 ¹⁶ cm ^-2 .

[Step shown in FIG. 2 (c)] After the LTO film 20 is removed, a heat treatment is performed to form silicon oxide on the n ⁻ -type silicon carbide epi layer 2 including on the p ⁻ -type silicon carbide base regions 3a and 3b. An (SiO ₂ ) film 30 is formed. Then, a heat treatment for external diffusion (hereinafter, referred to as an external diffusion step) is further performed. Specifically, heat treatment is performed at 1300 ° C. for 0.5 hour.

At this time, p ^- type silicon carbide base region 3
a, a silicon oxide film 30 is formed on 3b, because of the relatively small diffusion resistance, p This heat treatment ^-
Impurities present in the surface layer portions of type silicon carbide base regions 3a, 3b are diffused outside into silicon oxide film 30. This external diffusion step will be described by taking as an example a case where a silicon oxide 52 is formed on a p-type semiconductor substrate 51. FIG.
(A) to (c) show silicon oxide 5 on p-type semiconductor substrate 51.
2 shows an external diffusion step when film No. 2 is formed. FIG.
2A to 2C show not only the external diffusion step shown in FIG. 2C but also an ion implantation of an n-type impurity for forming a channel region shown in FIG. The process will be described by including the ion implantation process. Specifically, FIG. 5A shows a state during the external diffusion step, FIG. 5B shows a state after the external diffusion step, and FIG. 5C shows a state after the external diffusion step. The state of the ion implantation process is shown.

As shown in FIG. 5A, prior to the external diffusion step, a p-type impurity 53 such as boron is substantially evenly present from the surface to the inside of the p-type semiconductor substrate 51. Then, by performing the external diffusion step, the p-type impurity 53 present on the surface side of the p-type semiconductor substrate 51 is externally diffused into the silicon oxide film 52 as shown by the arrow in the figure.

Then, as shown in FIG. 5B, after the external diffusion step, the p-type impurity 53 on the surface side of the p-type semiconductor substrate 51 is reduced, and the surface side of the p-type semiconductor substrate 51 is reduced. The intervening p-type impurity 53 becomes a silicon oxide film 52
Moved inside. Thereafter, the silicon oxide 52 is removed using an aqueous solution containing hydrofluoric acid as an etching solution, and n
When the impurity 54 is ion-implanted, an n-type semiconductor layer 55 is formed on the surface of the p-type semiconductor substrate 51 as shown in FIG.

FIG. 6A shows the result of examining the impurity concentration in the p-type semiconductor substrate 51 on which the n-type semiconductor layer 55 is formed in the case where the external diffusion step is performed as described above.
FIG. 6B shows the result of examining the impurity concentration in the p-type semiconductor substrate 51 'on which the layer of the n-type semiconductor 55' was formed when the external diffusion step was not performed. 6A and 6B, the vertical axis represents the depth and the horizontal axis represents the impurity concentration, and the vertical axis represents the depth of the p-type semiconductor substrate 51 shown on the left side of the drawing. , 51 'correspond to the depth from the surface.

As shown in FIG. 6A, when the external diffusion step is performed, the p-type impurity concentration in the n-type semiconductor layer 55 is low, and the p-type impurity It can be seen that the total impurity concentration obtained by adding the impurity concentration and the n-type impurity concentration is small. On the other hand, as shown in FIG. 6B, when the external diffusion step is not performed, the p-type impurity concentration on the surface side of the n-type semiconductor layer 55 'is not reduced, so that the n-type impurity is In the case of adding, the total impurity concentration obtained by adding the p-type impurity concentration and the n-type impurity concentration is very high.

As can be seen from these results, by reducing the amount of p-type impurities interposed in the surface layers of p-type silicon carbide base regions 3a and 3b by the above-mentioned external diffusion step,
The amount of neutral impurities formed by ion implantation of n-type impurities can be reduced. Further, since the amount of ion implantation of the n-type impurity required to compensate for the p-type impurity can be reduced, crystal defects due to the ion implantation can be reduced.

[Step shown in FIG. 3A] After the silicon oxide film 30 is removed, an n-type impurity is ion-implanted as described above. Specifically, N ⁺ ions are implanted from the upper surface of substrate 1 to form surface channel layer 5a on the surface portions (surface layer portions) of p ⁻ -type silicon carbide base regions 3a and 3b,
An n ⁺ -type layer 5b is added to the surface of the n ⁻ -type silicon carbide
It is formed with a thickness of about 3 μm. The ion implantation conditions at this time are as follows: a temperature of 700 ° C. and a dose of 1 × 10 ¹³ to 1 × 1.
It is set to 0 ¹⁴ cm ^-2 .

At this time, as described above, in the surface portions (surface layer portions) of p ⁻ -type silicon carbide base regions 3a and 3b, since the p-type impurities are reduced by the external diffusion step, surface channel layer 5a is formed in the middle. It is formed of a material having few sexual impurities. Therefore, the carrier mobility of the surface channel layer 5a can be improved. Further, the amount of ion implantation of n-type impurities required for compensating for p-type impurities in p ⁻ -type silicon carbide base regions 3a and 3b can be reduced, so that crystal defects due to ion implantation can be reduced. For this reason, it is possible to prevent the occurrence of leakage current due to crystal defects.

In order to make the vertical power MOSFET a normally-off type, the thickness (film thickness) of the surface channel layer 5a is determined based on the following equation. In order to make the vertical power MOSFET a normally-off type, when a gate voltage is not applied, a depletion layer extending to the n ⁻ -type layer has a sufficient barrier height so as to prevent electric conduction. There is a need. This condition is expressed by the following equation.

[0042]

(Equation 1)

Here, Tepi is the height of the depletion layer extending over the n ⁻ -type layer. The first term on the right-hand side of this equation 1 is the extension of the depletion layer due to the built-in voltage Vbuilt of the PN junction between the surface channel layer 5a and the p ⁻ -type silicon carbide base regions 3a and 3b, ie, the p ⁻ -type silicon carbide base region 3a , 3b is the amount of elongation of the depletion layer extending from the surface channel layer 5a,
The second term is the amount of expansion of the depletion layer due to the charge of the gate insulating film 7 and φms, that is, from the gate insulating film 7 to the surface channel
The amount of elongation of the depletion layer. Therefore, the extension amount of the depletion layer extending from the p ⁻ -type silicon carbide base regions 3a and 3b,
If the sum of the extension of the depletion layer extending from the gate insulating film 7 and the thickness of the surface channel layer 5a is set to be equal to or greater than the thickness of the surface channel layer 5a, the vertical power MOSFET can be made a normally-off type. The surface channel layer 5a is formed under the conditions.

Such a normally-off type vertical power M
The OSFET can prevent a current from flowing even when a voltage cannot be applied to the gate electrode due to a failure or the like, so that safety can be ensured as compared with a normally-on type. As shown in FIG. 1, p ⁻ -type silicon carbide base regions 3a and 3b are in contact with source electrode 10 and are in a ground state. Therefore, surface channel layer 5a and p ⁻ -type silicon carbide base region 3
The surface channel layer 5a can be pinched off using the built-in voltage Vbuilt of the PN junction with the a and 3b. For example, when p ^- type silicon carbide base regions 3a and 3b are not grounded and are in a floating state, a depletion layer is extended from p ^- type silicon carbide base regions 3a and 3b using built-in voltage Vbuilt. Therefore, bringing p ⁻ -type silicon carbide base regions 3 a and 3 b into contact with source electrode 10 requires surface channel layer 5
It can be said that the structure is effective for pinching off a. In this embodiment, the p ⁻ -type silicon carbide base regions 3a and 3b are formed with a low impurity concentration. However, by increasing the impurity concentration, the built-in voltage Vbuilt can be more utilized.

Further, in this embodiment, the vertical power MOSFET is manufactured by using silicon carbide. However, if the vertical power MOSFET is manufactured by using silicon, the p ^- type silicon carbide base regions 3a and 3b, the surface channel layer 5a and the like are not used. It is difficult to control the diffusion amount of thermal diffusion when forming the impurity layer described above, so that it is difficult to manufacture a normally-off type MOSFET similar to the above-described configuration. Therefore, by using SiC as in the present embodiment, a vertical power MOSFET can be manufactured with higher accuracy than when silicon is used.

A normally-off type vertical power MOS
In order to make an FET, it is necessary to set the thickness of the surface channel layer 5a so as to satisfy the condition of the above formula 1,
Since Vbuilt is low when silicon is used, the surface channel layer 5a must be formed with a reduced thickness or a low impurity concentration. Considering that it is difficult to control the diffusion amount of impurity ions, It can be said that manufacturing is very difficult. However, when SiC is used, Vbuilt
Is about three times as high as silicon, and can be formed by increasing the thickness of the n ⁻ -type layer or increasing the impurity concentration. Therefore, it can be said that it is easy to manufacture a normally-off type storage MOSFET.

[0047] The LTO layer 21 is disposed in a predetermined region on the surface channel layer 5a [step shown in FIG. 3 (b)], the N ⁺ ions are implanted as a mask, n ⁺ -type source region 4
a and 4b are formed. The ion implantation conditions at this time were 7
At 00 ° C., the dose is 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² .

[Step shown in FIG. 3 (c)]
After removing the film 21, the LTO film 22 is disposed in a predetermined region on the surface channel layer 5a using a photoresist method,
Using this as a mask, surface channel layer 5a on p ⁻ -type silicon carbide base regions 3a and 3b is partially etched away by RIE.

[Step shown in FIG. 4 (a)]
B ⁺ ions are implanted using the film 22 as a mask to form the deep base layers 30a and 30b. Thereby, a part of the base regions 3a and 3b becomes thicker. The deep base layers 30a and 30b are formed in the n ⁺ type source region 4
a and 4b are formed in portions that do not overlap with each other, and portions of the p ⁻ -type silicon carbide base regions 3a and 3b where the deep base layers 30a and 30b are formed are thicker.
The impurity concentration is formed higher than that of the thin portion where the deep base layer 30a is not formed.

[Step shown in FIG. 4B] After the LTO film 22 is removed, a gate insulating film (gate oxide film) 7 is formed on the substrate by wet oxidation. At this time, the ambient temperature is 1080 ° C. Thereafter, a polysilicon gate electrode 8 is deposited on the gate insulating film 7 by LPCVD. The film formation temperature at this time is 600 ° C.

[Step shown in FIG. 4C] Subsequently, after removing unnecessary portions of the gate insulating film 7, an insulating film 9 made of LTO is formed to cover the gate insulating film 7. More specifically,
The film formation temperature is 425 ° C., and annealing is performed at 1000 ° C. after the film formation. After that, the source electrode 10 and the drain electrode 11 are arranged by metal sputtering at room temperature. When annealing at 1000 ° C. is performed after the film formation, the vertical power MOSFET shown in FIG. 1 is completed.

Next, the operation (operation) of this vertical power MOSFET will be described. This MOSFET operates in a normally-off type accumulation mode, and when no voltage is applied to the polysilicon gate electrode, the surface channel layer 5
a, the carrier is a p ⁻ -type silicon carbide base region 3
a, 3b and the surface channel layer 5a, and the entire area is depleted by a potential caused by a difference in work function between the surface channel layer 5a and the polysilicon gate electrode 8. By applying a voltage to the polysilicon gate electrode 8, a potential difference caused by a sum of a work function difference between the surface channel layer 5a and the polysilicon gate electrode 8 and an externally applied voltage is changed. As a result, the state of the channel can be controlled.

That is, the work function of the polysilicon gate electrode 8 is set to the first work function, the work function of the p ⁻ -type silicon carbide base regions 3a and 3b is set to the second work function, and the work function of the surface channel layer 5a is set to When the third work function is set, the difference between the first to third work functions is used to obtain the surface channel layer 5.
The first to third work functions and the impurity concentration and the film thickness of the surface channel layer 5a can be set so as to deplete the n-type carrier a.

In the off state, the depletion region is p
^- type silicon carbide base region 3a, by an electric field created by 3b and the polysilicon gate electrode 8 is formed on the surface channel layer 5a. When a positive bias is applied to the polysilicon gate electrode 8 from this state, the n ⁺ -type source regions 4a and 4b cause n ⁻ -type drift at the interface between the gate insulating film (SiO ₂ ) 7 and the surface channel layer 5a. A channel region extending in the direction of region 2 is formed, and is switched on. At this time, electrons flow from n ⁺ -type source regions 4a and 4b via surface channel layer 5a to n ⁻ -type silicon carbide epi layer 2 from surface channel layer 5a. Then, n ⁻ -type silicon carbide epilayer 2 (drift region)
When electrons reach n ⁺ , the electrons are transferred to n ⁺ type silicon carbide semiconductor substrate 1 (n
⁺ Drain).

At this time, since the surface channel layer 5a is formed with less neutral impurities, the channel mobility can be improved, and the amount of ion implantation for forming the surface channel layer 5a is small. Has become
Crystal defects due to ion implantation can be reduced, and leakage due to crystal defects can be prevented. (Second Embodiment) In the first embodiment, the case where one embodiment of the present invention is applied to a vertical power MOSFET in which current flows in the vertical direction (the thickness direction of the substrate) has been described. A case in which an embodiment of the present invention is applied to a MOSFET flowing in the lateral direction of the substrate (the direction parallel to the surface of the substrate) will be described.

FIG. 7 shows a MOSFET according to this embodiment.
Is shown. As shown in this figure, a channel layer 102 constituting a channel region is provided on a surface layer portion of a p-type semiconductor substrate 101.
Are formed. The channel layer 102 is formed of a material having a small amount of neutral impurities. An n ⁺ type region 1 for source contact is provided at one end of the channel layer 102.
03 is formed, and at the other end, an n ⁺ type region 104 for drain contact is formed. A gate electrode layer 106 is formed on the channel layer 102 with a gate oxide film 105 interposed therebetween.

The MOSFET configured as described above has p
Layer 1 formed on the surface layer of semiconductor substrate 101
A current flows in the lateral direction of the p-type semiconductor substrate 101 with 02 as a channel region. At this time, as described above, since the channel layer 102 is formed with a small amount of neutral impurities, carrier mobility can be improved.

Next, a method of manufacturing the MOSFET shown in FIG. 7 will be described with reference to FIGS. [Step shown in FIG. 8A] First, a p-type semiconductor substrate 101 having a reduced amount of p-type impurities in a surface layer portion is prepared. The p-type semiconductor substrate 101 has p inside evenly.
It can be manufactured by performing the external diffusion process shown in the first embodiment on the semiconductor substrate containing the type impurities. This p-type semiconductor substrate 101 is suitable for manufacturing the MOSFET shown in FIG.

[Step shown in FIG. 8B] An oxide film 110 is formed on the surface of the p-type semiconductor substrate 101, and a predetermined region of the oxide film 110 is opened through a photolithography process. Then, using the oxide film 110 as a mask, ions of an n-type impurity (for example, N ⁺ ) are implanted to form the channel layer 10.
Form 2

At this time, since the channel layer 102 is formed in the surface layer portion of the p-type semiconductor substrate 101 in which the amount of the p-type impurity is reduced, the channel layer 102 is formed with less neutral impurities. In addition, ion implantation of n-type impurities required for compensating for p-type impurities can be reduced, so that crystal defects due to ion implantation can be reduced.

[Step shown in FIG. 8C] After removing the oxide film 110, an oxide film 111 is formed again on the surface of the p-type semiconductor substrate 101, and a predetermined region of the oxide film 111 is formed through a photolithography process. To open. And the oxide film 1
Using n as a mask, n-type impurities (for example, N ⁺ ) are ion-implanted to form an n ⁺ -type layer 103 for a source contact and an n ⁺ -type layer 104 for a drain contact.

After the oxide film 111 is removed, a gate oxide film 105 and a gate electrode 106 are formed in this order, and a source electrode layer and a drain electrode layer are formed via an interlayer insulating film (not shown). MOSF shown in FIG.
ET is completed. As described above, the current M flows in the lateral direction.
One embodiment of the present invention can be applied to an OSFET or the like.

(Other Embodiments) In the first and second embodiments, MOSFETs have been described as examples. However, the present invention can be applied to FETs of other forms. For example, the present invention can be applied to a lateral type MESFET, and can also be applied to a trench gate type MOSFET in which a groove is formed in a substrate and a channel region is formed on a side surface of the groove.

In the first embodiment, since the heat treatment is performed under the above conditions (high temperature, long time), the concentration of the p-type impurity with respect to the depth from the substrate surface has a linear relationship (see FIG. 6). However, the depth may have a relationship according to a logarithmic function, or may have a relationship according to an error function. For example, in order to make the relationship according to the logarithmic relationship, high-temperature or long-time heat treatment may be performed, and to make the relationship according to the error function shown in the first embodiment. The heat treatment may be performed at a lower temperature and for a shorter time than the heat treatment. However, since the carrier mobility can be further increased by forming a linear relationship as in the above embodiment, it can be said that the heat treatment under the above conditions is more preferable.

Further, in the above embodiment, the silicon oxide film 30 is formed by thermal oxidation for external diffusion, but may be formed by another method (eg, deposition). Further, even if a silicon nitride film or aluminum nitride is formed instead of the silicon oxide film 30, external diffusion can be performed.

For example, the silicon nitride film can be formed by performing thermal oxidation in a nitrogen atmosphere, performing thermal oxidation in an oxygen-nitrogen atmosphere, or performing thermal oxidation after doping with nitrogen. Note that a silicon nitride film is an insulator having a high dielectric constant and a high band gap, and thus is effective for passivation.

Also, without forming a film for external diffusion,
It is possible to perform the above external diffusion. For example, high-temperature heat treatment can be performed in a vacuum atmosphere. That is, the reason why the diffusion of the impurity is not performed is that the diffusion resistance is increased, and the impurity can be diffused under the condition that the diffusion resistance is reduced. It is not necessary to form a film.

Further, in the above-described embodiment, the n-type impurity is ion-implanted after the silicon oxide film 30 is removed. However, the silicon oxide film 30 can be used as a mask at the time of ion implantation. As a result, the manufacturing process can be simplified. The silicon oxide film 3
The same can be said for a case where a silicon nitride film or the like is used instead of 0.

[Brief description of the drawings]

FIG. 1 is a vertical power MOS according to an embodiment of the present invention.
It is sectional drawing of FET.

FIG. 2 is a diagram showing a manufacturing process of the vertical power MOSFET shown in FIG.

FIG. 3 is a view illustrating a manufacturing process of the vertical power MOSFET following FIG. 2;

FIG. 4 is a view illustrating a manufacturing process of the vertical power MOSFET following FIG. 3;

FIG. 5 is a schematic view for explaining an external diffusion step.

FIG. 6 is a diagram comparing a case where an external diffusion step is performed and a case where the external diffusion step is not performed.

FIG. 7 is a cross-sectional view of a MOSFET according to a second embodiment.

FIG. 8 is a view showing a manufacturing process of the MOSFET shown in FIG. 7;

FIG. 9 is a vertical power MOSFE filed by the present applicant.
It is sectional drawing which shows the structure of T.

[Explanation of symbols]

1 ... n ⁺ -type silicon carbide semiconductor substrate, 2 ... n ^- -type silicon carbide epitaxial layer, 3a, 3b ... p ^- type silicon carbide base region, 4a, 4b ... n ⁺ -type source region, 5a ... surface channel layer (n ^- 7 gate insulating film, 8 gate electrode, 9 insulating film, 10 source electrode, 11 drain electrode layer, 101 p-type semiconductor substrate, 102 channel layer, 103, 104 n ⁺ Mold layer, 105: gate insulating film, 106: gate electrode.

Claims (12)

[Claims] A semiconductor substrate of a first conductivity type having a main surface and a back surface opposite to the main surface and made of silicon carbide.
A first conductivity type drain layer (2) formed on the main surface of the semiconductor substrate and made of silicon carbide having a higher resistance than the semiconductor substrate; and formed in a predetermined region of a surface layer portion of the drain layer; A second conductivity type semiconductor layer (3a, 3b) having a predetermined depth; and a first conductivity type source region (4a, 4b) formed in a predetermined region of a surface portion of the semiconductor layer and shallower than the semiconductor layer. 4
b) ion-implanting a first conductivity type impurity into a surface portion of the semiconductor layer and a surface portion of the drain layer to form a silicon carbide formed to connect the source region and the drain layer. A first conductivity type surface channel layer (5a), a gate insulating film (7) formed on the surface of the surface channel layer, and a gate electrode (8) formed on the gate insulating film.
A source electrode (10) formed to contact the semiconductor layer and the source region; and a drain electrode (1) formed on the back surface of the semiconductor substrate.
1) wherein the concentration of the second conductivity type impurity interposed in the surface channel layer is the second conductivity type impurity interposed in a region of the semiconductor layer located below the surface channel layer. A silicon carbide semiconductor device, wherein the concentration is lower than the concentration of impurities. 2. A semiconductor substrate having a first conductivity type semiconductor layer made of silicon carbide, and a second conductivity type formed by ion-implanting a second conductivity type impurity into a surface portion of the semiconductor layer. Channel layer (102), contact regions (103, 104) of the second conductivity type located at both ends of the channel layer, and a gate electrode formed at least on the channel layer using the channel layer as a channel region A layer (106), wherein the concentration of the first conductivity type impurity interposed in the channel layer is the first conductivity type impurity interposed in a region of the semiconductor layer located below the channel layer. A silicon carbide semiconductor device characterized by having a concentration lower than that of the silicon carbide semiconductor device. 3. A method of inverting the conductivity type by ion-implanting impurities of a second conductivity type into a surface layer portion of a semiconductor layer (3a, 3b, 101) of the first conductivity type made of silicon carbide.
The part where the conductivity type impurity is implanted is defined as a channel region (5).
a, 102), in a silicon carbide semiconductor device that switches a current flowing through the channel region by applying a voltage to at least a gate electrode (9, 106) formed on the channel region. The concentration of the first conductivity type impurity interposed in the region is lower than the concentration of the first conductivity type impurity interposed in a region of the semiconductor layer located below the channel region. A silicon carbide semiconductor device, characterized by: 4. forming a first conductivity type drain layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate on a main surface of the first conductivity type semiconductor substrate (1); Forming a second conductivity type semiconductor layer (3a, 3b) having a predetermined depth in a predetermined region of a surface layer portion of the drain layer; and removing a second conductivity type impurity interposed in the surface layer portion of the semiconductor layer. An external diffusion step of diffusing to the outside of the semiconductor layer, performing ion implantation in a predetermined region of a surface layer portion of the semiconductor layer,
Forming a surface channel layer (5a) serving as a channel region; and forming a source region of a first conductivity type in contact with the surface channel layer and shallower than a depth of the semiconductor layer in a predetermined region of a surface layer portion of the semiconductor layer. 4a, 4b). A method for manufacturing a silicon carbide semiconductor device, comprising: 5. A semiconductor substrate (101) including a semiconductor layer of a first conductivity type made of silicon carbide is prepared, and an impurity of the first conductivity type interposed in a surface layer portion of the semiconductor layer is diffused outside the semiconductor layer. An external diffusion step of forming a second conductive type channel layer (102) by ion-implanting a second conductive type impurity into a surface layer of the semiconductor layer; and forming the channel on both sides of the channel layer. Forming a second conductivity type contact region (103, 104) having a lower resistance than the layer; forming a gate electrode layer (106) on at least the channel layer using the channel layer as a channel region; A method for manufacturing a silicon carbide semiconductor device, comprising: 6. An ion implantation of a second conductivity type impurity into a surface layer portion of a first conductivity type semiconductor layer (3a, 3b, 101) made of silicon carbide, thereby inverting the conductivity type to form a channel region (3). 5a, 102), and at least a gate electrode (9, 106) formed on the channel region.
A method of manufacturing a silicon carbide semiconductor device in which current applied to the channel region is switched by applying a voltage to the semiconductor layer, wherein a first conductivity type impurity present in a surface portion of the semiconductor layer is diffused outside the semiconductor layer. A method for manufacturing a silicon carbide semiconductor device, comprising an external diffusion step, wherein the ion implantation is performed after the diffusion step. 7. The external diffusion step is a step of forming a diffusion film (30) on the semiconductor layer and diffusing impurities into the diffusion film.
The silicon carbide semiconductor device according to any one of the above. 8. A silicon oxide (3) as the diffusion film.
The silicon carbide semiconductor device according to claim 7, wherein 0) is used. 9. The silicon carbide according to claim 4, wherein the external diffusion step is a step of performing a heat treatment under a reduced pressure atmosphere to diffuse impurities into the atmosphere. Semiconductor device. 10. A second conductivity type impurity is ion-implanted into a surface layer portion of a first conductivity type semiconductor layer (3a, 3b, 101) made of silicon carbide, thereby inverting the conductivity type to form a channel region (3). 5a, 102), and at least a gate electrode (9, 10) formed on the channel region.
6) A silicon carbide semiconductor substrate used for manufacturing a silicon carbide semiconductor device that performs switching of a current flowing in the channel region by applying a voltage to the substrate, wherein the semiconductor layer is located on a surface, The first conductivity type impurity in the surface portion of the semiconductor layer is diffused to the outside of the semiconductor layer, and the concentration of the first conductivity type impurity interposed in the surface layer is higher than the concentration of the first conductivity type impurity in the semiconductor layer. A silicon carbide semiconductor substrate having a lower concentration than an intervening first conductivity type impurity. 11. The silicon carbide semiconductor substrate according to claim 10, wherein the concentration of said impurity has a low concentration in a linear relationship with the depth from said surface. 12. The PN junction is formed on the surface side where the impurity concentration is low, by doping an impurity of a conductivity type different from the impurity. Or the silicon carbide semiconductor substrate according to claim 11.