KR101110177B1 - EEPROM Cell and the method for manufacturing EEPROM Cell - Google Patents

Abstract

The present invention relates to a method for manufacturing an EEPROM cell in which the profile of the control gate is a vertical profile to secure the area of the LDD spacer to prevent an increase in the breakdown voltage of the junction region. Depositing a tunnel oxide film, a floating gate polysilicon, and an upper oxide film; Forming the hard mask thickly; Forming a floating gate by a photolithography and an etching process on the hard mask, the upper oxide layer, the floating gate polysilicon, and the tunnel oxide layer; Depositing an oxide film and a nitride film on the entire surface of the resultant of forming the floating gate; Etching the nitride film and the oxide film to form a sidewall oxide film and a sidewall nitride film on a sidewall of the floating gate; Cleaning the resultant of forming the sidewall nitride film and the sidewall oxide film; Performing the cleaning process and depositing a gate oxide film for a high voltage region and then depositing control gate polysilicon; Etching the control gate polysilicon to form a control gate having a vertical profile.

Control Gate, Vertical Profile, LDD Spacer

Description

EEPROMO cell and its manufacturing method {EEPROM Cell and the method for manufacturing EEPROM Cell}

1A to 1I are cross-sectional views illustrating a method for manufacturing an EEPROM cell according to the prior art.

2A to 2H are cross-sectional views illustrating a method of manufacturing an EEPROM cell according to the present invention.

   -Explanation of symbols for the main parts of the drawings-

200 silicon substrate 202 tunnel oxide film

204: floating gate polysilicon 206: upper oxide film

208: hard mask 210: floating gate

212: oxide film 214: nitride film

216 control gate polysilicon 218 gate oxide film

220: control gate polysilicon

The present invention relates to a method for manufacturing an EEPROM cell, and more particularly, to an EEPROM cell manufacturing method for forming a profile of a control gate to be a vertical profile to secure an area of an LDD spacer to prevent an increase in breakdown voltage of a junction region. It is about.

The EEPROM can write and erase data by electrically changing the charges of the devices constituting the chip. The EEPROM can also read and write data, and can be reprogrammed as embedded in the system. Programming in the EEPROM is possible by generating channel hot eletrons on the drain side and accumulating the electrons in the floating gate to increase the threshold voltage of the cell transistors. It is possible to lower the threshold voltage of the cell transistor by generating a high voltage between the floating gate and the electrons accumulated in the floating gate.

The EEPROM cell requires one select transistor in each unit cell to perform write / erase operation in units of 8 bits, and the selection transistor used here uses a first polysilicon. A floating gate of the EEPROM cell and a control gate of the EEPROM cell using the second polysilicon.

Such a control gate of the EEPROM cell has a rounded profile, which causes a problem in that the LDD spacer remains small at the time of subsequent LDD spacer formation, thereby lowering the breakdown voltage characteristic of the cell junction.

Hereinafter, with reference to the accompanying drawings will be described in detail the problem of the prior art EEPROM cell manufacturing method.

1A to 1I are cross-sectional views illustrating a method for manufacturing an EEPROM cell according to the prior art.

First, as shown in FIG. 1A, a tunnel oxide film 102, a floating gate polysilicon 104, an upper oxide film / nitride film 106, and a hard mask oxide film 108 are sequentially deposited on the silicon substrate 100.

Then, after forming a floating gate 110 as shown in FIG. 1B by performing a photo and etching process, an oxide film 112 and a nitride film 114 are deposited on the entire surface as shown in FIG. 1C.

After the dry etching process, the sidewall oxide film 112 'and the sidewall nitride film 114' are formed only on the floating gate sidewalls as shown in FIG. 1D. As shown, the hard mask oxide film 108 is partially lost.

After the cleaning process is performed, as shown in FIG. 1F, the gate oxide layer 116 for the high voltage region is deposited and the control gate polysilicon 118 is deposited.

Subsequently, a control gate etching process is performed to form a low-concentration n-type impurity after forming a gate in the form of a spacer on the side of the floating gate as shown in FIG. 1G.                         

Thereafter, a LDD spacer 120 is formed by performing a dry etching process after depositing a nitride film for the LDD spacer. At this time, as shown in FIG. 1H, since the profile of the control gate is round, the LDD spacer remains too small. do. After the LDD spacer is formed, a high concentration of n-type impurity is implanted. However, the LDD spacer is formed so small that the breakdown voltage of the cell junction is lowered and the leakage current also increases.

The present invention for solving the above problems is to form a hard mask as a nitride film to increase the height of the control gate profile to form a vertical profile to secure the area of the LDD spacer to prevent the breakdown voltage increase in the junction region The present invention provides a method for manufacturing an EEPROM cell.

The present invention for realizing the above object comprises the steps of depositing a tunnel oxide film, a floating gate polysilicon, an upper oxide film on a silicon substrate; Forming the hard mask thickly; Forming a floating gate by photolithography and etching processes on the hard mask, the upper oxide layer, the floating gate polysilicon, and the tunnel oxide layer; Depositing an oxide film and a nitride film on the entire surface of the resultant of forming the floating gate; Etching the nitride film and the oxide film to form a sidewall oxide film and a sidewall nitride film on a sidewall of the floating gate; Cleaning the resultant of forming the sidewall nitride film and the sidewall oxide film; Performing the cleaning process and depositing a gate oxide film for a high voltage region and then depositing control gate polysilicon; Etching the control gate polysilicon to form a control gate having a vertical profile.

In the method for manufacturing an EEPROM cell according to the present invention, the hard mask is formed of a nitride film, or a double structure of an oxide film and a nitride film, thereby preventing the oxide film from being lost during the cleaning process as well as preventing the nitride film from capping and hard mask height. By increasing the control gate is formed to be a vertical profile to secure the proper area of the LDD spacer.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same symbols and names.

2A to 2H are cross-sectional views illustrating a method of manufacturing an EEPROM cell according to the present invention.

First, as shown in FIG. 2A, a tunnel oxide film 202, a floating gate polysilicon 204, an upper oxide film 206, and a hard mask 208 nitride film are sequentially deposited on the silicon substrate 200, and the nitride film ( 208 adjusts the height in consideration of the profile of subsequent control gates. In this case, the hard mask may be formed of a double structure of an oxide film and a nitride film instead of the nitride film.

Then, after forming a floating gate 210 as shown in FIG. 2B by performing a photo and etching process, an oxide film 212 and a nitride film 214 are deposited on the entire surface as shown in FIG. 2C.

Then, the dry etching process is performed to form the sidewall oxide film 212 'and the sidewall nitride film 214' only on the floating gate sidewalls as shown in FIG. 2D, and then the cleaning process is performed. Otherwise, since the nitride film is used as the hard mask, the hard mask is not lost.

After the cleaning process is performed, as shown in FIG. 2E, the gate oxide layer 216 for the high voltage region is deposited and the control gate polysilicon 218 is deposited.

Subsequently, a control gate etching process is performed to form a low-concentration n-type impurity after the gate is formed in the form of a spacer on the side of the floating gate as shown in FIG. 2F. At this time, the height is increased by using a nitride film as the hard mask, so that the vertical control section A is formed unlike the conventional control gate.

After that, a LDD spacer 220 is formed by performing a dry etching process after depositing a nitride film for the LDD spacer. In this case, as shown in FIG. 2G, a vertical section occurs in the profile of the control gate so that the LDD spacer has an appropriate area. It is secured.

After forming the LDD spacer, as shown in FIG. 2H, a high concentration n-type impurity is implanted, and the LDD spacer is secured in an appropriate area to prevent the breakdown voltage of the cell junction from decreasing, and also to reduce the off leakage current during erasing.

As described above, the present invention can prevent the breakdown voltage of the junction region from being lowered by forming the LDD spacer of the EEPROM cell large, and can be turned off by erasing the distance due to vertical diffusion relatively to the channel region of the high concentration junction region. There is an advantage that can reduce the leakage current.

Claims (8)

Forming a tunnel oxide film and a floating gate polysilicon on the silicon substrate; Sequentially depositing an upper oxide film and a hard mask nitride film on the floating gate polysilicon; Forming a floating gate by photolithography and etching processes on the hard mask nitride layer, the upper oxide layer, the floating gate polysilicon, and the tunnel oxide layer; Forming a structure in which sidewall oxide films and sidewall nitride films are stacked on the floating gate sidewalls; Cleaning the resultant of forming the sidewall nitride film and the sidewall oxide film; Performing the cleaning process, depositing a gate oxide film for a high voltage region, and then depositing control gate polysilicon; And Etching the control gate polysilicon to form control gates on both sidewalls of the floating gate, wherein the control gate is formed such that a portion of one side of the control gate not in contact with the floating gate has a vertical profile; EEPROM cell manufacturing method characterized in that. The method of claim 1, The hard mask is formed of a nitride film or a double structure of an oxide film and a nitride film. The method of claim 1, And the control gate is formed such that an upper surface is positioned higher than an upper surface of the floating gate. The method of claim 1, After the forming of the control gate, implanting an n-type impurity of a first concentration into the silicon substrate using the control gate with an ion implantation mask; Forming an LDD spacer on sidewalls of the control gate having the vertical profile; And And implanting an n-type impurity of a second concentration relatively higher than the n-type impurity of the first concentration into the silicon substrate using the LDD spacer as an ion implantation mask. delete A tunnel oxide film and a floating gate stacked on a silicon substrate; A hard mask formed on the floating gate through an upper oxide film; A dielectric layer formed on the floating gate sidewalls and the substrate on both sides of the floating gate; A control gate formed on both sides of the floating gate on the dielectric layer in the form of a spacer, and a portion of one side not in contact with the floating gate having a vertical profile; And And an LDD spacer formed on the sidewall of the control gate. The method of claim 6, The dielectric film is an EEPROM cell formed of a structure in which a sidewall nitride film and a sidewall oxide film are stacked. The method of claim 6, And the control gate is formed such that an upper surface thereof is higher than an upper surface of the floating gate.

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