CN108389897B - Gate spacer and method of forming the same - Google Patents
Gate spacer and method of forming the same Download PDFInfo
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- CN108389897B CN108389897B CN201810107090.2A CN201810107090A CN108389897B CN 108389897 B CN108389897 B CN 108389897B CN 201810107090 A CN201810107090 A CN 201810107090A CN 108389897 B CN108389897 B CN 108389897B
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
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Abstract
本发明公开了一种栅极侧墙，包括：由栅介质层和多晶硅栅叠加而成的栅极结构；自对准形成于多晶硅栅侧面的侧墙；多晶硅栅的顶部被回刻一定厚度且回刻后的多晶硅栅的顶部表面低于侧墙的顶部表面；层间介质层和穿过层间介质层的接触孔；延伸到多晶硅栅的顶部表面上方的侧墙部分作为多晶硅栅和邻近的接触孔之间的阻挡层，用于防止多晶硅栅和邻近的所述接触孔产生击穿。本发明公开了一种栅极侧墙的形成方法。本发明能对多晶硅栅的顶部进行保护，防止多晶硅栅顶部和邻近的接触孔之间产生击穿，提高器件的性能；多晶硅栅的回刻能通过自对准实现，不需要增加额外的光罩，工艺成本低；不会对多晶硅栅的厚度产生影响，能使多晶硅栅的性能得到很好的保证。
The invention discloses a gate sidewall, comprising: a gate structure formed by superimposing a gate dielectric layer and a polysilicon gate; a sidewall self-aligned on the side of the polysilicon gate; the top of the polysilicon gate is engraved back to a certain thickness and The top surface of the polysilicon gate after etchback is lower than the top surface of the spacer; the interlayer dielectric layer and the contact holes passing through the interlayer dielectric layer; the part of the spacer extending above the top surface of the polysilicon gate serves as the polysilicon gate and the adjacent A barrier layer between the contact holes is used to prevent breakdown of the polysilicon gate and the adjacent contact holes. The invention discloses a method for forming a gate sidewall. The invention can protect the top of the polysilicon gate, prevent breakdown between the top of the polysilicon gate and the adjacent contact holes, and improve the performance of the device; the etching back of the polysilicon gate can be realized by self-alignment without adding an additional mask , the process cost is low; the thickness of the polysilicon gate is not affected, and the performance of the polysilicon gate can be well guaranteed.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a grid side wall; the invention also relates to a forming method of the grid side wall.
Background
With the continuous reduction of the size of the device, the size between the grid electrodes is smaller and smaller, and the size of the contact hole is smaller and smaller; in the existing silicon nitride gate side wall, the problem that the interlayer dielectric layer is not filled enough to form a cavity is caused by the reduction of the size between the gate and the gate, so people invent the L-shaped gate side wall to improve the filling of the interlayer dielectric layer; however, as the size of the device is reduced, the filling of the interlayer dielectric layer of the L-shaped gate sidewall is still a problem.
In addition, with the continuous reduction of the size of the contact hole, the cost of the photomask is higher and higher, and meanwhile, the exposure of the contact hole is more and more difficult; meanwhile, the distance between the contact hole and the grid is smaller and smaller due to the reduction of the size of the device, and the contact hole and the grid are easy to break down due to the fluctuation of the process capability; in addition, the distance between the bottom of the contact hole and the gate has a great influence on the disturb (disturb) performance of the memory. The problems with the prior art structure will now be described with reference to fig. 1:
fig. 1 is a schematic structural diagram of a conventional gate sidewall; a corresponding well region 102 is formed on a semiconductor substrate, such as a silicon substrate 101, and a gate structure is formed on the surface of the well region 102, wherein the gate structure comprises a gate dielectric layer, such as a gate oxide layer 103 and a polysilicon gate 104, which are sequentially stacked. The surface of the well region 102 covered by the polysilicon gate 104 is used to form a channel. Field oxygen such as shallow trench field oxygen is also formed on the silicon substrate 101.
A side wall 105 is formed on the side surface of the polysilicon gate 104, the side wall 105 is usually a silicon nitride side wall, the side wall 105 in fig. 1 is in an L-shaped structure, a silicon nitride layer and a silicon oxide layer are sequentially deposited, then a silicon oxide side wall and a silicon nitride side wall are formed by adopting general etching, and then the silicon oxide side wall is removed, so that the side wall 105 composed of the silicon nitride side wall is formed.
The interlayer dielectric layer 106 will be formed to cover the surface of the semiconductor substrate 101 of the gate structure.
Active drain regions are generally formed on both sides of the polysilicon gate 104, contact holes 107 are respectively formed in the source drain regions and the top of the polysilicon gate 104, and the tops of the contact holes 107 are respectively connected to metal electrode structures composed of front metal layers, such as a source electrode, a drain electrode and a metal gate. Contact holes 107 on both sides of the polysilicon gate 104 are shown in fig. 1.
As the device size shrinks, the spacing between the polysilicon gates 104 decreases, which results in a smaller spacing between the contact holes 107 adjacent to the polysilicon gates 104 and the polysilicon gates 104, so that breakdown between the contact holes 107 and the corresponding polysilicon gates 104 can easily occur, mainly at the top of the dotted circle 108, where the spacing between the contact holes 107 and the corresponding polysilicon gates 104 is d 101.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a grid side wall which can protect the top of a polysilicon gate, prevent the top of the polysilicon gate and an adjacent contact hole from being punctured and improve the performance of a device. Therefore, the invention also provides a forming method of the grid side wall.
In order to solve the above technical problem, the gate sidewall provided by the present invention includes:
the grid structure comprises a grid dielectric layer and a polysilicon grid which are overlapped on the surface of the semiconductor substrate.
And the side wall is formed on the side surface of the polysilicon gate in a self-alignment manner.
The top of the polysilicon gate is etched back to a certain thickness, and the top surface of the etched-back polysilicon gate is lower than the top surface of the side wall.
The contact hole penetrates through the interlayer dielectric layer; the part of the side wall extending to the position above the top surface of the polysilicon gate is used as a barrier layer between the polysilicon gate and the adjacent contact hole and used for preventing the polysilicon gate and the adjacent contact hole from being broken down.
The further improvement is that the gate dielectric layer is a gate oxide layer.
The further improvement is that the thickness of the polysilicon gate after the back etching is equal to a target value, and the thickness of the polysilicon gate before the back etching is set according to the target value and is increased on the basis of the target value.
In a further improvement, the thickness of the polysilicon gate before the etch back is the target value plus
In a further improvement, the sidewall spacers are silicon nitride sidewall spacers.
In order to solve the technical problem, the method for forming the gate sidewall provided by the invention comprises the following steps:
step one, forming a grid structure, wherein the grid structure comprises a grid dielectric layer and a polysilicon grid which are overlapped on the surface of a semiconductor substrate.
And step two, forming a side wall on the side surface of the polysilicon gate.
And step three, forming a protective layer and carrying out back etching on the protective layer, wherein the top surface of the protective layer after back etching is lower than the top surface of the side wall.
And fourthly, etching the polysilicon gate by taking the protective layer as a mask and etching the top surface of the polysilicon gate to be lower than the top surface of the side wall. And then removing the protective layer.
And step five, forming an interlayer dielectric layer.
And sixthly, forming a contact hole penetrating through the interlayer dielectric layer, wherein the part of the side wall extending to the upper part of the top surface of the polysilicon gate is used as a barrier layer between the polysilicon gate and the adjacent contact hole and is used for preventing the polysilicon gate and the adjacent contact hole from being broken down.
In a further improvement, the material of the protective layer in step three is photoresist, and the step of forming the protective layer includes:
and 31, gluing to form the photoresist, wherein the thickness of the photoresist is greater than that of the polysilicon gate.
And 32, etching the photoresist to ensure that the etched photoresist is only remained in the bottom area between the polysilicon gates and the remained photoresist is used as the protective layer.
The further improvement is that the interlayer dielectric layer is formed by overlapping a first dielectric layer and a second dielectric layer, and the forming step comprises:
and step 51, forming the first dielectric layer by adopting a high-density plasma chemical vapor deposition process, wherein the first dielectric layer completely fills the interval region.
And step 52, flattening the first dielectric layer by adopting a chemical mechanical polishing process.
And 53, depositing the second dielectric layer.
In a further improvement, in step 53, a plasma enhanced chemical vapor deposition process is used to form the second dielectric layer.
In a further improvement, the step of forming the gate structure in the first step includes:
and 11, sequentially forming the gate dielectric layer and the polysilicon gate on the surface of the semiconductor substrate.
And step 12, defining a forming area of the gate structure by photoetching.
And step 13, removing the polysilicon gate and the gate dielectric layer outside the forming area of the gate structure, and overlapping the gate dielectric layer and the polysilicon gate reserved in the forming area of the gate structure to form the gate structure.
The further improvement is that the thickness of the polysilicon gate after etching in the fourth step is equal to a target value, and the thickness of the polysilicon gate in the first step is set according to the target value and is increased on the basis of the target value.
In a further improvement, the thickness of the polysilicon gate in the first step is increased based on the target value
Thus obtaining the product.
In a further improvement, in the second step, the side wall is a silicon nitride side wall.
In a further improvement, the step of forming the sidewall comprises:
and 21, depositing a third silicon nitride layer and a fourth silicon oxide layer in sequence.
And step 22, adopting a general etching process to sequentially etch the fourth silicon oxide layer and the third silicon nitride layer to form a silicon oxide side wall and a silicon nitride side wall on the side surface of the polysilicon gate, wherein the silicon nitride side wall is L-shaped.
And 23, removing the silicon oxide side wall, wherein the silicon nitride side wall forms an L-shaped side wall.
In a further improvement, the step of forming the sidewall comprises:
step 21, depositing a third silicon nitride layer.
And step 22, adopting a general etching process to sequentially etch the third silicon nitride layer on the side surface of the polysilicon gate to form a silicon nitride side wall, wherein the silicon nitride side wall forms a D-shaped side wall.
The invention sets the relation between the grid side wall, namely the side wall on the side surface of the polysilicon grid and the polysilicon grid, the side wall can be formed on the side surface of the polysilicon grid in a self-aligning way, the polysilicon grid is etched back for a certain thickness after the side wall is defined in a self-aligning way, so that the top surface of the polysilicon grid after etching back is lower than the top surface of the side wall, the top end of the side wall can protrude above the top surface of the polysilicon grid, and the top end part of the side wall protruding above the top surface of the polysilicon grid can be used as a barrier layer between the polysilicon grid and an adjacent contact hole, thereby preventing the breakdown problem generated at the top of the polysilicon grid when the distance between the polysilicon grid and the adjacent contact hole is smaller, protecting the top of the polysilicon grid, preventing the breakdown between the top of the polysilicon grid and the adjacent contact hole, and improving the performance of a device.
Meanwhile, the back etching of the polysilicon gate can be realized through self-alignment without adding an additional photomask, so the process cost of the invention is low.
Meanwhile, the thickness of the polysilicon gate after the back etching is made to be the thickness corresponding to the target value by increasing the thickness of the polysilicon gate in advance, so the thickness of the polysilicon gate is not influenced by the method, and the performance of the polysilicon gate is well ensured.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic structural diagram of a conventional gate sidewall;
FIG. 2 is a schematic structural diagram of a gate sidewall according to an embodiment of the present invention;
fig. 3A-3E are schematic diagrams of device structures in various steps of a method according to an embodiment of the invention.
Detailed Description
As shown in fig. 2, it is a schematic structural diagram of the gate sidewall spacer 5 according to an embodiment of the present invention; the gate side wall 5 of the embodiment of the invention comprises:
the grid structure comprises a grid dielectric layer 3 and a polysilicon grid 4 which are overlapped on the surface of the semiconductor substrate 1.
Preferably, the semiconductor substrate 1 is a silicon substrate. The gate dielectric layer 3 is a gate oxide layer.
The surface of the semiconductor substrate 1 is provided with a well region 2, the well region 2 is divided into an N-type well region and a P-type well region according to the type of a corresponding MOS transistor, the forming region of an NMOS tube corresponds to the forming of the P-type well region, and the forming region of a PMOS tube corresponds to the forming of the N-type well region. A step of forming field oxide, such as shallow trench field oxide, in the semiconductor substrate 1, the field oxide isolating the active region of the device.
And the side wall 5 is formed on the side surface of the polysilicon gate 4 in a self-alignment manner. Preferably, the sidewall spacers 5 are silicon nitride sidewall spacers 5.
The top of the polysilicon gate 4 is etched back to a certain thickness, and the top surface of the etched back polysilicon gate 4 is lower than the top surface of the side wall 5. The thickness of the polysilicon gate 4 after the back etching is equal to a target value, and the thickness of the polysilicon gate 4 before the back etching is set according to the target value and is increased on the basis of the target value. Preferably, the thickness of the polysilicon gate 4 before the etching back is the target value plus
Since the thickness of the polysilicon gate 4 after the etch back is equal to the target value, the device according to the embodiment of the invention does not adversely affect the performance of the polysilicon gate 4 itself.
An interlayer dielectric layer 6 and a contact hole 7 penetrating through the interlayer dielectric layer 6; the part of the side wall 5 extending above the top surface of the polysilicon gate 4 serves as a barrier layer between the polysilicon gate 4 and the adjacent contact hole 7, and is used for preventing the polysilicon gate 4 and the adjacent contact hole 7 from being broken down. The position where the polysilicon gate 4 and the adjacent contact hole 7 are broken down usually occurs in the region corresponding to the dotted circle 8, and the distance d1 between the polysilicon gate 4 and the adjacent contact hole 7 is smaller at this position, but in the embodiment of the present invention, the side wall 5 is more protruded than the surface of the polysilicon gate 4, and a barrier layer can be formed between the polysilicon gate 4 and the adjacent contact hole 7 by using the protruded side wall 5, and the barrier layer can improve the voltage endurance capability between the polysilicon gate 4 and the adjacent contact hole 7 at the position of the dotted circle 8.
As can be seen from the above, in the embodiment of the present invention, the relationship between the gate sidewall 5, i.e., the sidewall 5 on the side of the polysilicon gate 4, and the polysilicon gate 4 is specially set, the sidewall 5 can be formed on the side of the polysilicon gate 4 in a self-aligned manner, the polysilicon gate 4 is etched back by a certain thickness after the sidewall 5 is defined in a self-aligned manner, so that the top surface of the polysilicon gate 4 after etching back is lower than the top surface of the sidewall 5, so that the top end of the sidewall 5 protrudes above the top surface of the polysilicon gate 4, and the top end portion of the sidewall 5 protruding above the top surface of the polysilicon gate 4 can be used as a barrier layer between the polysilicon gate 4 and the adjacent contact hole 7, thereby preventing the breakdown problem generated at the top of the polysilicon gate 4 when the distance between the polysilicon gate 4 and the adjacent contact hole 7 is small, so that the embodiment of the present invention can protect the top of the polysilicon gate 4, and prevent the breakdown generated between the top of the polysilicon gate 4 and the adjacent contact, the performance of the device is improved.
Meanwhile, the back etching of the polysilicon gate 4 in the embodiment of the invention can be realized through self-alignment without adding an additional photomask, so that the process cost is low in the embodiment of the invention.
Meanwhile, the thickness of the polysilicon gate 4 after the back etching is made to be the thickness corresponding to the target value by increasing the thickness of the polysilicon gate 4 in advance, so that the embodiment of the invention does not influence the thickness of the polysilicon gate 4, and the performance of the polysilicon gate 4 is well ensured.
As shown in fig. 3A to fig. 3E, which are schematic views of device structures in the steps of the method according to the embodiment of the present invention, the method for forming the gate sidewall spacer according to the embodiment of the present invention includes the following steps:
step one, as shown in fig. 3A, a gate structure is formed, and the gate structure includes a gate dielectric layer 3 and a polysilicon gate 4 which are overlapped on the surface of a semiconductor substrate 1.
Preferably, the semiconductor substrate 1 is a silicon substrate.
In an embodiment of the present invention, the step of forming the gate structure includes:
and 11, forming a well region 2 on the semiconductor substrate 1, wherein the well region 2 is divided into an N-type well region and a P-type well region according to the type of the corresponding MOS transistor, the forming region of the NMOS transistor corresponds to the forming of the P-type well region, and the forming region of the PMOS transistor corresponds to the forming of the N-type well region.
And then, a step of forming field oxygen such as shallow trench field oxygen is further included, and the field oxygen isolates the active region of the device.
And sequentially forming the gate dielectric layer 3 and the polysilicon gate 4 on the surface of the semiconductor substrate 1. Preferably, the gate dielectric layer 3 is a gate oxide layer.
And step 12, defining a forming area of the gate structure by photoetching.
And step 13, removing the polysilicon gate 4 and the gate dielectric layer 3 outside the forming area of the gate structure, and overlapping the gate dielectric layer 3 and the polysilicon gate 4 reserved in the forming area of the gate structure to form the gate structure.
Step two, as shown in fig. 3B, a side wall 5 is formed on the side surface of the polysilicon gate 4.
The side wall 5 is a silicon nitride side wall.
In the embodiment of the present invention, the forming step of the side wall 5 includes:
and 21, depositing a third silicon nitride layer and a fourth silicon oxide layer in sequence.
And step 22, adopting a general etching process to sequentially etch the fourth silicon oxide layer and the third silicon nitride layer to form a silicon oxide side wall and a silicon nitride side wall on the side surface of the polysilicon gate 4, wherein the silicon nitride side wall is in an L shape.
And 23, removing the silicon oxide side wall, wherein the silicon nitride side wall forms the L-shaped side wall 5.
In other embodiments can also be: the forming step of the side wall 5 includes:
step 21, depositing a third silicon nitride layer.
And step 22, adopting a general etching process to sequentially etch the third silicon nitride layer on the side surface of the polysilicon gate 4 to form a silicon nitride side wall, wherein the side wall 5 is formed by the silicon nitride side wall.
Preferably, after the side walls 5 are formed in the second step, a step of performing source-drain injection to form a source region and a drain region on two sides of the polysilicon gate 4 is further included, and the source region and the drain region are respectively self-aligned to the corresponding side walls 5.
The method also comprises the step of forming a cobalt alloy on the surfaces of the source region and the drain region after the source region and the drain region are formed.
Step three, as shown in fig. 3C, forming a protection layer 201; as shown in fig. 3D, the protection layer 201 is etched back, and the top surface of the protection layer 201 after etching back is lower than the top surface of the sidewall 5.
In an embodiment of the present invention, the material of the protection layer 201 is a photoresist, and the step of forming the protection layer 201 includes:
and 31, gluing to form the photoresist, wherein the thickness of the photoresist is greater than that of the polysilicon gate 4.
And 32, etching the photoresist to ensure that the etched photoresist only remains in the bottom area between the polysilicon gates 4 and the remained photoresist is used as the protective layer 201.
Step four, as shown in fig. 3E, the protection layer 201 is used as a mask to etch the polysilicon gate 4, and the top surface of the polysilicon gate 4 is etched to be lower than the top surface of the side wall 5. The protective layer 201 is then removed. The protective layer 201 composed of the photoresist can be removed simultaneously during the etching back process of the polysilicon gate 4.
In the embodiment of the present invention, the thickness of the polysilicon gate 4 after etching in the fourth step is equal to a target value, i.e., h2 in fig. 3E, and the thickness of the polysilicon gate 4 in the first step, i.e., h1 in fig. 3D, is set according to the target value h2 and is increased based on the target value h 2. Preferably, the thickness h1 of the polysilicon gate 4 in the first step is increased based on the target value h2
Thus obtaining the product.
And step five, forming an interlayer dielectric layer 6.
In the embodiment of the present invention, the interlayer dielectric layer 6 is formed by stacking a first dielectric layer and a second dielectric layer, and the forming step includes:
and step 51, forming the first dielectric layer by adopting a high-density plasma chemical vapor deposition process, wherein the first dielectric layer completely fills the interval region.
And step 52, flattening the first dielectric layer by adopting a chemical mechanical polishing process.
And 53, depositing the second dielectric layer.
Preferably, in step 53, a plasma enhanced chemical vapor deposition process is used to form the second dielectric layer. The interlayer dielectric layer 6 is a silicon dioxide layer.
And sixthly, forming a contact hole 7 penetrating through the interlayer dielectric layer 6, wherein the part of the side wall 5 extending to the upper part of the top surface of the polysilicon gate 4 is used as a barrier layer between the polysilicon gate 4 and the adjacent contact hole 7, and the barrier layer is used for preventing the polysilicon gate 4 and the adjacent contact hole 7 from being broken down.
In the embodiment of the invention, the sixth step comprises the following sub-steps:
and 61, defining a forming area of the contact hole 7 by photoetching.
And 62, removing the interlayer dielectric layer 6 in the forming area of the contact hole 7 by adopting a dry etching process.
And 63, filling metal in the forming area of the contact hole 7 to form the contact hole 7.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (9)
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| CN113809004A (en) * | 2021-09-17 | 2021-12-17 | 恒烁半导体(合肥)股份有限公司 | Manufacturing method, circuit and application of a memory |
| CN114038752A (en) * | 2021-10-09 | 2022-02-11 | 上海华力集成电路制造有限公司 | High-voltage MOSFET device and manufacturing method thereof |
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| US7633125B2 (en) * | 2007-08-31 | 2009-12-15 | Intel Corporation | Integration of silicon boron nitride in high voltage and small pitch semiconductors |
| JP2012099517A (en) * | 2010-10-29 | 2012-05-24 | Sony Corp | Semiconductor device and method of manufacturing the same |
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| KR20050095429A (en) * | 2004-03-26 | 2005-09-29 | 매그나칩 반도체 유한회사 | Method for manufacturing eeprom cell |
| CN102427031A (en) * | 2011-11-29 | 2012-04-25 | 上海华力微电子有限公司 | Method for manufacturing polycrystalline silicon side wall |
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