KR101085450B1 - Thin film transistor substrate and its manufacturing method - Google Patents

Abstract

The present invention relates to a thin film transistor substrate and a method of manufacturing the same. The thin film transistor substrate according to the present invention is characterized in that it comprises an aluminum layer and the upper molybdenum layer located on the aluminum layer having a thickness of 10 to 40% of the thickness of the aluminum layer. Thereby, the hillock which arises in an aluminum wiring can be reduced.

Description

Thin film transistor substrate and its manufacturing method {TFT SUBSTRATE AND MANUFACTURING METHOD OF THE SAME}

1A to 1C are diagrams for explaining the wiring when the upper molybdenum layer has a first thickness,

2A to 2C are diagrams for explaining the wiring when the upper molybdenum layer has a second thickness,

3A to 3C are diagrams for explaining wiring when the upper molybdenum layer has a third thickness,

4 is a view for explaining the etching rate change of molybdenum and aluminum according to the thickness ratio of the upper molybdenum layer / aluminum layer,

5A and 5B are optical micrographs of Experimental Example 1 of Table 1,

6A and 6B are optical micrographs of Experimental Example 2 of Table 1;

7A and 7B are optical micrographs of Experiment 3 of Table 1;

8 is an optical microscope picture of Experiment 4 of Table 1;

9 is an optical micrograph for Experiment 5 of Table 1,

10A and 10B are optical micrographs of Experimental Example 6 of Table 1,

11 is a plan view of a thin film transistor substrate according to a first embodiment of the present invention,

12 is a cross-sectional view taken along XII-XII of FIG. 11,

13 to 16 are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate according to a first embodiment of the present invention.

17 is a plan view of a thin film transistor substrate according to a second embodiment of the present invention,

18 is a cross-sectional view taken along the line VII-VII of FIG. 17,

19 is a cross-sectional view taken along the line VII-VII of FIG. 17,

20A to 27B are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate according to a second embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

22 gate line 26 gate electrode

62: data line 65: source electrode

66: drain electrode

The present invention relates to a thin film transistor substrate and a method of manufacturing the same.

The liquid crystal display device includes a liquid crystal display panel in which liquid crystal is injected between the thin film transistor substrate and the color filter substrate. Since the liquid crystal display panel is a non-light emitting device, a backlight unit for supplying light is located at the back of the thin film transistor substrate. Light transmitted from the backlight is adjusted according to the arrangement of liquid crystals.

Recent liquid crystal displays require large screen area, high resolution, and high aperture ratio. As a result, the wirings (gate wirings and data wirings) formed on the thin film transistor substrate are lengthening, while the width thereof is decreasing. In this trend, the high resistivity of the wiring material causes an RC delay, which seriously distorts the screen.

Metals such as chromium (Cr) and molybdenum-tungsten alloys (MoW), which have been used as wiring materials, have been difficult to be applied to liquid crystal display devices of 20 inches or more due to high resistivity of 10 µΩ / cm or more. As a result, there is an increasing demand to use a wiring material having a small specific resistance.

Examples of metals with low specific resistance include silver, copper, and aluminum. Among them, silver and copper have significantly lower adhesion to the glass substrate. In particular, copper penetrates into the amorphous silicon to destroy the device, or conversely, amorphous silicon penetrates into the copper to increase the resistivity value.

Due to these disadvantages of silver and copper, the most commonly used wiring materials are based on aluminum. Aluminum has the advantage that the specific resistance is very low, such as 3μΩ / ㎝, easy wiring forming process and low cost.

However, aluminum has a problem of being easily oxidized or disconnected due to weak corrosion resistance to chemicals. In order to compensate for this, molybdenum having high corrosion resistance to chemicals is formed as an upper layer.

By the way, in the double layer structure of an aluminum layer / molybdenum layer, there exists a problem that hillock generate | occur | produces.

 It is therefore an object of the present invention to provide a thin film transistor substrate having aluminum wiring with reduced hillock generation.

Another object of the present invention is to provide a method of manufacturing a thin film transistor substrate having aluminum wiring with reduced hillock generation.

Another object of the present invention is to provide a liquid crystal display device having aluminum wiring with reduced hillock generation.

The above object can be achieved by a thin film transistor substrate comprising an aluminum layer and an upper molybdenum layer located on the aluminum layer and having a thickness of 10% to 40% of the aluminum layer.

It is preferable that the aluminum layer and the upper molybdenum layer are in direct contact.

The thickness of the upper molybdenum layer is preferably 20% to 27% of the thickness of the aluminum layer.

The upper molybdenum layer further comprises at least one element selected from the group consisting of tungsten (W), zirconium (Zr), tantalum (Ta), titanium (Ti), niobium (niobium), nitrogen (nitrogen). desirable.

It is preferable to further include a lower molybdenum layer formed under the aluminum layer.

The above object is a thin film transistor substrate comprising a gate wiring and a data wiring, wherein at least one of the gate wiring and the data wiring has a thickness of 10% to 40% of the thickness of the aluminum layer and the aluminum layer sequentially formed. Branches can also be achieved by including an upper molybdenum layer.

Another object of the present invention is the step of depositing an aluminum layer on an insulating substrate, the step of depositing an upper molybdenum layer having a thickness of 10% to 40% of the thickness of the aluminum layer on the aluminum layer, and the aluminum layer And patterning the molybdenum layer to form a wiring, which may be achieved by a method of manufacturing a thin film transistor substrate.

The method may further include sequentially forming an insulating film, a semiconductor layer, and an ohmic contact layer on the wiring by a plasma enhanced chemical vapor deposition method.

Another object of the present invention includes a gate wiring and a data wiring, wherein at least one of the gate wiring and the data wiring has a thickness of 10% to 40% of the aluminum layer and the thickness of the aluminum layer sequentially formed. It can be achieved by a liquid crystal display device including a first substrate including an upper molybdenum layer, a second substrate facing the first substrate, and a liquid crystal layer positioned between the first substrate and the second substrate. .

In wet etching, two aspects are important in controlling the shape of a multilayer wiring. The first is the etch rate of a single metal layer and the second is the standard reduction potential of each metal layer.

In the etching rate of a single metal layer for an etchant including phosphoric acid, nitric acid and acetic acid used for wet etching, the molybdenum layer is twice as fast as the aluminum layer.

However, in the double layer having the aluminum layer as the lower layer and the molybdenum layer as the upper layer, the etching rate of the molybdenum layer is slow at the interface. This is because the standard reduction potential between the metal layers is different. When wet etching is performed on two bonded metal layers, a metal having a relatively small standard reduction potential (anode) gives electrons to a metal having a large standard reduction potential (cathode). This reduces the etching rate of the cathode metal than in the case of a single layer. This is called the galvanic effect.

The standard reduction potential of aluminum is -1.76V and that of molybdenum is -0.2V. In the case of the molybdenum layer / aluminum layer (Mo / Al), an aluminum layer having a small standard reduction potential becomes an anode to supply electrons to the molybdenum layer, which is a cathode. The molybdenum layer supplied with electrons has a lower etch rate than the single layer.

On the other hand, the causes of the hillock occurring in the aluminum wiring are as follows.

In the manufacture of the thin film transistor substrate, after the formation of the aluminum wiring, an insulating film, a semiconductor layer, and the like are deposited by a plasma enhanced chemical vapor deposition (PECVD) method. The PECVD process is performed at a high temperature of about 300 ° C. or higher. In this process, aluminum moves through a grain boundary where aluminum has a compressive stress and diffuses well on the aluminum surface. An aluminum is called a hillock.

In the case of the molybdenum layer / aluminum layer double layer, the wiring is not easily tapered due to the galvanic effect and the hillock generation. In the present invention, the molybdenum layer / aluminum layer double layer is formed into a preferable shape by controlling the thickness ratio of the molybdenum layer and the aluminum layer.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

1A to 1C are diagrams for explaining the wiring when the upper molybdenum layer 3 has the first thickness d2.

As shown in FIG. 1A, an aluminum layer 2 and an upper molybdenum layer 3 are sequentially deposited on the insulating substrate 1. A patterned photosensitive film 4 is formed on the upper molybdenum layer 3. In this state, wet etching is performed to form wiring in the shape of the photosensitive film 4. The etchant etches the aluminum layer 2 and the upper molybdenum layer 3 which are not covered by the photoresist film 4 at the same time. Here, the thickness d1 of the aluminum layer 2 is formed relatively large compared with the thickness d2 of the upper molybdenum layer 3. As described, the aluminum layer 2 having a relatively small standard reduction potential becomes an anode to supply electrons to the upper molybdenum layer 3 having a large standard reduction potential.

In the upper molybdenum layer 3 which receives electrons from the aluminum layer 2, the etching rate decreases due to the galvanic effect. When the thickness d1 of the aluminum layer 2 is formed to be relatively large compared to the thickness d2 of the upper molybdenum layer 3, the upper molybdenum layer 3 receives relatively large electrons per unit mass, thereby greatly reducing the etching rate. do. As a result, the aluminum layer 2 is relatively etched to form a wiring as shown in FIG. 1B. The upper molybdenum layer 3 has an overhang A extending outward of the aluminum layer 2.

An insulating film 4 made of silicon nitride or the like, a semiconductor layer 5 made of amorphous silicon or the like, n + hydrogenated amorphous silicon doped with a high concentration of n-type impurities, or the like, as shown in FIG. The triple layers of resistive contact layers 6 made up are sequentially stacked. The triple layer is usually laminated by a plasma enhanced chemical vapor deposition (PECVD) method, wherein a high temperature of 300 ° C. or higher is applied to the wiring. In this process, the aluminum layer 2 has a compressive stress, and the hillocks 7 and 8 are generated. The hillocks 7 and 8 include side hillocks 7 laterally generated and top hillocks 8 upwardly. The upper molybdenum layer 3 also serves to cap the hillocks 7 and 8 generated in the aluminum layer 2, and the upper molybdenum layer 3 is formed by the small thickness d1 of the upper molybdenum layer 3. Through the hillocks (7, 8) will be formed. When the hill locks 7 and 8 are generated, a defect such as a short circuit between the wirings is generated and the reliability of the wiring is lowered.

In the wiring of FIG. 1C, since an overhang A is formed in the upper molybdenum layer 3, a triple layer stacked adjacent to the overhang A has a large stacking angle, resulting in step open. It may be. Step open also causes a short between the wires.

2A to 2C are diagrams for explaining the wiring when the upper molybdenum layer 3 has the second thickness d3. The thickness d3 of the upper molybdenum layer 3 is formed relatively larger than the first thickness d2.

As shown in FIG. 2A, electrons of the aluminum layer 2 are supplied to the upper molybdenum layer 3. Since the thickness d3 of the upper molybdenum layer 3 is relatively large, the number of electrons supplied per unit mass of the upper molybdenum layer 3 becomes small. Accordingly, the upper molybdenum layer 3 is more affected by the etching rate of the single metal layer than by the galvanic effect. As a result, the upper molybdenum layer 3 is more etched than the aluminum layer 2 to form a wiring as shown in FIG. 2B. In the upper part of the aluminum layer 2, the part B which is not covered by the upper molybdenum layer 3 is formed.

Triple layers are sequentially stacked on the wiring line as shown in FIG. 2B as shown in FIG. 2C. The stacking angle of the triple layer is reduced, reducing the possibility of step opening. On the other hand, a side heel lock 7 is generated in the portion B of the aluminum layer 2 that is not covered by the upper molybdenum layer 3, and light from the outside is reflected to cause staining on the screen.

3A to 3C are diagrams for explaining the wiring when the upper molybdenum layer has a third thickness d4. The thickness d4 of the upper molybdenum layer 3 has a value between the first thickness d2 and the second thickness d3.

As shown in FIG. 3A, electrons of the aluminum layer 2 are supplied to the upper molybdenum layer 3. By properly adjusting the thickness d4 of the upper molybdenum layer 3, the etching rate of the aluminum layer 2 and the upper molybdenum layer 3 can be similarly controlled by offsetting the effect of the galvanic effect and the difference in etching speed of the single metal layer. have. When the etching rates of the aluminum layer 2 and the upper molybdenum layer 3 are similar, a wiring as shown in FIG. 3B is formed. The aluminum layer 2 and the upper molybdenum layer 3 have a tapered shape.

Triple layers are sequentially stacked on the wiring line as shown in FIG. 3B as shown in FIG. 3C. The stacking angle of the triple layer is relatively small, reducing the possibility of step opening. On the other hand, the aluminum layer 2 is capped by the upper molybdenum layer 3, thereby reducing the occurrence of hillock.

As described above, by adjusting the thickness ratio of the aluminum layer 2 and the upper molybdenum layer 3, it is possible to reduce the occurrence of hillock. In addition, if the heel lock is prevented, the wiring has a tapered shape.

4, the etching rate of molybdenum and aluminum becomes the same in the thickness ratio of the specific molybdenum layer / aluminum layer, and the farther away from the thickness ratio, the difference occurs in the etching rate of molybdenum and aluminum. Specifically, when the thickness of the molybdenum layer 3 decreases, the etching rate of aluminum is faster than that of molybdenum, because the molybdenum layer having a small thickness is greatly affected by the galvanic effect. On the other hand, when the thickness of the molybdenum layer is increased, the etching rate of molybdenum is faster than that of aluminum because molybdenum is more affected by the etching rate of a single layer than the galvanic effect.

It can be seen from FIG. 4 that the etch rates of aluminum and molybdenum can be similar at appropriate molybdenum layer / aluminum layer thickness ratios.

Experimental Example

In order to find the molybdenum layer / aluminum layer thickness ratio in which the etching rate of aluminum and molybdenum are similar, and the hillock generation is suppressed, the following experiment was performed.

An aluminum layer and a molybdenum layer were sequentially deposited on the insulating substrate by a sputtering method. The thickness of the aluminum layer was constant at 3000 kPa and the thickness of the upper molybdenum layer was changed between 200 kPa and 1500 kPa.

Afterwards, the aluminum layer and the molybdenum layer were patterned by a wet etching method, and then a silicon nitride layer, an amorphous silicon layer, and an n + amorphous silicon hydride layer were sequentially deposited by using plasma enhanced chemical vapor deposition at about 320 ° C. The thickness of the silicon nitride layer was about 4500 kPa, the thickness of the amorphous silicon layer was about 2000 kPa, and the thickness of the n + amorphous silicon hydride layer was about 500 kPa.

After the triple layer deposition, the wiring state was observed using an optical microscope to observe the occurrence of the top hillock and the side hillock.

Table 1 shows the experimental conditions and whether the hillocks are generated, and FIGS. 5A to 10B show optical microscope images.

TABLE 1

5A and 5B, it can be seen that a lot of upper hillocks located on the wiring and side hilllocks protruding to the wiring side have occurred. This is because, in Experimental Example 1, the molybdenum layer / aluminum layer thickness ratio was 6.67%, so that hillock was generated through the molybdenum layer.

In Experimental Example 2, in which the molybdenum layer / aluminum layer thickness ratio was 10%, the heellock was greatly decreased, and in particular, the side heellock was sharply decreased. In Experimental Example 3 in which the molybdenum layer / aluminum layer thickness ratio was 20%, no lateral hillock was observed. This is because the thickness of the molybdenum layer becomes thick to prevent hillock.

In Experimental Example 4, in which the molybdenum layer / aluminum layer thickness ratio was 27%, the upper hillock was not observed while the small amount of side hillock was observed. In Experimental Example 5 and Experimental Example 6, in which the molybdenum layer / aluminum layer thickness ratio was 40% and 50%, respectively, the upper heellock still did not occur, while the side heellock increased, especially in Experimental Example 6. The upper hillock is more effectively prevented when the molybdenum layer becomes thicker. On the other hand, as the molybdenum layer / aluminum layer thickness ratio increases, the etching rate of the molybdenum layer increases, so that a part of the upper part of the aluminum layer that is not covered by the molybdenum layer is generated.

It can be seen from the above experimental example that the molybdenum layer / aluminum layer thickness ratio is preferably 10% to 40% in order to reduce hillock. In particular, it can be seen that the thickness ratio of the molybdenum layer / aluminum layer is more preferably 20 to 27% in order to effectively reduce both the upper and the side hillocks.

Hereinafter, a thin film transistor substrate and a method of manufacturing the same according to the present invention will be described.

FIG. 11 is a plan view of a thin film transistor substrate according to the first embodiment of the present invention, and FIG. 12 is a cross-sectional view taken along the line II-XII of the thin film transistor substrate shown in FIG. 13 to 16 are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate according to the first embodiment of the present invention.

Gate wirings 22, 24, and 26 are formed on the insulating substrate 10. In this case, the gate wirings 22, 24, and 26 are formed of double layers of aluminum layers 221, 241, and 261 and upper molybdenum layers 222, 242, and 262, respectively, and the thicknesses of the upper molybdenum layers 222, 242, and 262 are different. Is 10% to 40% of the thickness of the aluminum layers 221, 241, and 261.

The gate lines 22 and 26 include a gate line 22 extending in the horizontal direction and a gate electrode 26 of the thin film transistor connected to the gate line 22. Here, one end portion 24 of the gate line 22 is extended in width for connection with an external circuit.

On the insulating substrate 10, a gate insulating film 30 made of silicon nitride (SiNx) covers the gate wirings 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24, and n + having a high concentration of silicide or n-type impurity is formed on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as hydrogenated amorphous silicon are formed, respectively.

Data lines 65, 66, and 68 are formed on the ohmic contacts 55 and 56 and the gate insulating layer 30. The data wirings 65, 66, and 68 are also made of a double layer of aluminum layers 651, 661, and 681 and upper molybdenum layers 652, 662, and 682, and the upper molybdenum layers 652, 662, and 682 are aluminum layers. (651, 661, 681) 10 to 40% of the thickness.

 Although not shown, the data line 62 is a double layer like the data lines 65, 66, and 68. As shown in FIG.

The data lines 62, 65, and 66 are formed in the vertical direction and intersect the gate line 22 to define the pixel, the branch of the data line 62, the data line 62, and the upper portion of the ohmic contact layer 55. A drain electrode 66 which is separated from the extending source electrode 65 and the source electrode 65 and is formed on the ohmic contact layer 56 opposite to the source electrode 65 with respect to the gate electrode 26. It includes. At this time, one end portion 68 of the data line 62 is extended in width for connection with an external circuit.

A-Si: C: O film or a deposited on the data lines 62, 65, 66, 68 and on the semiconductor layer 40 which is not covered by silicon nitride (SiNx) or plasma enhanced chemical vapor deposition (PECVD) A protective film 70 made of a -Si: O: F film (low dielectric constant CVD film), an acrylic organic insulating film, and the like is formed. The a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method have a dielectric constant of 4 or less (the dielectric constant has a value between 2 and 4). The dielectric constant is very low. Therefore, even a thin thickness does not cause a parasitic capacity problem. Excellent adhesion to another film and step coverage. Moreover, since it is an inorganic CVD film, heat resistance is excellent compared with an organic insulating film. In addition, the a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method have a 4 to 10 times faster process time than the silicon nitride film in terms of deposition rate and etching rate. It is also very advantageous in terms of.

In the passivation layer 70, contact holes 76 and 78 are formed to expose the drain electrode 66 and the end portion 68 of the data line, respectively, and the contact portion exposing the end portion 24 of the gate line together with the gate insulating layer 30. The hole 74 is formed.

On the passivation layer 70, a pixel electrode 82 electrically connected to the drain electrode 66 and positioned in the pixel region is formed through the contact hole 76. Further, on the passivation layer 70, contact auxiliary members 86 and 88 are formed to be connected to the end portion 24 of the gate line and the end portion 68 of the data line, respectively, through the contact holes 74 and 78. Here, the pixel electrode 82 and the contact auxiliary members 86 and 88 are made of a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO). That is, the drain electrode 66 is in contact with the pixel electrode 82 through the molybdenum layer 664.

11 and 12, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor, and when the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate lines 22, 24, and 26. It is also possible to add a storage capacitor wiring.

In addition, the pixel electrode 82 may also be formed to overlap the data line 62 to maximize the aperture ratio. Even if the pixel electrode 82 is formed to overlap the data line 62 in order to maximize the aperture ratio, if the low dielectric constant CVD film or the like of the protective film 70 is formed, the parasitic capacitance formed therebetween will be small. I can keep it.

Looking at the manufacturing method of the thin film transistor substrate according to the first embodiment, first, as shown in Figure 13, the aluminum layer (221, 241, 261) and the upper molybdenum layer (222, 242, 262) on the insulating substrate 10 A gate metal layer formed of a double layer of the layer) and patterned by a photolithography process using a mask to form the gate lines 22, 24, and 26 including the gate lines 22 and the gate electrodes 26 and extending in the horizontal direction. Form.

Next, as shown in FIG. 14, the three-layer film of the gate insulating film 30 made of silicon nitride, the semiconductor layer 40 made of amorphous silicon, and the doped amorphous silicon layer 50 is successively laminated, and the semiconductor layer 40 ) And the doped amorphous silicon layer 50 are photo-etched to form an island-like semiconductor layer 40 and an ohmic contact layer 50 on the gate insulating layer 30 on the gate electrode 24.

Next, as shown in FIG. 15, a data metal layer including a double layer of aluminum layers 621, 651, and 661 and upper molybdenum layers 622, 652, and 662 is deposited, and patterned by a photolithography process using a mask to form a gate. The data line 62 crossing the line 22 and the source electrode 65 connected to the data line 62 and extending to the upper portion of the gate electrode 26 are separated from the source electrode 65 and the gate electrode ( A data line including a drain electrode 66 facing the source electrode 65 is formed around 26.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIG. 16, the silicon nitride film, the a-Si: C: O film, or the a-Si: O: F film is grown by chemical vapor deposition (CVD) or an organic insulating film is applied to the protective film 70. ).

Subsequently, the passivation layer 70 is patterned together with the gate insulating layer 30 by a photolithography process, thereby contact holes 74 and 76 exposing the end portion 24 of the gate line, the drain electrode 66 and the end portion 68 of the data line. , 78).

Next, as shown in FIGS. 11 and 12, the ITO or IZO film is deposited, photo-etched, and the pixel electrode 82 and the contact holes 74 and 78 connected to the drain electrode 66 through the contact hole 76. The contact auxiliary members 86 and 88 which are connected to the end portion 24 of the gate line and the end portion 68 of the data line are respectively formed therethrough. It is preferable to use nitrogen as the gas used in the pre-heating process before laminating ITO or IZO.

The first embodiment described above uses five masks in the manufacture of a thin film transistor substrate, and the second embodiment described below uses four masks.

17 is a plan view of a thin film transistor substrate according to a second embodiment of the present invention, FIG. 18 is a cross-sectional view taken along the line VII-VII of FIG. 17, and FIG. 19 is a sectional view taken along the line VII-VII of FIG. to be. 20A to 27B are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate according to a second embodiment of the present invention.

On the insulating substrate 10, as in the first embodiment, gate wirings 22, 24, and 26 formed of two layers of aluminum layers 221, 241, and 261 and upper molybdenum layers 222, 242, and 262 are provided. Formed. The upper molybdenum layers 222, 242, 262 have a thickness of 10 to 40% of the thickness of the aluminum layers 221, 241, 261.

The storage electrode line 28 is formed on the substrate material 10 in parallel with the gate line 22. The storage electrode line 28 also has a quad layer like the gate wirings 22, 24, and 26. The storage electrode line 28 overlaps with the conductor 64 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor which improves charge storage capability of the pixel. The pixel electrode 82 and the gate line (to be described later) It may not be formed if the holding capacity resulting from the overlap of 22) is sufficient. The same voltage as that of the common electrode of the upper substrate is usually applied to the storage electrode line 28.

A gate insulating film 30 made of silicon nitride (SiNx) is formed on the gate wirings 22, 24, 26 and the storage electrode line 28 to cover the gate wirings 22, 24, 26 and the storage electrode line 28. .

On the gate insulating layer 30, semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed, and on the semiconductor patterns 42 and 48, n-type impurities such as phosphorus (P) have a high concentration. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the resistive contact layer patterns 55, 56, and 58, a data line 62 comprising a double layer of aluminum layers 621, 641, 651, 661, and 681 and upper molybdenum layers 622, 642, 652, 662, and 682. 64, 65, 66, 68) are formed. The upper molybdenum layers 622, 642, 652, 662, 682 are 10 to 40% of the thickness of the aluminum layers 621, 641, 651, 661, 681. The data line is formed in the vertical direction and is a branch of the data line 62 and the data line 62 which are connected to one end of the data line 62 and have an end portion 68 of the data line to which an image signal from the outside is applied. And a data line portion 62, 68, 65 made of the source electrode 65 of the thin film transistor, and are separated from the data line portions 62, 68, 65, and the channel portion C of the gate electrode 26 or the thin film transistor. ) Also includes the drain electrode 66 of the thin film transistor positioned on the opposite side of the source electrode 65 and the conductor 64 for the storage capacitor located on the storage electrode line 28. When the storage electrode line 28 is not formed, the storage capacitor conductor 64 is also not formed.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and Slightly different from the rest of the contact layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

On the data lines 62, 64, 65, 66 and 68, an a-Si: C: O film or a-Si: O: F film (low dielectric constant CVD) deposited by silicon nitride or plasma enhanced chemical vapor deposition (PECVD) method Film) or an organic insulating film is formed. The protective film 70 has contact holes 76, 78, and 72 that expose the drain electrode 66, the end portion 68 of the data line, and the conductor 64 for the storage capacitor, and together with the gate insulating film 30. It has a contact hole 74 that exposes the end portion 24 of the gate line.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as ITO or indium tin oxide (IZO), and is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. The pixel electrode 82 is also connected to the storage capacitor conductor 64 through the contact hole 72 to transmit an image signal to the conductor pattern 64. On the other hand, contact auxiliary members 86 and 88 are formed on the end portion 24 of the gate line 24 and the end portion 68 of the data line, respectively, through the contact holes 74 and 78. These contact auxiliary members 86 and 88 complement the adhesion between the ends 24 and 68 and the external circuit device, and serve to protect the ends 24 and 68 of the gate lines and the data lines, respectively, and are also transparent. It is formed of a conductive film.

Looking at the manufacturing method of the thin film transistor substrate according to the second embodiment, the aluminum layer (221, 241, 261, 281) and the upper molybdenum layer 222, 242, 262 as shown in Figure 20a and 20b 282 is etched to form a gate line including the gate line 22 and the gate electrode 26 and the storage electrode line 28. At this time, one end portion 24 of the gate line 22 connected to the external circuit has a wider width.

Next, as illustrated in FIGS. 21A and 21B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kPa and 500 kPa to 2,000 using chemical vapor deposition. 연속, 300 600 to 600 연속 continuous deposition, followed by forming a conductor layer 60 consisting of a double layer of an aluminum layer 601 and an upper molybdenum layer 602 to form a data line, and then thereon a photoresist film thereon. (110) is applied in a thickness of 1 µm to 2 µm.

Thereafter, the photosensitive film 110 is irradiated with light through a mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 21A and 21B. At this time, the channel portion C of the photosensitive film patterns 112 and 114, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion E, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed, and all of the photosensitive film of the other portion D is removed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion E should be different depending on the process conditions in the etching process described later. However, it is preferable that the thickness of the first portion 114 is 1/2 or less of the thickness of the second portion 112, for example, 4,000 kPa or less.

As such, there may be various methods of varying the thickness of the photoresist film according to the position, and in order to control the light transmittance in the C region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure, and in the case of using a translucent film, the transmittance is different in order to control the transmittance when fabricating a mask. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all polymer molecules are decomposed, so it should not be so.

This thin film 114 is developed by using a photosensitive film made of a reflowable material and exposed with a conventional mask that is divided into a part that can completely transmit light and a part that cannot completely transmit light. It may be formed by reflowing a portion of the photosensitive film to a portion where the photosensitive film does not remain.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the layers under the data line remain in the data line E, and only the semiconductor layer remains in the channel part C, and the other three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 22A and 22B, the conductor layer 60 exposed to the other portion D is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, and thus the photoresist patterns 112 and 114 may be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

This leaves only the conductor layer of the channel portion C and the data wiring portion E, that is, the source / drain conductor pattern 67 and the storage capacitor conductor 64, as shown in Figs. 23A and 23B. The conductor layer 60 of the other portion D is all removed to reveal the underlying intermediate layer 50. The remaining conductor patterns 67 and 64 are the same as those of the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. . In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 24A and 24B, the exposed intermediate layer 50 of the other portion D and the semiconductor layer 40 thereunder are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions in which the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 24A and 24B, and the intermediate layer 50 of the other portion D. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data line portion E is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductors 64, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as shown in FIGS. 25A and 25B, the source / drain conductor pattern 67 of the channel portion C and the source / drain interlayer pattern 57 under the etching are removed by etching. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57, and the source / drain conductor pattern 67 may be wet-etched, and the intermediate layer pattern ( 57 may be performed by dry etching. In the former case, it is preferable to perform etching under the condition that the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in C). In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include a mixture gas of CF ₄ and HCl or a mixture gas of CF ₄ and O ₂ , and CF ₄ and O ₂ . The semiconductor pattern 42 may be left at a uniform thickness. At this time, as shown in FIG. 24B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the photosensitive film second portion 112 remaining in the data wiring portion E is removed. However, the removal of the second portion 112 may be performed after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

Next, as shown in FIGS. 26A and 26B, a silicon nitride, an a-Si: C: O film, or an a-Si: O: F film is grown by chemical vapor deposition (CVD) or an organic insulating film is applied to the protective film. Form 70.

27A and 27B, the protective film 70 is photo-etched together with the gate insulating film 30 to drain the electrode 66, the end portion 24 of the gate line, and the end portion 68 of the data line. And contact holes 76, 74, 78, 72 exposing the conductor 64 for the holding capacitor, respectively.

Finally, as illustrated in FIGS. 18 and 19, a pixel connected to the drain electrode 66 and the storage capacitor conductor 64 by depositing and photo-etching an ITO layer or an IZO layer having a thickness of 400 kHz to 500 kHz. A data contact assistant member 88 connected to the electrode 82, the end portion 24 of the gate line and the gate contact assistant member 86, and the end portion 68 of the data line are formed.

On the other hand, as a gas used in the pre-heating process before laminating ITO or IZO, it is preferable to use nitrogen, which is the metal film 24 exposed through the contact holes 72, 74, 76, and 78. This is to prevent the metal oxide film from being formed on the upper portions of 64, 66 and 68.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48 may be formed using a single mask, and the manufacturing process may be simplified by separating the source electrode 65 and the drain electrode 66 in this process.

The above embodiments can be variously modified. The upper molybdenum layer may further include any one of tungsten (W), zirconium (Zr), tantalum (Ta), titanium (Ti), and niobium. In addition, a lower molybdenum layer may be further formed below the aluminum layer to form a triple layer wiring.

The thin film transistor substrate according to the present invention may be used in a display device such as a liquid crystal display device or an organic light emitting diode.

The organic electroluminescent device is a self-luminous device using an organic material that emits light upon receiving an electrical signal. In the organic electroluminescent device, a cathode layer (pixel electrode), a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and an anode layer (counter electrode) are stacked. The drain electrode of the TFT substrate according to the present invention may be electrically connected to the cathode layer to apply a data signal.

As described above, according to the present invention, there is provided a thin film transistor substrate and a manufacturing method having aluminum wiring with reduced hillock generation.

Claims (9)

An aluminum layer; And a top molybdenum layer disposed on the aluminum layer and having a thickness of 10% to 40% of the thickness of the aluminum layer. The method of claim 1, And the aluminum layer and the upper molybdenum layer are in direct contact with each other. The method of claim 1, The thickness of the upper molybdenum layer is a thin film transistor substrate, characterized in that 20% to 27% of the thickness of the aluminum layer. The method of claim 1, The upper molybdenum layer further comprises at least one element selected from the group consisting of tungsten (W), zirconium (Zr), tantalum (Ta), titanium (Ti), niobium (niobium), nitrogen (nitrogen). Thin film transistor substrate. The method of claim 1, The thin film transistor substrate further comprising a lower molybdenum layer formed under the aluminum layer. In the thin film transistor substrate comprising a gate wiring and a data wiring, One of the gate wiring and the data wiring includes a thin film transistor substrate including an aluminum layer sequentially formed and an upper molybdenum layer having a thickness of 10% to 40% of the thickness of the aluminum layer. Depositing an aluminum layer on the insulating substrate; Depositing an upper molybdenum layer having a thickness of 10 & 40% of the thickness of the aluminum layer on the aluminum layer; And patterning the aluminum layer and the molybdenum layer to form a wiring. The method of claim 7, wherein And sequentially forming an insulating film, a semiconductor layer, and an ohmic contact layer on the wiring by a plasma-enhanced chemical vapor deposition method. A first substrate including a gate wiring and a data wiring, wherein one of the gate wiring and the data wiring comprises an aluminum layer sequentially formed and an upper molybdenum layer having a thickness of 10% to 40% of the thickness of the aluminum layer; ; A second substrate facing the first substrate; And a liquid crystal layer disposed between the first substrate and the second substrate.

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