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KR100898580B1 - Device Separating Method of Semiconductor Device - Google Patents

Device Separating Method of Semiconductor Device Download PDF

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KR100898580B1
KR100898580B1 KR1020020077594A KR20020077594A KR100898580B1 KR 100898580 B1 KR100898580 B1 KR 100898580B1 KR 1020020077594 A KR1020020077594 A KR 1020020077594A KR 20020077594 A KR20020077594 A KR 20020077594A KR 100898580 B1 KR100898580 B1 KR 100898580B1
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film
trench
hdp oxide
sog film
sog
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KR20040049739A (en
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김한민
김진웅
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating

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Abstract

본 발명은 STI 기술에 의한 고집적 소자의 소자분리막 형성시 보이드 발생없이 트렌치를 용이하게 매립하여 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 소자분리막 형성방법을 제공하기 위한 것으로, 본 발명은 반도체기판을 소정 깊이만큼 식각하여 트렌치를 형성하는 단계; 상기 트렌치의 바닥에서 형성되는 두께가 상기 트렌치의 측벽에서 형성되는 두께보다 더 두껍게 하여 상기 트렌치 저부를 소정 부분 채우도록 상기 트렌치 및 마스크 패턴의 표면 상에 제1HDP산화막을 형성하는 단계; 상기 제1HDP산화막이 형성된 트렌치에 매립되도록 상기 제1HDP산화막 상부에 SOG막을 형성하는 단계; 상기 SOG막과 제1HDP산화막을 상기 마스크 패턴의 표면이 노출되도록 전면식각하여 상기 SOG막이 상기 제1HDP산화막이 형성된 트렌치 내부를 소정 부분만 채우도록 하는 단계; 상기 제1HDP산화막과 SOG막이 형성된 상기 트렌치 내부의 나머지 부분을 채우도록 상기 반도체기판의 전면 상에 제2HDP산화막을 형성하는 단계; 및 상기 마스크 패턴의 표면이 노출되도록 상기 제2HDP산화막을 전면식각하여 상기 SOG막이 상기 제1HDP산화막과 제2HDP산화막에 의해 둘러싸이는 소자분리막을 형성하는 단계를 포함한다. The present invention is to provide a method for forming a device isolation film of a semiconductor device that can improve the reliability of the device by easily filling the trench without generating voids when forming a device isolation film of the highly integrated device by the STI technology, the present invention provides a semiconductor substrate Etching to form a trench to form a trench; Forming a first HDP oxide film on a surface of the trench and a mask pattern such that a thickness formed at a bottom of the trench is thicker than a thickness formed at a sidewall of the trench to fill a portion of the trench bottom; Forming an SOG film on the first HDP oxide film so as to be buried in the trench in which the first HDP oxide film is formed; Etching the SOG film and the first HDP oxide film to expose the surface of the mask pattern so that the SOG film fills a predetermined portion of the trench in which the first HDP oxide film is formed; Forming a second HDP oxide film on an entire surface of the semiconductor substrate to fill the remaining portion of the trench in which the first HDP oxide film and the SOG film are formed; And etching the entire surface of the second HDP oxide layer so that the surface of the mask pattern is exposed to form an isolation layer in which the SOG layer is surrounded by the first HDP oxide layer and the second HDP oxide layer.

HDP-CVD, SOG막, STI, 보이드, 갭매립, 소자분리막HDP-CVD, SOG film, STI, void, gap filling, device isolation film

Description

반도체 소자의 소자분리막 형성방법{METHOD OF FORMING ISOLATION LAYER FOR SEMICONDUCTOR DEVICE} METHODS OF FORMING ISOLATION LAYER FOR SEMICONDUCTOR DEVICE             

도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device in accordance with an embodiment of the present invention.

※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing

10 : 반도체 기판 11A : 패드 산화막10: semiconductor substrate 11A: pad oxide film

11B : 패드 질화막 11 : 마스크 패턴11B: Pad Nitride Film 11: Mask Pattern

12A, 12B : 제 1 및 제 2 HDP 산화막12A, 12B: First and Second HDP Oxides

13 : SOG막 100 : 소자분리막
13: SOG film 100: device isolation film

본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 특히 STI(Sallow Trench Isolation) 기술을 적용한 반도체 소자의 소자분리막 형성방법에 관한 것이다. The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device using STI (Sallow Trench Isolation) technology.                         

일반적으로, 소자분리막은 질화막 패턴을 마스크로 하여 반도체 기판을 열산화시키는 로코스(Local Oxidation of Silicon; LOCOS) 공정을 주로 이용하여 형성하였으나, LOCOS 공정에 의한 소자분리 영역은 비교적 면적이 크고 경계면에 발생되는 버즈빅(bird's beak) 등의 문제로 인하여 고집적 소자에 적용하는데 한계가 있었다. 따라서, 최근에는 소자의 고집적화에 대응하기 위하여, 기판에 얕은 깊이의 트렌치를 형성하고, 이 트렌치에 산화막을 매립시키는 STI(Sallow Trench Isolation) 기술로 소자분리막을 형성하고 있다. 여기서, 산화막은 통상적으로 고밀도플라즈마(High Density Plasma;HDP)-화학기상증착(Chemical Vapor Deposition; CVD) 공정에 의해 형성한다. In general, the device isolation layer is mainly formed using a Local Oxidation of Silicon (LOCOS) process that thermally oxidizes a semiconductor substrate using a nitride pattern as a mask. However, the device isolation region is relatively large in area and is formed on the interface by the LOCOS process. Due to problems such as bird's beak generated, there was a limit to the application to the highly integrated device. Therefore, in recent years, in order to cope with high integration of devices, a device isolation film is formed by a shallow trench isolation (STI) technique in which a trench having a shallow depth is formed in a substrate and an oxide film is buried in the trench. Here, the oxide film is typically formed by a high density plasma (HDP) -chemical vapor deposition (CVD) process.

한편, HDP-CVD 공정은 트렌치 저부에서는 증착속도가 늦게 이루어지는 반면 기판 상부에서는 증착과 스퍼터링이 동시에 이루어져서 예컨대 삼각형상의 패턴을 형성하며, 이러한 HDP-CVD 공정을 일정 두께까지 수행하게 되면 삼각형상의 패턴은 거의 변화가 없고 트렌치 저부의 막이 점점 더 증가하여 트렌치를 매립하게 된다. 그러나, 기판 상부에서 스퍼터링된 원자나 분자들이 트렌치 상부의 에지측면으로 재증착(redeposition)되어 증착막의 프로파일이 보잉(bowing)을 가지게 되어 증착막 내부에 보이드(void)를 유발함으로써 소자의 신뢰성에 악영향을 미치게 된다. 또한, 이러한 현상은 어스펙트비(aspect ratio)가 큰 경우 더 심하게 발생되어 갭매립 특성을 저하시키기 때문에, 예컨대 100㎚ 이하의 고집적 소자에서 HDP-CVD 공정에 의한 산화막으로 소자분리막을 형성하는 데에는 많은 어려움이 있다.
On the other hand, in the HDP-CVD process, the deposition rate is slow at the bottom of the trench, but deposition and sputtering are simultaneously performed on the substrate to form a triangular pattern, and when the HDP-CVD process is performed to a certain thickness, the triangular pattern is almost There is no change and the film at the bottom of the trench increases more and more to fill the trench. However, atoms or molecules sputtered on the substrate are redeposited to the edge side of the trench, so that the deposition profile has bowing, causing voids in the deposition film, thereby adversely affecting the reliability of the device. Go crazy. In addition, since this phenomenon occurs more severely when the aspect ratio is large and degrades the gap filling characteristics, it is often difficult to form a device isolation film using an oxide film by an HDP-CVD process in a highly integrated device of 100 nm or less. There is difficulty.

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, STI 기술에 의한 고집적 소자의 소자분리막 형성시 보이드 발생없이 트렌치를 용이하게 매립하여 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 소자분리막 형성방법을 제공하는데 그 목적이 있다.
The present invention has been proposed to solve the above problems of the prior art, a semiconductor device device that can easily improve the reliability of the device by filling the trench easily without voids when forming the device isolation film of the highly integrated device by the STI technology The purpose is to provide a method for forming a separator.

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 반도체 기판 상에 상기 반도체기판의 일부를 노출시키는 마스크 패턴을 준비하는 단계; 상기 노출된 반도체기판을 소정 깊이만큼 식각하여 트렌치를 형성하는 단계; 상기 트렌치의 바닥에서 형성되는 두께가 상기 트렌치의 측벽에서 형성되는 두께보다 더 두껍게 하여 상기 트렌치 저부를 소정 부분 채우도록 상기 트렌치 및 마스크 패턴의 표면 상에 제1HDP산화막을 형성하는 단계; 상기 제1HDP산화막이 형성된 트렌치에 매립되도록 상기 제1HDP산화막 상부에 SOG막을 형성하는 단계; 상기 SOG막과 제1HDP산화막을 상기 마스크 패턴의 표면이 노출되도록 전면식각하여 상기 SOG막이 상기 제1HDP산화막이 형성된 트렌치 내부를 소정 부분만 채우도록 하는 단계; 상기 제1HDP산화막과 SOG막이 형성된 상기 트렌치 내부의 나머지 부분을 채우도록 상기 반도체기판의 전면 상에 제2HDP산화막을 형성하는 단계; 및 상기 마스크 패턴의 표면이 노출되도록 상기 제2HDP산화막을 전면식각하여 상기 SOG막이 상기 제1HDP산화막과 제2HDP산화막에 의해 둘러싸이는 소자분리막을 형성하는 단계를 포함하는 반도체 소자의 소자분리막 형성방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, an object of the present invention comprises the steps of preparing a mask pattern for exposing a portion of the semiconductor substrate on a semiconductor substrate; Etching the exposed semiconductor substrate by a predetermined depth to form a trench; Forming a first HDP oxide film on a surface of the trench and a mask pattern such that a thickness formed at a bottom of the trench is thicker than a thickness formed at a sidewall of the trench to fill a portion of the trench bottom; Forming an SOG film on the first HDP oxide film so as to be buried in the trench in which the first HDP oxide film is formed; Etching the SOG film and the first HDP oxide film to expose the surface of the mask pattern so that the SOG film fills a predetermined portion of the trench in which the first HDP oxide film is formed; Forming a second HDP oxide film on an entire surface of the semiconductor substrate to fill the remaining portion of the trench in which the first HDP oxide film and the SOG film are formed; And etching the entire surface of the second HDP oxide layer to expose the surface of the mask pattern, thereby forming an isolation layer in which the SOG layer is surrounded by the first HDP oxide layer and the second HDP oxide layer. Can be achieved.

삭제delete

또한, SOG막을 형성하는 단계는 SOG막을 도포 및 베이킹하는 단계과 SOG막을 경화하는 단계로 이루어진다. 또한, SOG막은 HSQ 계열의 무기 SOG막이나 폴리실록산 계열의 유기 SOG막으로 형성할 수 있는데, 무기 SOG막의 경우에는 경화를 200 내지 1000℃의 온도에서 수행하고, 유기 SOG막의 경우에는 200 내지 600℃의 온도에서 수행한다.In addition, forming the SOG film includes applying and baking the SOG film and curing the SOG film. In addition, the SOG film may be formed of an inorganic SOG film of an HSQ series or an organic SOG film of a polysiloxane series. In the case of an inorganic SOG film, curing is performed at a temperature of 200 to 1000 ° C., and an organic SOG film of 200 to 600 ° C. Run at temperature.

또한, 트렌치는 2500Å의 깊이로 형성하고, 제 1 산화막은 트렌치 저부를 500Å 정도 채우도록 형성하며, SOG막의 전면식각은 에치백공정으로 기판 표면으로부터 500Å 하부에 SOG막이 존재하도록 수행한다.In addition, the trench is formed to a depth of 2500 kV, the first oxide film is formed to fill the trench bottom about 500 kV, and the entire etching of the SOG film is performed by etching back so that the SOG film exists below 500 kV from the surface of the substrate.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.

도 1a를 참조하면, 반도체 기판(10) 상에 패드 산화막(11A)과 패드 질화막(11B)을 순차적으로 증착하고 패터닝하여 기판(10)의 일부를 노출시키는 마스크 패턴(11)을 형성한다. 그 다음, 마스크 패턴(11)을 식각 마스크로하여 노출된 기판(10)을 소정 깊이, 바람직하게 약 2500Å 깊이로 식각하여 트렌치를 형성한다. 그 후, 트렌치 저부를 소정 부분, 바람직하게 약 500Å 정도 채우도록 트렌치 및 마스크 패턴(11)의 표면 상에 HDP-CVD 방식으로 제 1 HDP 산화막(12A)을 형성한 다. 바람직하게, HDP-CVD 공정은 O2 및 SiH4 등의 반응성 개스와 Ar 및/또는 He 등의 비활성 개스를 이용하여 30mTorr 이하의 압력과 1500 내지 6000W의 플라즈마발생 전력(plasma generationp power) 및 500 내지 4000W의 플라즈마 내의 이온바이어스 전력(ion-bias power) 하에서 수행한다. 여기서, 반응성 개스와 비활성 개스의 총개스 유량은 100 내지 500sccm으로 조절하고, O2/SiH4의 비율은 1.2 내지 4.0 정도로 한다. 그 다음, 제 1 HDP 산화막(12A)이 형성된 트렌치에 매립되도록 제 1 HDP 산화막(12A) 상부에 갭매립 특성이 우수한 SOG(Spin-On-Glass)막(13)을 형성한다. 여기서, SOG막(13)의 형성은 SOG막을 도포 및 베이킹(baking)하는 공정과 SOG막을 경화(curing)하는 공정으로 이루어진다. 또한, SOG막(13)은 HSQ(Hydrogen Silsequioxane) 계열의 무기 SOG막이나 폴리실록산(polysiloxane) 계열의 유기 SOG막을 이용하여 형성하는데, 무기 SOG막의 경우에는 경화를 200 내지 1000℃의 온도에서 수행하고, 유기 SOG막의 경우에는 경화를 200 내지 600℃의 온도에서 수행한다.Referring to FIG. 1A, a mask pattern 11 exposing a portion of the substrate 10 is formed by sequentially depositing and patterning a pad oxide film 11A and a pad nitride film 11B on a semiconductor substrate 10. Next, the exposed substrate 10 is etched to a predetermined depth, preferably about 2500 kV, using the mask pattern 11 as an etching mask to form a trench. Thereafter, a first HDP oxide film 12A is formed on the surface of the trench and mask pattern 11 by HDP-CVD to fill the trench bottom with a predetermined portion, preferably about 500 GPa. Preferably, the HDP-CVD process uses a reactive gas such as O 2 and SiH 4 and an inert gas such as Ar and / or He, and has a pressure of 30 mTorr or less and a plasma generationp power of 1500 to 6000 W and 500 to It is performed under ion-bias power in a plasma of 4000 W. Here, the total gas flow rate of the reactive gas and the inert gas is adjusted to 100 to 500 sccm, and the ratio of O 2 / SiH 4 is about 1.2 to 4.0. Next, an SOG (Spin-On-Glass) film 13 having excellent gap filling characteristics is formed on the first HDP oxide film 12A so as to fill the trench in which the first HDP oxide film 12A is formed. Here, the formation of the SOG film 13 includes a step of applying and baking the SOG film and a step of curing the SOG film. In addition, the SOG film 13 is formed by using an inorganic SOG film of a HSQ (Hydrogen Silsequioxane) series or an organic SOG film of a polysiloxane series. In the case of the inorganic SOG film, curing is performed at a temperature of 200 to 1000 ° C. In the case of an organic SOG film, curing is performed at a temperature of 200 to 600 ° C.

도 1b를 참조하면, SOG막(13) 및 제 1 HDP 산화막(12A)을 마스크 패턴(11)의 표면이 노출되도록 에치백(etch-back) 공정으로 전면식각하여 포켓(pocket) 형태로 SOG막(13)이 제 1 HDP 산화막(12A)이 형성된 트렌치 내부를 소정 부분 채우도록 한다. 바람직하게는, 기판 표면으로부터 약 500Å 하부에 SOG막(13)이 존재하도록 한다. 또한, 에치백 공정시 패드 질화막(11B)에 비해 제 1 HDP 산화막(12A)과 SOG막(13)이 우수한 식각선택비를 갖도록 하고, 제 1 HDP 산화막(12A)과 SOG막(13)에 대해서는 약 1 : 1 정도의 식각선택비를 갖도록 한다. 또한, 트렌치 상부의 제 1 HDP 산화막(12A) 측벽에 SOG막(13)이 잔존하는 것을 방지하기 위하여, 에치백 공정 후 세정공정을 수행할 수도 있다. 이때, 세정공정은 SOG막(13)과 제 1 HDP 산화막(12A)과의 식각비가 약 100 : 1 정도로 큰 식각용액을 이용하여 습식식각으로 수행한다.Referring to FIG. 1B, the SOG film 13 and the first HDP oxide film 12A are etched back by an etch-back process so that the surface of the mask pattern 11 is exposed. (13) fills a predetermined portion of the inside of the trench in which the first HDP oxide film 12A is formed. Preferably, the SOG film 13 is present below about 500 GPa from the substrate surface. In addition, the first HDP oxide film 12A and the SOG film 13 have an excellent etching selectivity compared to the pad nitride film 11B during the etch back process, and the first HDP oxide film 12A and the SOG film 13 Have an etching selectivity of about 1: 1. In addition, in order to prevent the SOG film 13 from remaining on the sidewalls of the first HDP oxide film 12A on the trench, the cleaning process may be performed after the etch back process. In this case, the cleaning process may be performed by wet etching using an etching solution having an etching ratio of about 100: 1 to the SOG film 13 and the first HDP oxide film 12A.

도 1c를 참조하면, 제 1 HDP 산화막(12A)이 형성된 트렌치 내부의 나머지 부분을 채우도록 기판 전면 상에 HDP-CVD 공정으로 제 2 HDP 산화막(12B)을 형성한다. 바람직하게, HDP-CVD 공정은 제 1 HDP 산화막(12A) 형성에서와 마찬가지로 O2 및 SiH4 등의 반응성 개스와 Ar 및/또는 He 등의 비활성 개스를 이용하여 30mTorr 이하의 압력과 1500 내지 6000W의 플라즈마발생 전력(plasma generationp power) 및 500 내지 4000W의 플라즈마 내의 이온바이어스 전력(ion-bias power) 하에서 수행한다. 여기서, 반응성 개스와 비활성 개스의 총개스 유량은 100 내지 500sccm으로 조절하고, O2/SiH4의 비율은 1.2 내지 4.0 정도로 한다. Referring to FIG. 1C, the second HDP oxide layer 12B is formed on the entire surface of the substrate by the HDP-CVD process so as to fill the remaining portion of the trench in which the first HDP oxide layer 12A is formed. Preferably, the HDP-CVD process uses a reactive gas such as O 2 and SiH 4 and an inert gas such as Ar and / or He and a pressure of 30 mTorr or less and 1500 to 6000 W as in the formation of the first HDP oxide film 12A. It is performed under plasma generationp power and ion-bias power in the plasma of 500 to 4000W. Here, the total gas flow rate of the reactive gas and the inert gas is adjusted to 100 to 500 sccm, and the ratio of O 2 / SiH 4 is about 1.2 to 4.0.

도 1d를 참조하면, 화학기계연마(Chemical Mechanical Polishing; CMP) 공정으로 마스크 패턴(11)의 표면이 노출되도록 제 2 HDP 산화막(12B)을 전면식각하여 제 1 HDP 산화막(12A), SOG막(13) 및 제 2 HDP 산화막(12B)으로 이루어진 소자분리막(100)을 형성한다. 그 후, 마스크 패턴(11)을 제거하고 세정공정을 수행한다.Referring to FIG. 1D, the first HDP oxide film 12A and the SOG film may be completely etched by etching the second HDP oxide film 12B so that the surface of the mask pattern 11 is exposed by a chemical mechanical polishing (CMP) process. 13) and the device isolation film 100 formed of the second HDP oxide film 12B. Thereafter, the mask pattern 11 is removed and a cleaning process is performed.

상기 실시예에 의하면, HDP 산화막과 갭매립 특성이 우수한 SOG막을 조합하여 보이드 발생없이 트렌치를 용이하게 매립할 수 있게 된다. 또한, 트렌치 내에 서 SOG막을 둘러싸는 포켓형태로 HDP 산화막을 형성함에 따라 SOG막의 비교적 열악한 절연특성을 보완할 수 있고, 이에 따라 안정적인 소자분리막 특성을 확보할 수 있게 됨으로써 소자의 신뢰성을 향상시킬 수 있다.According to the above embodiment, the trench can be easily buried without generating voids by combining the HDP oxide film and the SOG film having excellent gap filling properties. In addition, by forming the HDP oxide film in the form of a pocket surrounding the SOG film in the trench, it is possible to compensate for the relatively poor insulation characteristics of the SOG film, thereby ensuring stable device isolation film properties, thereby improving device reliability. .

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은 STI 기술에 의한 고집적 소자의 소자분리막 형성시 HDP 산화막과 SOG막을 조합하여 보이드 발생없이 트렌치를 용이하게 매립함으로써 소자의 신뢰성을 향상시킬 수 있다.The present invention described above can improve the reliability of the device by easily filling the trench without voids by combining the HDP oxide film and the SOG film when forming the device isolation film of the highly integrated device by the STI technology.

Claims (11)

반도체 기판 상에 상기 반도체기판의 일부를 노출시키는 마스크 패턴을 준비하는 단계;Preparing a mask pattern exposing a portion of the semiconductor substrate on a semiconductor substrate; 상기 노출된 반도체기판을 소정 깊이만큼 식각하여 트렌치를 형성하는 단계;Etching the exposed semiconductor substrate by a predetermined depth to form a trench; 상기 트렌치의 바닥에서 형성되는 두께가 상기 트렌치의 측벽에서 형성되는 두께보다 더 두껍게 하여 상기 트렌치 저부를 소정 부분 채우도록 상기 트렌치 및 마스크 패턴의 표면 상에 제1HDP산화막을 형성하는 단계;Forming a first HDP oxide film on a surface of the trench and a mask pattern such that a thickness formed at a bottom of the trench is thicker than a thickness formed at a sidewall of the trench to fill a portion of the trench bottom; 상기 제1HDP산화막이 형성된 트렌치에 매립되도록 상기 제1HDP산화막 상부에 SOG막을 형성하는 단계;Forming an SOG film on the first HDP oxide film so as to be buried in the trench in which the first HDP oxide film is formed; 상기 SOG막과 제1HDP산화막을 상기 마스크 패턴의 표면이 노출되도록 전면식각하여 상기 SOG막이 상기 제1HDP산화막이 형성된 트렌치 내부를 소정 부분만 채우도록 하는 단계;Etching the SOG film and the first HDP oxide film to expose the surface of the mask pattern so that the SOG film fills a predetermined portion of the trench in which the first HDP oxide film is formed; 상기 제1HDP산화막과 SOG막이 형성된 상기 트렌치 내부의 나머지 부분을 채우도록 상기 반도체기판의 전면 상에 제2HDP산화막을 형성하는 단계; 및 Forming a second HDP oxide film on an entire surface of the semiconductor substrate to fill the remaining portion of the trench in which the first HDP oxide film and the SOG film are formed; And 상기 마스크 패턴의 표면이 노출되도록 상기 제2HDP산화막을 전면식각하여 상기 SOG막이 상기 제1HDP산화막과 제2HDP산화막에 의해 둘러싸이는 소자분리막을 형성하는 단계Etching the entire surface of the second HDP oxide layer to expose the surface of the mask pattern to form an isolation layer in which the SOG layer is surrounded by the first HDP oxide layer and the second HDP oxide layer 를 포함하는 반도체 소자의 소자분리막 형성방법.Device isolation film forming method of a semiconductor device comprising a. 삭제delete 제 1 항에 있어서, The method of claim 1, 상기 SOG막을 형성하는 단계는 SOG막을 도포 및 베이킹하는 단계과 상기 SOG막을 경화하는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The forming of the SOG film comprises coating and baking the SOG film and curing the SOG film. 제 1 항 또는 제 3 항에 있어서, The method according to claim 1 or 3, 상기 SOG막은 HSQ 계열의 무기 SOG막으로 형성하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.And the SOG film is formed of an inorganic SOG film of HSQ series. 제 1 항 또는 제 3 항에 있어서, The method according to claim 1 or 3, 상기 SOG막은 폴리실록산 계열의 유기 SOG막으로 형성하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.Wherein the SOG film is formed of an organic SOG film of polysiloxane series. 제 4 항에 있어서, The method of claim 4, wherein 상기 SOG막의 경화는 200 내지 1000℃의 온도에서 수행하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.Curing the SOG film is a device isolation film forming method of a semiconductor device, characterized in that performed at a temperature of 200 to 1000 ℃. 제 5 항에 있어서, The method of claim 5, wherein 상기 SOG막의 경화는 200 내지 600℃의 온도에서 수행하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.Curing the SOG film is a device isolation film forming method of a semiconductor device, characterized in that carried out at a temperature of 200 to 600 ℃. 제 1 항에 있어서, The method of claim 1, 상기 트렌치는 2500Å의 깊이로 형성하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.And forming said trench at a depth of 2500 microns. 제 1 항에 있어서, The method of claim 1, 상기 제1HDP산화막은 상기 트렌치 저부를 500Å 채우도록 형성하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.And the first HDP oxide layer is formed to fill the trench bottom portion of 500 mu m. 제 1 항에 있어서, The method of claim 1, 상기 SOG막의 전면식각은 에치백공정으로 수행하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.And etching the entire surface of the SOG film by an etch back process. 제 10 항에 있어서, The method of claim 10, 상기 에치백 공정은 상기 기판 표면으로부터 500Å 하부에 상기 SOG막이 존재하도록 수행하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.Wherein the etch back process is performed such that the SOG film is present at a lower portion of 500 GHz from the surface of the substrate.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9721830B2 (en) 2015-07-16 2017-08-01 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices including isolation layers

Families Citing this family (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7332409B2 (en) 2004-06-11 2008-02-19 Samsung Electronics Co., Ltd. Methods of forming trench isolation layers using high density plasma chemical vapor deposition
KR100816749B1 (en) * 2006-07-12 2008-03-27 삼성전자주식회사 Device isolation films, nonvolatile memory devices including the device isolation films, and device isolation films and methods of forming nonvolatile memory devices
KR100880322B1 (en) * 2006-09-29 2009-01-28 주식회사 하이닉스반도체 Flash memory device and its manufacturing method
KR101050454B1 (en) * 2007-07-02 2011-07-19 주식회사 하이닉스반도체 Device Separation Film of Semiconductor Device and Formation Method Thereof
KR100920048B1 (en) * 2007-12-20 2009-10-07 주식회사 하이닉스반도체 Manufacturing method of semiconductor device
KR100929640B1 (en) * 2008-01-18 2009-12-03 주식회사 하이닉스반도체 Manufacturing method of semiconductor device
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US8771536B2 (en) 2011-08-01 2014-07-08 Applied Materials, Inc. Dry-etch for silicon-and-carbon-containing films
US8927390B2 (en) 2011-09-26 2015-01-06 Applied Materials, Inc. Intrench profile
WO2013070436A1 (en) 2011-11-08 2013-05-16 Applied Materials, Inc. Methods of reducing substrate dislocation during gapfill processing
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9064816B2 (en) 2012-11-30 2015-06-23 Applied Materials, Inc. Dry-etch for selective oxidation removal
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US8801952B1 (en) 2013-03-07 2014-08-12 Applied Materials, Inc. Conformal oxide dry etch
US20140271097A1 (en) 2013-03-15 2014-09-18 Applied Materials, Inc. Processing systems and methods for halide scavenging
US8895449B1 (en) 2013-05-16 2014-11-25 Applied Materials, Inc. Delicate dry clean
US9114438B2 (en) 2013-05-21 2015-08-25 Applied Materials, Inc. Copper residue chamber clean
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US8956980B1 (en) 2013-09-16 2015-02-17 Applied Materials, Inc. Selective etch of silicon nitride
US8951429B1 (en) 2013-10-29 2015-02-10 Applied Materials, Inc. Tungsten oxide processing
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9236265B2 (en) 2013-11-04 2016-01-12 Applied Materials, Inc. Silicon germanium processing
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9117855B2 (en) 2013-12-04 2015-08-25 Applied Materials, Inc. Polarity control for remote plasma
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9263278B2 (en) 2013-12-17 2016-02-16 Applied Materials, Inc. Dopant etch selectivity control
US9190293B2 (en) 2013-12-18 2015-11-17 Applied Materials, Inc. Even tungsten etch for high aspect ratio trenches
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299538B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9136273B1 (en) 2014-03-21 2015-09-15 Applied Materials, Inc. Flash gate air gap
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9847289B2 (en) 2014-05-30 2017-12-19 Applied Materials, Inc. Protective via cap for improved interconnect performance
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9159606B1 (en) 2014-07-31 2015-10-13 Applied Materials, Inc. Metal air gap
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9165786B1 (en) 2014-08-05 2015-10-20 Applied Materials, Inc. Integrated oxide and nitride recess for better channel contact in 3D architectures
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000114362A (en) * 1998-10-02 2000-04-21 Nec Corp Manufacture of semiconductor device
KR20010063731A (en) * 1999-12-24 2001-07-09 박종섭 Method of forming an isolation layer in a semiconductor device
JP2002110780A (en) * 2000-09-20 2002-04-12 United Microelectron Corp Manufacturing method of shallow trench isolation structure
KR20020071169A (en) * 2001-03-05 2002-09-12 삼성전자 주식회사 Method of forming insulation layer in trench isolation type semiconductor device
KR20020072657A (en) * 2001-03-12 2002-09-18 삼성전자 주식회사 Trench isolation type semiconductor device and method of forming trench type isolation layer
US6479369B1 (en) * 1999-11-08 2002-11-12 Nec Corporation Shallow trench isolation (STI) and method of forming the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000114362A (en) * 1998-10-02 2000-04-21 Nec Corp Manufacture of semiconductor device
US6479369B1 (en) * 1999-11-08 2002-11-12 Nec Corporation Shallow trench isolation (STI) and method of forming the same
KR20010063731A (en) * 1999-12-24 2001-07-09 박종섭 Method of forming an isolation layer in a semiconductor device
JP2002110780A (en) * 2000-09-20 2002-04-12 United Microelectron Corp Manufacturing method of shallow trench isolation structure
KR20020071169A (en) * 2001-03-05 2002-09-12 삼성전자 주식회사 Method of forming insulation layer in trench isolation type semiconductor device
KR20020072657A (en) * 2001-03-12 2002-09-18 삼성전자 주식회사 Trench isolation type semiconductor device and method of forming trench type isolation layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9721830B2 (en) 2015-07-16 2017-08-01 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices including isolation layers

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