KR100567747B1 - Device Separating Method of Semiconductor Device - Google Patents
Device Separating Method of Semiconductor Device Download PDFInfo
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- KR100567747B1 KR100567747B1 KR1020030101786A KR20030101786A KR100567747B1 KR 100567747 B1 KR100567747 B1 KR 100567747B1 KR 1020030101786 A KR1020030101786 A KR 1020030101786A KR 20030101786 A KR20030101786 A KR 20030101786A KR 100567747 B1 KR100567747 B1 KR 100567747B1
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 28
- 238000002955 isolation Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229920000642 polymer Polymers 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 보다 자세하게는 다층의 적층막 식각시 중간에 트렌치의 폭을 줄이는 마스크 공정을 추가함으로써 최종적으로 미세한 선폭의 트렌치를 얻을 수 있는 방법에 관한 것이다. The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of finally obtaining a trench having a fine line width by adding a mask process to reduce the width of a trench in the middle of etching a multilayer film.
본 발명의 반도체 소자의 소자분리막 형성방법은 반도체 기판의 상부에 다층의 적층막을 형성하는 단계; 소자분리막이 형성될 영역을 개방하는 포토레지스트 패턴을 형성하여 고밀도 플라즈마를 이용한 식각을 실시하는 단계; 소정 층의 적층막까지 식각을 진행한 후 상기 포토레지스트 패턴을 제거하고 폴리머 마스크 패턴을 형성하는 단계; 및 상기 폴리머 마스크 패턴을 식각마스크로 하여 소정 층 이후의 적층막과 실리콘 기판을 동시에 식각하여 소자분리막을 형성하는 단계로 이루어짐에 기술적 특징이 있다.The device isolation film forming method of the semiconductor device of the present invention comprises the steps of forming a multilayer film on the semiconductor substrate; Forming a photoresist pattern to open a region where the device isolation layer is to be formed, and performing etching using a high density plasma; Removing the photoresist pattern and forming a polymer mask pattern after etching the laminated film of a predetermined layer; And forming a device isolation layer by simultaneously etching the laminated film and the silicon substrate after a predetermined layer using the polymer mask pattern as an etching mask.
따라서, 본 발명의 반도체 소자의 소자분리막 형성방법은 다층의 적층막 식각시 중간에 트렌치의 폭을 줄이는 마스크 공정을 추가함으로써 최종적으로 미세한 선폭의 트렌치를 얻을 수 있는 효과가 있다.Therefore, the device isolation film forming method of the semiconductor device of the present invention has an effect of finally obtaining a fine line width trench by adding a mask process to reduce the width of the trench in the middle of the multilayer film etching.
고밀도 플라즈마, 폴리머 마스크High Density Plasma, Polymer Mask
Description
도 1 내지 도 3은 본 발명에 의한 반도체 소자의 소자분리막 형성방법의 단면도.1 to 3 are cross-sectional views of a device isolation film forming method of a semiconductor device according to the present invention.
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 보다 자세하게는 다층의 적층막 식각시 중간에 트렌치(trench)의 폭을 줄이는 마스크 공정을 추가함으로써 최종적으로 미세한 선폭의 트렌치를 얻을 수 있는 방법에 관한 것이다. The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of finally obtaining a fine line width trench by adding a mask process that reduces the width of a trench in the middle of etching a multilayer film. It is about.
종래에는, 일반적으로 반도체 소자를 분리하는 방법으로 선택적으로 질화막을 이용하는 LOCOS(Local Oxidation of Sillicon, 이하 LOCOS) 소자 분리 방법이 이용되어 왔다. LOCOS 소자 분리 방법은 질화막을 마스크로 해서 실리콘 웨이퍼 자체를 열산화시키기 때문에 공정이 간소해서 산화막의 소자 응력 문제가 적고, 생성 되는 산화막질이 좋다는 이점이 있다. 그러나, LOCOS 소자 분리 방법을 이용하면 소자 분리 영역이 크기 때문에 소자의 미세화에 한계가 있을 뿐만 아니라 버즈비크(bird's beak)가 발생하게 된다.Conventionally, a LOCOS (Local Oxidation of Sillicon, LOCOS) device isolation method using a nitride film selectively has been used as a method for separating semiconductor devices. Since the LOCOS device isolation method thermally oxidizes the silicon wafer itself using a nitride film as a mask, the process is simple and there is an advantage that the device stress problem of the oxide film is small, and the resulting oxide film quality is good. However, when the LOCOS device isolation method is used, the device isolation region is large, thereby limiting the miniaturization of the device and generating bird's beak.
상기와 같은 문제점을 극복하기 위해 LOCOS 소자 분리 방법을 대체하는 기술로서 트렌치 소자 분리(Shallow Trench Isolation, 이하 STI)가 있다. 트렌치 소자 분리에서는 실리콘 웨이퍼에 트렌치를 만들어 절연물을 집어넣기 때문에 소자 분리 영역이 차지하는 면적이 작아서 소자의 미세화에 유리하다. 현재 적용되는 STI 공정은 반도체 기판을 건식식각하여 트렌치를 형성한 후 건식식각으로 인한 손상을 큐어링(curing)한 후, 계면특성 및 활성영역과 소자격리 영역의 모서리 라운딩 특성을 향상시키기 위해 트렌치 내부를 열산화하여 산화막을 형성하는 공정을 진행한다. 이 후 산화막이 형성된 트렌치를 메우도록 반도체 기판 전면에 절연막을 두껍게 증착하고 화학적 기계적 연마(Chemical Mechanical Polishing, 이하 CMP)를 진행하여 반도체 기판을 평탄화한다. 그러나, 상기와 같은 종래의 STI 공정은 고집적화된 소자일수록 소자간 간격이 좁아짐과 동시에 트렌치 기울기(Trench Slope)도 거의 직각을 이룰 수 밖에 없다. 따라서 산화막의 갭필(gap-fill)이 이루어지지 않아 보이드(void)가 발생할 수 있는 문제점이 있다. 또한 상기 트렌치를 갭필하는 산화막으로는 갭필 특성과 평탄화 특성이 양호한 O3-TEOS(O3-TetraEthylOrthoSilicate, 이하 O3-TEOS) 상압화학기상증착(Atmospheric Pressure Chemical Vapor Deposition, 이하 APCVD) 산화막, 고밀도 플라즈마 화학기상증착(High Density Plasma Chemical Vapor Deposition) 산화막이 주로 사용되어 오고 있다. In order to overcome the problems described above, as a technique for replacing the LOCOS device isolation method, there is trench trench isolation (hereinafter, STI). In trench device isolation, a trench is formed in a silicon wafer to insulate the insulator, so the area of the device isolation region is small, which is advantageous for miniaturization of the device. Currently applied STI process is to dry the semiconductor substrate to form the trench, and then to cure the damage caused by the dry etching, and then to improve the interface characteristics and the corner rounding characteristics of the active region and the device isolation region inside the trench Is thermally oxidized to form an oxide film. Thereafter, an insulating film is thickly deposited on the entire surface of the semiconductor substrate so as to fill the trench in which the oxide film is formed, and chemical mechanical polishing (CMP) is performed to planarize the semiconductor substrate. However, in the conventional STI process as described above, the spacing between the devices becomes narrower and the trench slopes are almost right at the same time as the integrated devices become higher. Therefore, there is a problem that voids may occur because a gap-fill of the oxide layer is not performed. In addition, the oxide film gap-filling the trench may be O 3 -TEOS (O 3 -TetraEthylOrthoSilicate, hereinafter O 3 -TEOS) Atmospheric Pressure Chemical Vapor Deposition (APCVD) oxide film having high gap fill characteristics and planarization characteristics, and high density plasma. High Density Plasma Chemical Vapor Deposition An oxide film has been mainly used.
그러나 소자의 고집적화가 진행됨에 따라 STI 형성을 위해 여러 단계의 공정을 거치게되므로서 품질의 저하 및 생산성의 저하를 일으키는 문제점이 발생한다. 또한 여러단계를 거쳐서 식각을 진행하게 되면 식각의 폭이 점점 넓어지는 문제점이 발생한다.However, as the integration of devices proceeds, several steps are required to form STIs, resulting in a problem of deterioration in quality and productivity. In addition, if the etching proceeds through several steps, the width of the etching gradually increases.
따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 다층의 적층막 식각시 중간에 트렌치의 폭을 줄이는 마스크 공정을 추가함으로써 최종적으로 미세한 선폭의 트렌치를 얻을 수 있는 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the problems of the prior art as described above, by providing a method for finally obtaining a fine line width trench by adding a mask process to reduce the width of the trench in the middle of the multilayer film etching. There is an object of the present invention.
본 발명의 상기 목적은 반도체 기판의 상부에 다층의 적층막을 형성하는 단계; 소자분리막이 형성될 영역을 개방하는 포토레지스트 패턴을 형성하여 고밀도 플라즈마를 이용한 식각을 실시하는 단계; 소정 층의 적층막까지 식각을 진행한 후 상기 포토레지스트 패턴을 제거하고 폴리머 마스크 패턴을 형성하는 단계; 및 상기 폴리머 마스크 패턴을 식각마스크로 하여 소정 층 이후의 적층막과 실리콘 기판을 동시에 식각하여 소자분리막을 형성하는 단계로 이루어진 반도체 소자의 소자분리 막 형성방법에 의해 달성된다.The object of the present invention is to form a multi-layer laminated film on top of the semiconductor substrate; Forming a photoresist pattern to open a region where the device isolation layer is to be formed, and performing etching using a high density plasma; Removing the photoresist pattern and forming a polymer mask pattern after etching the laminated film of a predetermined layer; And forming a device isolation film by simultaneously etching the laminated film and the silicon substrate after a predetermined layer using the polymer mask pattern as an etch mask.
본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.
먼저, 도 1은 다층의 적층막을 형성하는 단계를 나타내는 단면도이다. 반도체 기판(1)에 SiO2 패드 산화막(2)을 150Å의 두께로 형성하고 Si3N4 질화막(3)을 1500Å의 두께로 형성한다. 이후 TEOS(Tetra-ethoxysilane) 산화막(4)을 1000Å의 두께로 형성하고 그 상부에 반사방지막(5)을 600Å의 두께로 형성한다. 이후 STI 소자분리막이 형성될 영역을 개방하는 포토레지스트(photoresist) 패턴(6)을 형성한다.First, FIG. 1 is sectional drawing which shows the process of forming a multilayer laminated film. The SiO 2 pad oxide film 2 is formed on the semiconductor substrate 1 to a thickness of 150 kPa, and the Si 3 N 4 nitride film 3 is formed to a thickness of 1500 kPa. Thereafter, a TEOS (Tetra-ethoxysilane)
다음, 도 2는 상기 패턴을 식각마스크로 하여 TEOS 산화막까지 식각하는 단계를 나타내는 단면도이다. 이때 식각은 고밀도 플라즈마를 이용하여 실시하며 식각조건은 다음과 같다. 40 내지 100mTorr의 압력에서 CF4/Ar/NH3 혼합가스를 이용해 1000 내지 2000W의 파워를 이용해 실시한다. 또한 상기 혼합가스를 30 내지 60sccm의 CF4, 30 내지 300sccm의 Ar 그리고 10 내지 40sccm의 NH3의 비율로 흘려주면서 반사방지막과 TEOS 산화막을 식각한다. Next, FIG. 2 is a cross-sectional view illustrating a step of etching the TEOS oxide layer using the pattern as an etching mask. At this time, etching is performed using high density plasma, and etching conditions are as follows. It is carried out using a power of 1000 to 2000W using a CF 4 / Ar / NH 3 mixed gas at a pressure of 40 to 100mTorr. In addition, the anti-reflection film and the TEOS oxide film are etched while flowing the mixed gas at a ratio of CF 4 of 30 to 60 sccm, Ar of 30 to 300 sccm, and NH 3 of 10 to 40 sccm.
다음, 도 3은 소정 폭을 가지는 폴리머(polymer) 마스크 패턴(7)을 형성하는 단계를 보여주는 단면도이다. 상기 단계에서 마스크로 이용하였던 반사방지막 상부의 포토레지스트 패턴을 제거한 후 상기 산화막의 트렌치에 폴리머 물질을 사용하 여 소정 폭의 마스크 패턴을 형성한다. 폴리머에 의해 형성된 마스크의 폭은 상기 포토레지스트 패턴의 폭보다 좁음을 특징으로 한다.Next, FIG. 3 is a cross-sectional view illustrating a step of forming a
다음, 도 4는 상기 폴리머 마스크를 식각마스크로 하여 질화막과 패드산화막 그리고 실리콘 기판을 소정의 두께만큼 추가적으로 식각하는 단계를 나타내는 단면도이다. 상기 산화막까지 식각할 때와 동일한 플라즈마를 이용해 식각을 진행한다. 즉, 동일한 챔버 내에서 동일한 플라즈마의 조건으로 다층의 적층막과 실리콘 기판을 식각함으로써 종래의 실리콘 기판을 포함한 다층의 적층막을 식각하는 경우에 비해 감소된 횟수로 식각을 실시하면서 동시에, 형성되는 트렌치의 폭을 미세화할 수 있는 특징을 가진다.Next, FIG. 4 is a cross-sectional view illustrating a step of additionally etching the nitride film, the pad oxide film, and the silicon substrate using the polymer mask as an etching mask. Etching is performed using the same plasma as when etching to the oxide film. That is, by etching the multilayer film and the silicon substrate in the same chamber under the same plasma conditions, the trenches formed at the same time are etched at a reduced number of times compared to the case of etching the multilayer film including the conventional silicon substrate. It has the feature of making the width smaller.
이후 단계는 도시되지는 않았지만 형성된 소자분리막에 라이너(liner) 산화막을 형성하고 절연막을 갭필(gap-fill)하여 소자분리막을 완성한다.Although not shown in the drawing, a liner oxide film is formed on the formed device isolation film, and the device isolation film is gap-filled to complete the device isolation film.
상세히 설명된 본 발명에 의하여 본 발명의 특징부를 포함하는 변화들 및 변형들이 당해 기술 분야에서 숙련된 보통의 사람들에게 명백히 쉬워질 것임이 자명하다. 본 발명의 그러한 변형들의 범위는 본 발명의 특징부를 포함하는 당해 기술 분야에 숙련된 통상의 지식을 가진 자들의 범위 내에 있으며, 그러한 변형들은 본 발명의 청구항의 범위 내에 있는 것으로 간주된다.It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.
따라서, 본 발명의 반도체 소자의 소자분리막 형성방법은 다층의 적층막 식각시 중간에 트렌치의 폭을 줄이는 마스크 공정을 추가함으로써 최종적으로 미세한 선폭의 트렌치를 얻을 수 있는 효과가 있다.Therefore, the device isolation film forming method of the semiconductor device of the present invention has an effect of finally obtaining a fine line width trench by adding a mask process to reduce the width of the trench in the middle of the multilayer film etching.
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