KR100750913B1 - Method for manufacturing wiring and thin film transistor substrate for liquid crystal display device including the wiring and method for manufacturing same - Google Patents

Abstract

First, an aluminum-based conductive material is stacked and patterned to form a horizontal gate line including a gate line, a gate electrode, and a gate pad on a substrate. Next, a gate insulating film is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. Next, an aluminum-based conductive material is stacked and patterned to form a data line including a data line, a source electrode, a drain electrode, and a data pad crossing the gate line. Subsequently, the protective film is stacked and patterned to form contact holes that expose the drain electrode, the gate pad, and the data pad, respectively. Subsequently, a metal film including chromium or molybdenum or molybdenum alloy is stacked and annealed, and then the metal film is removed to form a buffer layer on the drain electrode gate pad and the data pad exposed through the contact hole. Subsequently, the IZO is stacked and patterned to form pixel electrodes, auxiliary gate pads, and auxiliary data pads respectively connected to the drain electrode, the gate pad, and the data pad through the buffer layer.

Aluminum, IZO, Chrome, Contact Properties

Description

TECHNICAL MANUFACTURING A WIRES, AND THIN FILM TRANSISTOR SUBSTRATE FOR LIQUID CRYSTAL DISPLAY INCLUDING THE WIRES AND MANUFACTURING METHOD THEREOF

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II.

3 is a thin film transistor substrate for a liquid crystal display according to a second embodiment of the present invention;

FIG. 4 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 3 taken along the line IV-IV.

5A, 6A, 7A, 8A, and 9A are layout views of a thin film transistor substrate in an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A, and is a cross-sectional view illustrating the following steps of FIG. 5B;

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ in FIG. 7A and illustrating the next step in FIG. 6B;

FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb ′ in FIG. 8A and is a cross-sectional view showing the next step in FIG. 7B;

FIG. 9B is a cross-sectional view taken along the line IXb-IXb 'of FIG. 9A and illustrates the next step of FIG. 8B;

FIG. 10A is a layout view of a thin film transistor substrate illustrating a next step of FIG. 8A in an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention; FIG.

FIG. 10B is a cross-sectional view taken along the line Xb-Xb 'in FIG. 10A and illustrates the next step of FIG. 8B;

11 is a layout view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention.

12 and 13 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 11 taken along lines XII-XII 'and XIII-XIII',

14A is a layout view of a thin film transistor substrate at a first stage of manufacture in accordance with a third embodiment of the present invention;

14B and 14C are cross-sectional views taken along the lines XIVb-XIVb ′ and XIVc-XIVc ′ in FIG. 14A, respectively.

15A and 15B are cross-sectional views taken along the XIVb-Xb 'line and the XIVc-XIVc' line in FIG. 14A, respectively, and are cross-sectional views in the next steps of FIGS. 14B and 14C;

FIG. 16A is a layout view of a thin film transistor substrate in the next steps of FIGS. 15A and 15B;

16B and 16C are cross-sectional views taken along lines XVIb-XVIb 'and XVIc-XVIc', respectively, of FIG. 16A.

17A, 18A, 19A and 17B, 18B, and 19B are cross-sectional views taken along the lines XVIb-XVIb 'and XVIc-XVIc' in FIG. 16A, respectively, illustrating the following steps in the order of the process. ,

20A is a layout view of a thin film transistor substrate in the next steps of FIGS. 19A and 19B;

20B and 20C are cross-sectional views taken along the lines XXb-XXb 'and XXc-XXc' of FIG. 20A, respectively.

FIG. 21A is a layout view of a thin film transistor substrate at a next step of FIG. 20A,

21B and 21C are cross-sectional views taken along the lines XXIb-XXIb 'and XXIc-XXIc', respectively, in FIG. 21A.

The present invention relates to a manufacturing method of a wiring, a thin film transistor substrate for a liquid crystal display device including the wiring, and a manufacturing method thereof.

In general, the wiring in the semiconductor device is used as a means for transmitting a signal, it is required to minimize the signal delay.

In this case, in order to prevent signal delay, the wiring is generally made of a metal material having a low resistance, particularly an aluminum-based metal material such as aluminum (Al) or aluminum alloy (Al alloy). However, since the aluminum-based wiring has weak physical or chemical properties, corrosion occurs when the terminal is connected to the terminal of the semiconductor device, thereby deteriorating the characteristics of the semiconductor device. In order to improve such contact characteristics, wiring may be interposed with other metals when forming an aluminum series. However, in order to form a multilayer wiring, not only different etching solutions are required but also multiple etching processes are required, which makes the manufacturing process complicated. .

On the other hand, the liquid crystal display device is one of the most widely used flat panel display devices, and consists of two substrates on which electrodes are formed and a liquid crystal layer inserted therebetween. The display device controls the amount of light transmitted by rearranging.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

In such a liquid crystal display device, in order to prevent signal delay, the wiring generally uses a low resistance material such as aluminum (Al) or aluminum alloy (Al alloy) having a low resistance. However, in the case of forming a pixel electrode using ITO (indium tin oxide), which is a transparent conductive material as in a liquid crystal display, or securing the pad part reliability, aluminum-based metal and ITO have poor contact characteristics, and thus molybdenum-based or chrome Intervening with other metals, such as aluminum, or aluminum alloy in the contact portion has to be removed, so the manufacturing process is complicated.

On the other hand, in the manufacturing method of the liquid crystal display device, the substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, it is preferable to reduce the number of masks in order to reduce the production cost.

The technical problem to be achieved by the present invention is to provide a method for manufacturing a wiring made of a low resistance material and having excellent contact characteristics.

Another object of the present invention is to provide a thin film transistor substrate for a liquid crystal display device including a wiring having excellent contact characteristics and a method of manufacturing the same.

In addition, another object of the present invention is to simplify the manufacturing method of the thin film transistor substrate for liquid crystal display devices.

In order to solve this problem, in the manufacturing method of the wiring according to the present invention, an intermetallic compound layer or an intermetallic contact layer is formed on the wiring.

In the manufacturing method of the wiring which concerns on this invention, a 1st metal layer is first laminated | stacked on a board | substrate, and a 2nd metal layer is laminated | stacked. Subsequently, an annealing process is performed to form a compound layer between metals between the first and second metal layers, and then the second metal layer is removed.

In this case, the first metal layer is preferably formed of an aluminum-based conductive material, and the second metal layer is preferably formed of a transition metal.

In addition, it is preferable to perform an annealing process in 200-400 degreeC.

Here, an insulating layer may be formed on the first metal layer, patterned to form a contact hole, and then a second metal layer may be formed to form a compound layer between the metal only on the upper part of the first metal layer exposed through the contact hole.

The method for manufacturing a wiring according to the present invention may further include forming a conductive layer connected to the first metal layer on the insulating layer through the compound layer between the metals exposed through the contact hole.

Herein, the conductive layer may be a transparent conductive material having no battery reaction with the aluminum-based conductive layer.

Such a method for manufacturing a wiring according to the present invention can be applied to a method for manufacturing a thin film transistor substrate for a liquid crystal display device.

According to the present invention, a conductive material is stacked and patterned on an insulating substrate to form a gate wiring including a gate line and a gate electrode connected to the gate line, and to form a gate insulating film. Subsequently, a semiconductor layer is formed on the gate insulating layer, and the data line includes a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode adjacent to the gate electrode and positioned opposite to the source electrode with respect to the gate electrode. Form the wiring. Subsequently, a protective film is laminated and patterned to form a first contact hole exposing the drain electrode, and a compound layer between the first metals is formed on the exposed drain electrode. Finally, a pixel electrode connected to the drain electrode is formed on the passivation layer through the compound layer between the first metals.

Here, the compound layer between the first metals is formed by laminating a metal film, performing annealing to form a compound layer between the metals, and then removing only the metal film through the entire surface etching. At this time, the metal film contains a transition metal, and the annealing is preferably carried out in the range of 200 ~ 400 ℃.

In addition, after the first contact hole is formed, it is preferable to perform dry cleaning using an etching solution or dry cleaning using plasma to clean the portion exposed through the contact hole.

It is preferable that the conductive material and the data wiring include an aluminum-based metal.

The gate line further includes a gate pad that receives a scan signal from the outside and transmits the scan signal to the gate line, and the data wire further includes a data pad that transmits an image signal from the outside to a data line, and the protective layer includes a data pad and a gate. And a second electrode and a third contact hole exposing the gate pad together with the insulating layer, and further forming a compound layer between the second and third metal on the gate pad and the data pad with the same layer as the compound layer between the first metal and the pixel electrode. An auxiliary gate pad and an auxiliary data pad connected to the compound layer between the second and third metals may be further formed on the same layer as each other through the second and third contact holes.

In this case, the pixel electrode may be formed of IZO.

The data line and the semiconductor layer may be formed by a photolithography process using a photoresist pattern having a partially different thickness, and the photoresist pattern may include a first portion having a first thickness, a second portion thicker than the first thickness, and no thickness. It is preferable to include the third portion except for the first and second portions.

In the photolithography process, the photoresist pattern may be formed using an optical mask including a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region.

In the photolithography process, the first portion may be positioned between the source electrode and the drain electrode, and the second portion may be positioned above the data line.

In order to control the transmittance of the first to third regions differently, a slit pattern smaller than the resolution of the translucent film or the exposure machine may be formed in the photomask.

The thickness of a 1st part is 1/2 or less with respect to the thickness of a 2nd part, The manufacturing method of the thin film transistor substrate for liquid crystal display devices.

An ohmic contact layer may be further included between the semiconductor layer and the data line, and the data line, the contact layer, and the semiconductor layer may be formed using one mask.

In the thin film transistor substrate for a liquid crystal display according to the present invention, a gate line including a gate line through which a scan signal extending in a horizontal direction is transmitted and a gate electrode of a thin film transistor that is part of the gate line are formed. A semiconductor pattern made of a semiconductor is formed on the gate insulating film covering the gate wiring, and a data line extending in the vertical direction on the semiconductor pattern or the gate insulating film is separated from the source electrode and the source electrode of the thin film transistor which are branches of the data line. The data line including the drain electrode of the thin film transistor facing the source electrode is formed. A passivation layer pattern having a first contact hole exposing the drain electrode is formed on the data line and the semiconductor pattern. A compound layer between the first metals is formed on the drain electrode through the first contact hole, and a contact hole is formed on the passivation layer pattern. A pixel electrode connected to the first compound layer is formed through the pixel compound.

The gate wiring further includes a gate pad connected to the gate line to receive a signal from the outside, and the data wiring further includes a data pad connected to the data line to receive a signal from the outside. And a second and third contact hole exposing the pad and the data pad, the compound layer further comprising a compound layer between the second and third metal formed on the gate pad and the data pad through the second and third contact holes. The semiconductor device may further include an auxiliary gate pad and an auxiliary data pad connected to the compound layer between the second and third metals through the second and third contact holes and formed of the same layer as the pixel electrode.

The pixel electrode may be made of IZO, which is a transparent conductive material. The gate wiring and the data wiring may be made of an aluminum-based metal, and the compound layer between the first metals may include a transition metal.

The semiconductor device may further include an ohmic contact layer pattern formed between the semiconductor pattern and the data line and heavily doped with impurities.

The data line may be formed only on the upper portion of the semiconductor pattern, the contact layer pattern may have the same shape as the data line, and the semiconductor pattern may have the same shape as the data line except for the channel portion.

Here, a contact improving layer containing a transition metal may be formed in place of the compound layer between the metals.

Then, with reference to the accompanying drawings, a method for manufacturing a wiring according to an embodiment of the present invention, a thin film transistor substrate for a liquid crystal display device including the wiring, and a method for manufacturing the same, the general knowledge in the technical field to which the present invention belongs. It will be described in detail to be easily carried out by those who have.

As a semiconductor device, particularly a wiring for transmitting a signal, an aluminum-based metal material having a low resistivity of 15 μΩcm or less is suitable to minimize signal delay. At this time, the wiring should be connected to the terminal of the semiconductor device in order to receive a signal from the outside, or to transmit a signal to the outside, it should not be easily corroded when contacting other materials in the manufacturing process. To this end, in the manufacturing method of the wiring according to the embodiment of the present invention, first, the first and second metal layers are sequentially stacked on the substrate, and the heat treatment process is performed by annealing to form an intermetallic compound between the first and second metal layers. After the layer is formed, the second metal layer is removed.

In this case, the first metal layer is preferably formed of an aluminum-based conductive material, and the second metal layer is preferably formed of a transition metal.

In addition, it is preferable to perform an annealing process in 200-400 degreeC.

In the method for manufacturing a wiring according to another embodiment of the present invention, the first metal layer is laminated, and an insulating film is formed thereon. Subsequently, the insulating film is patterned and patterned to form contact holes exposing a part of the first metal layer. Subsequently, the second metal layer is then laminated and annealed to form a compound layer between the metals only on top of the first metal layer exposed through the contact holes. Next, a conductive layer connected to the first metal layer is formed on the insulating film through the compound layer between the metals exposed through the contact hole.

The conductive layer may be a transparent conductive material, such as indium zinc oxide (IZO), in which a battery reaction does not occur with the aluminum-based conductive layer.

Such a method for manufacturing a wiring according to the present invention can be applied to a method for manufacturing a thin film transistor substrate for a liquid crystal display device.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along the line II-II.

A gate wiring made of an aluminum-based metal material having low resistance is formed on the insulating substrate 10. The gate wire is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26, and the gate insulating film 30 is provided with a gate pad along with a protective film 70 formed thereafter. It has a contact hole 74 that exposes 24.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24 in an island shape, and silicide or n-type impurities are doped with high concentration on the semiconductor layer 40. Resistive contact layers 54 and 56 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.

On the resistive contact layers 54 and 56 and the gate insulating layer 30, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), Data wires 62, 64, 66, 68 made of metal or a conductor such as titanium (Ti) are formed. The data line is formed in the vertical direction and crosses the gate line 22 to define a pixel, the data line 62 and the branch of the data line 62 and the source electrode 64 extending to the upper portion of the ohmic contact layer 54. ), Which is connected to one end of the data line 62 and is separated from the data pad 68 and the source electrode 64 to which an image signal from the outside is applied, and is opposite to the source electrode 64 with respect to the gate electrode 26. And a drain electrode 66 formed on the ohmic contact layer 56.

The data lines 62, 64, 66, and 68 are preferably formed of a single film of aluminum series, but may be formed of two or more layers. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials. Examples thereof include Cr / Al (or Al alloy) or Al / Mo. In the embodiment of the present invention, the data lines 62, 64, 66, and 68 may be formed of the lower layer 601 of Cr and the aluminum alloy. The upper film 602 is formed.

The passivation layer 70 is formed on the data lines 62, 64, 66, and 68 and the semiconductor layer 40 not covered by the data lines 62. In the passivation layer 70, contact holes 76 and 78 respectively exposing the drain electrode 66 and the data pad 68 are formed, respectively, and the contact holes 74 exposing the gate pad 24 together with the gate insulating layer 30. ) Is formed.

Intermetallic compound layers 94, 96, and 98 are formed on the gate pads 24, the drain electrodes 66, and the data pads 68 through the contact holes 74, 76, and 78, respectively. Here, the compound layers 94, 96, and 98 between the metals may include a gate wiring 24 and a drain electrode formed of an indium zinc oxide (IZO) pixel wiring 82, 86, 88, and an aluminum-based metal. 66 and a transition metal such as chromium or molybdenum or molybdenum alloy as the layer for improving the contact property of the upper layer 602 of the data pad 68.

The protective layer 70 is connected to the compound layer 96 between the metals on the drain electrode 66 through the contact hole 76 and through the pixel electrode 82 and the contact holes 74 and 78 respectively positioned in the pixel. An auxiliary gate pad 86 and an auxiliary data pad 88 connected with the compound layers 94 and 98 between the gate pads 24 and the metals on the data pads 68; It is.

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring.

In the structure according to the embodiment of the present invention, the low resistance includes the gate wirings 22, 24, and 26 and the data wirings 82, 84, 86, and 88, which are made of aluminum-based metal, so that the liquid crystal display having a high resolution is large. Applicable to the device. At the same time, the gate pad 24, the data pad 68, the drain electrode 66, and the auxiliary gate pad 86 made of the IZO, the auxiliary data pad 88, and the pixel electrode 82 respectively exhibit their contact characteristics. In order to improve the contact portion including the pad portion by preventing the aluminum-based metal from being corroded at each contact through the compound layer 94, 98, 96 between the metal to improve.

On the other hand, in the first embodiment of the present invention, the compound layers 94, 96, and 98 between metals containing transition metals such as chromium, molybdenum, or molybdenum alloys each have data wirings inside the contact holes 74, 76, and 78, respectively. Although the upper layer 602 of the aluminum-based metal film and the gate pad 24, the data pad 68 and the drain electrode 66 are formed on the contact improvement layer made of a transition metal layer, the contact hole 74, 76 and 78 may be formed in a shape that will be described in detail with reference to FIGS. 3 and 4.

3 is a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view of the thin film transistor substrate shown in FIG. 3 taken along line IV-IV.

As shown in Figures 3 and 4, most of the structure is similar to the first embodiment as shown in Figures 1 and 2.

However, each of the contact enhancement layers 94, 96, and 98 is formed to cover the contact holes 74, 76, and 78, and the auxiliary gate pad 86, the pixel electrode 82, and the data pad 98 are formed. Respectively, the contact improvement layers 94, 96, and 98 are formed so that it may completely cover.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having a structure according to the first and second embodiments of the present invention will be described in detail with reference to FIGS. 1 to 4 and FIGS. 3A to 10B.

First, as shown in FIGS. 5A and 5B, a low-resistance aluminum-based conductive film is laminated and patterned on the substrate 10 to a thickness of about 2,500 kV to form a gate line 22, a gate electrode 26, and a gate pad. The horizontal gate wiring including 24 is formed.

Next, as shown in FIGS. 6A and 6B, the gate insulating film 30, the semiconductor layer 40 made of amorphous silicon, and the three layer films of the doped amorphous silicon layer 50 are successively laminated and patterned using a mask. The semiconductor layer 40 and the doped amorphous silicon layer 50 are patterned to form an island-like semiconductor layer 40 and an ohmic contact layer 50 on the gate insulating layer 30 facing the gate electrode 24. .

Next, as shown in FIGS. 7A to 7B, the lower layer 601 made of molybdenum, molybdenum alloy, chromium, or the like has a thickness of 300 GPa or more, and the upper layer 602 made of aluminum-based metal having low resistance is 2,500. After stacking each one in order to a thickness of about 각각, patterning is performed by a photolithography process using a mask and connected to the data line 62 and the data line 62 intersecting the gate line 22 to extend above the gate electrode 26. The source electrode 64 and the data line 62 are separated from the data pad 68 and the source electrode 64 connected to one end thereof, and have a drain facing the source electrode 66 around the gate electrode 26. A data line including an electrode 66 is formed. Here, both the upper layer 602 and the lower layer 601 may be etched by wet etching, the upper layer 602 may be etched by wet etching, and the lower layer 601 may be etched by dry etching.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 64, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 54 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 8A and 8B, a protective film 70 made of silicon nitride or an organic insulating film is stacked, and patterned by dry etching together with the gate insulating film 30 by a photolithography process using a mask. Contact holes 74, 76, and 78 are formed to expose the pad 24, the drain electrode 66, and the data pad 68. Subsequently, the surfaces of the gate pad 24 and the drain electrode 66 and the upper film 602 of the data pad 68 exposed through the contact holes 74, 76, and 78 are dry cleaned. At this time, examples of the gas to be used include SF ₆ / O ₂ .

Next, as shown in FIGS. 9A and 9B, chromium, molybdenum or molybdenum alloys, or titanium, are formed on the substrate 10 to form a compound layer between metals capable of improving contact characteristics between IZO and an aluminum-based metal. Transition metal films, such as these, are laminated to a thickness of 200 kPa or more. Subsequently, annealing is performed at a range of 200 ° C. to 400 ° C., and the gate pad 24 and the drain electrode 66 and the aluminum pad-based metal of the data pad 68 are exposed through the contact holes 74, 76, and 78. After forming compound layers 94, 96, and 98 between metals including transition metals such as chromium, molybdenum, molybdenum alloy, titanium, or the like, on the upper layer 602, the metal layer is removed through full etching. At this time, the metal film is removed, but the compounds 94, 96 and 98 between the metals formed through the annealing remain. In an embodiment of the present invention, the transition metal film was laminated to a thickness of about 300 kPa and annealing was performed at about 300 ° C. for 30 minutes, and the thickness of the compound layers 84, 96, and 98 between the metals formed was 60 kPa or less. .

Here, in order to form a good compound layer (94, 96, 98) between the metal formed between the upper film 602 made of aluminum-based metal and the transition metal film, the protective film 70 is dry-etched to contact holes 74. , 76, 78), the surface of the upper layer 602 made of aluminum-based metal is preferably subjected to wet cleaning using an etchant or dry cleaning using a plasma.

On the other hand, in the case of forming the contact improvement layers 94, 96, and 98 as in the second embodiment, as shown in FIGS. 10A and 10B, a metal film made of a transition metal or an alloy thereof is laminated, and then a mask is applied. The contact enhancement layers 94, 96, and 98 are formed by the photolithography process.

In this case, the mask is not required to be formed as in the first embodiment, but one mask is additionally used to be formed as in the second embodiment.

Next, as shown in FIGS. 1 and 2 and 3 and 4, the IZO film is laminated and patterned using a mask to form a compound layer between the metals on the upper portion of the drain electrode 66 through the contact hole 76 or the like. The compound or contact enhancement layers 94 and 98 between the gate pad 24 and the metal on the data pad 68 through the pixel electrodes 82 and the contact holes 74 and 78 connected to the contact enhancement layer 96. And an auxiliary gate pad 86 and an auxiliary data pad 88 respectively connected to each other.

In the manufacturing method according to the exemplary embodiment of the present invention, the compound layer or the contact improving layer 94, 96, 98 between the metals is formed before the IZO film is laminated in order to improve the contact property between the metal IZO and the aluminum-based metal. Therefore, it is possible to prevent corrosion occurring at the contact portion including the pad and to secure the reliability of the contact portion.

As described above, the method can be applied to a manufacturing method using five or six masks, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 11 to 12.

11 is a layout view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention, and FIGS. 12 and 13 are lines XII-XII 'and XIII-XIII', respectively, of the thin film transistor substrate shown in FIG. A cross-sectional view taken along the line.

First, a gate line including a gate line 22, a gate pad 24, and a gate electrode 26 made of an aluminum-based metal is formed on the insulating substrate 10 as in the first embodiment. The gate wiring includes a sustain electrode 28 that is parallel to the gate line 22 on the substrate 10 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and 28 to cover the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56, and 58, a data line made of an aluminum-based conductive material having low resistance is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 64 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65, separated from the data line portions 62, 64, and 65, of the source electrode 65 with respect to the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 68 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 68 for the storage capacitor is also not formed.

The data lines 62, 64, 65, 66, 68 may also be formed in a single layer like the gate lines 22, 24, 26, 28, but similarly to the first embodiment, chromium or molybdenum or molybdenum alloys or tantalum Or it may be formed of a double film containing titanium.

The contact layer patterns 55, 56, and 58 lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has the same shape as the wirings 62, 64, 65, 66 and 68. That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 64 and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 68 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shapes as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 57 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 68 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, the data line parts 62, 64, 65, in particular, the source electrode 65 and the drain electrode 66 are separated from the channel portion C of the thin film transistor, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode is separated. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

The passivation layer 70 is formed on the data wires 62, 64, 65, 66, and 68, and the passivation layer 70 forms the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor. The contact holes 71, 73, and 74 are exposed, and the contact holes 72 are exposed to expose the gate pad 24 together with the gate insulating film 30. As shown in FIG. The passivation layer 70 may be made of an organic insulating material such as silicon nitride or acrylic.

Similarly to the first embodiment, the upper portion of the drain electrode 66, the gate pad 24, the data pad 64, and the conductor pattern 68 for the storage capacitor are exposed through the contact holes 71, 72, 73, and 74. Compound layers 91, 92, 93, and 94 between metals are formed in the substrate.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (IZO). The pixel electrode 82 is physically and electrically connected to the compound layer 91 between the metals on the drain electrode 66 through the contact hole 71 to be imaged. Receive a signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. The pixel electrode 82 is also connected to the buffer layer 94 on the conductive capacitor pattern 68 for the storage capacitor through the contact hole 74 to transmit an image signal to the conductor pattern 68. On the other hand, on the compound layers 92 and 93 between the metals on the gate pad 24 and the data pad 64, the auxiliary gate pad 84 and the auxiliary data pad (connected to them through the contact holes 72 and 73, respectively) 86 is formed, and these are not essential to serve to protect the pads and to protect the pads 24 and 64 from the external circuit device, and their application is optional.

Here, the transparent IZO is mentioned as an example of the material of the pixel electrode 82, but may be formed of indium tin oxide (ITO) or a transparent conductive polymer, or the like. In the case of a reflective liquid crystal display, an opaque conductive material is used. You may.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 11 to 13 using four masks will be described in detail with reference to FIGS. 11 to 13 and FIGS. 14A to 21C. Shall be.

 First, as shown in FIGS. 14A to 14C, the gate line 22, the gate pad 24, and the gate electrode 26 are formed on the substrate 10 by a photolithography process using a first mask as in the first embodiment. And a sustain electrode 28 to form a gate wiring made of an aluminum-based metal having low resistance.

Next, as shown in FIGS. 15A and 15B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 kV to 5,000 kV, 500 kV to 2,000 kV, and 300 kV using chemical vapor deposition. Continuously deposited to a thickness of 600 to 600 kW, and then depositing a conductor layer 60 to a thickness of 1,500 kW to 3,000 kW by sputtering or the like, based on an aluminum-based metal having low resistance, and then depositing a photoresist film 110 thereon. Apply at a thickness of μm to 2 μm.

Thereafter, the photosensitive film 110 is irradiated with light through a second mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 16B and 16C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure, and in the case of using a translucent film, the transmittance is different in order to control the transmittance when fabricating a mask. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 17A and 17B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

When the conductor layer 60 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in Figs. 17A and 17B, only the conductor layers of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 68 for the storage capacitor, are shown. All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 67 and 68 have the same shape as the data lines 62, 64, 65, 66, and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 18A and 18B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 thereunder are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions where the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 18A and 18B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 indicate the intermediate layer pattern under the source / drain conductor pattern 67 and the intermediate layer pattern under the storage capacitor conductor pattern 68, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as illustrated in FIGS. 19A and 19B, the source / drain conductor pattern 67 of the channel portion C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in Fig. 2). For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 15B, a part of the semiconductor pattern 42 may be removed to reduce the thickness, and the second part 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching should be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After the data wirings 62, 64, 65, 66, and 68 are formed in this manner, as shown in FIGS. 20A to 20C, silicon nitride is deposited by CVD or spin-coated an organic insulating material to have a thickness of 3,000 Å or more. The protective film 70 is formed. Subsequently, the passivation layer 70 is etched together with the gate insulating layer 30 by using a third mask to form the drain electrode 66, the gate pad 24, the data pad 64, and the conductive pattern 68 for the storage capacitor, respectively. The exposed contact holes 71, 72, 73, 74 are formed.

Next, as shown in FIGS. 21A to 21C, contact holes 71 and 72 in a plasma state using a gas such as SF ₆ / O ₂ or CF ₄ / O ₂ or BCl ₃ / Cl ₂ or BCl ₃ / HBR ₂ . Dry clean the drain electrode 66, the gate pad 24, the data pad 64, and the conductive pattern 68 for the storage capacitor, which are exposed through the substrates 73 and 74, and then, on the substrate 10, As in the first exemplary embodiment, the drain electrode 66, the gate pad 24, and the data pad exposed through the contact holes 71, 72, 73, and 74 are removed by stacking and annealing the transition metal layer and removing only the metal layer through front etching. 64) and a compound layer 91, 92, 93, 94 between metals containing a transition metal is formed on the aluminum-based metal film exposing the conductor pattern 68 for the storage capacitor.

Finally, as shown in FIGS. 11 to 13, the IZO layer having a thickness of 400 kV to 500 kV is deposited and etched using a fourth mask to drain the electrode 66 through the intermetallic compound layers 91 and 94. And an auxiliary gate pad 84 connected to the gate pad 24 and a compound layer 93 between the metals, the pixel electrode 82 connected to the conductor pattern 68 for the storage capacitor, and the compound layer 92 between the metals. An auxiliary data pad 86 connected to the data pad 64 is formed.

In the third embodiment of the present invention, in addition to the effects according to the first embodiment, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 and the semiconductor patterns 42 thereunder. , 48) may be formed using one mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.

In this embodiment of the present invention, a compound layer or a contact improving layer between metals including transition metals such as chromium or molybdenum or molybdenum alloy is formed therebetween in order to improve contact characteristics between the aluminum-based metal and the IZO film.

As described above, according to the present invention, a buffer layer made of chromium, molybdenum, or molybdenum alloy is formed between the aluminum-based metal film and the IZO film to secure the pad part and to form a wiring with low resistance aluminum or aluminum alloy. The characteristics of a high-definition product can be improved. In addition, the manufacturing process may be simplified to manufacture a thin film transistor substrate for a liquid crystal display, thereby simplifying the manufacturing process and reducing the manufacturing cost.

Claims (36)

Stacking a first metal layer on the substrate; Stacking a second metal layer made of a transition metal on the first metal layer; Performing a heat treatment process by annealing to form a compound layer between metals between the first and second metal layers, Removing the second metal layer, Forming a conductive layer connected to the first metal layer through the intermetallic compound layer Method for producing a wiring comprising a. In claim 1, And the first metal layer is formed of an aluminum-based conductive material. delete In claim 1, Said annealing is a manufacturing method of the wiring performed in 200-400 degreeC. Stacking a first metal layer on the substrate; Forming an insulating film covering the first metal layer; Etching the insulating film to form a contact hole exposing the first metal layer; Stacking a second metal layer on the insulating layer; Performing a heat treatment process by annealing to form a compound layer between metals between the first and second metal layers in contact with each other through the contact hole, Removing the second metal layer, Forming a conductive layer on the insulating layer, the conductive layer being connected to the first metal layer through the intermetallic compound layer; Method for producing a wiring comprising a. In claim 5, And the first metal layer is formed of an aluminum-based conductive material. In claim 5, And the second metal layer is formed of a transition metal. In claim 5, Said annealing is a manufacturing method of the wiring performed in 200-400 degreeC. Stacking and patterning a conductive material on an insulating substrate to form a gate line including a gate line and a gate electrode connected to the gate line; Forming a gate insulating film, Forming a semiconductor layer on the gate insulating layer; Forming a data line including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode adjacent to the gate electrode, and a drain electrode opposite to the source electrode; Stacking and patterning a protective film to form a first contact hole exposing the drain electrode, Forming a compound layer between the first metals on the exposed drain electrode, Forming a pixel electrode on the passivation layer, the pixel electrode being connected to the drain electrode through the compound layer between the first metals; Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 9, Forming the compound layer between the first metal,  Laminating a metal film, Annealing the metal film to form a compound layer between the metals; And removing only the metal layer through front surface etching. In claim 10, The metal film is a method of manufacturing a thin film transistor substrate for a liquid crystal display device containing a transition metal. In claim 10, The annealing step is a manufacturing method of a thin film transistor substrate for a liquid crystal display device performed in the range of 200 ~ 400 ℃. In claim 9, After the first contact hole forming step, A method of manufacturing a thin film transistor substrate for a liquid crystal display device further comprising the step of performing dry cleaning using an etchant or dry cleaning using a plasma. In claim 9, The conductive material is an aluminum-based metal manufacturing method of a thin film transistor substrate for a liquid crystal display device. In claim 9, The data line is a manufacturing method of a thin film transistor substrate for a liquid crystal display device containing an aluminum-based metal. In claim 9, The gate line further includes a gate pad receiving a scan signal from the outside and transferring the scan signal to the gate line, The data line further includes a data pad which transfers an image signal from an external source to the data line. The passivation layer has second and third contact holes exposing the gate pad together with the data pad and the gate insulating layer. Forming a compound layer between the second and third metals on the gate pad and the data pad, the same layer as the compound layer between the first metal, And forming an auxiliary gate pad and an auxiliary data pad respectively connected to the compound layer between the second and third metals through the second and third contact holes in the same layer as the pixel electrode. Manufacturing method. In claim 9, And the pixel electrode is formed of IZO. In claim 9, And the data line and the semiconductor layer are formed by a photolithography process using a photoresist pattern having a partially different thickness. The method of claim 18, The photoresist pattern may include a first part having a first thickness, a second part thicker than the first thickness, and a third part having no thickness and excluding the first and second parts. Manufacturing method. The method of claim 19, In the photolithography process, the photoresist pattern is formed using a photomask including a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region. Method for manufacturing a thin film transistor substrate for a device. The method of claim 20, And forming the first portion between the source electrode and the drain electrode and the second portion over the data line in the photolithography process. The method of claim 21, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, in which a slit pattern smaller than the resolution of a translucent film or an exposure machine is formed in the photomask in order to differently control the transmittance of the first to third regions. The method of claim 19, And a thickness of the first portion is 1/2 or less with respect to a thickness of the second portion. In claim 9, And a resistive contact layer between the semiconductor layer and the data line. The method of claim 24, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the data line, the contact layer, and the semiconductor layer are formed using one mask. Board, A gate line formed on the substrate, the gate line including a gate line through which a scan signal extending in a horizontal direction is transmitted, and a gate electrode of a thin film transistor that is part of the gate line; A gate insulating film covering the gate wiring, A semiconductor pattern formed on the gate insulating film, having a channel portion, and formed of a semiconductor; A data line formed on the semiconductor pattern or the gate insulating layer and extending in a vertical direction, a source electrode of the thin film transistor which is a branch of the data line, and separated from the source electrode and facing the source electrode with respect to the channel part; A data wiring including a drain electrode of the thin film transistor, A passivation layer pattern formed on the data line and the semiconductor pattern and having a first contact hole exposing the drain electrode; A compound layer between the first metals formed on the drain electrode through the first contact hole; And a pixel electrode formed on the passivation layer pattern and connected to the first compound layer through the contact hole. The method of claim 26, The gate line further includes a gate pad connected to the gate line to receive a signal from the outside, and the data line further includes a data pad connected to the data line to receive a signal from the outside, The passivation layer pattern and the gate insulating layer have second and third contact holes exposing the gate pad and the data pad. And a compound layer between the second and third metals formed on the gate pad and the data pad through the second and third contact holes, The thin film transistor further comprises an auxiliary gate pad and an auxiliary data pad connected to the compound layer between the second and third metals through the second and third contact holes and formed of the same layer as the pixel electrode. Board. The method of claim 26, The pixel electrode is a thin film transistor substrate for a liquid crystal display device made of IZO, a transparent conductive material. The method of claim 26, The gate wiring is a thin film transistor substrate for a liquid crystal display device made of an aluminum-based metal. The method of claim 26, The data line is a thin film transistor substrate for a liquid crystal display device made of an aluminum-based metal. The method of claim 26, The compound layer between the first metal is a thin film transistor substrate for a liquid crystal display device comprising a transition metal. The method of claim 26, And a resistive contact layer pattern formed between the semiconductor pattern and the data line and heavily doped with impurities. The method of claim 26, The data line is a thin film transistor substrate for a liquid crystal display device is formed only on the upper portion of the semiconductor pattern. The method of claim 33, And the contact layer pattern has the same shape as that of the data line. The method of claim 34, A thin film transistor substrate for a liquid crystal display device, wherein the semiconductor pattern has the same shape as the data line except for the channel portion. Board, A gate line formed on the substrate, the gate line including a gate line through which a scan signal extending in a horizontal direction is transmitted, and a gate electrode of a thin film transistor that is part of the gate line; A gate insulating film covering the gate wiring, A semiconductor pattern formed on the gate insulating layer and formed of a semiconductor; A data line formed on the semiconductor pattern or the gate insulating layer and extending in a vertical direction, a source electrode of the thin film transistor which is a branch of the data line, and separated from the source electrode to face the source electrode with respect to the gate electrode; A data line including a drain electrode of the thin film transistor; A passivation layer pattern formed on the data line and the semiconductor pattern and having a first contact hole exposing the drain electrode; A contact improvement layer formed on the drain electrode through the first contact hole and formed of a transition metal, And a pixel electrode formed on the passivation pattern and connected to the contact enhancement layer through the contact hole.

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