KR100878265B1 - Method of manufacturing thin film transistor substrate - Google Patents

Abstract

A gate wiring made of a material having a low specific resistance such as aluminum (Al) or an aluminum alloy is formed on the insulating substrate, and a gate insulating film made of silicon nitride (SiN _x ) is formed on the gate wiring. A semiconductor layer made of a semiconductor such as amorphous silicon is formed on the gate insulating film, and an ohmic contact layer made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of silicide or n-type impurities is formed on the semiconductor layer. . A data line made of aluminum (Al) or an aluminum alloy is formed on the ohmic contact layer and the gate insulating film, and a protective film made of silicon nitride is formed on the data line. A contact hole is formed in the passivation layer to expose a portion of the data line and the gate line. A pixel electrode and an auxiliary gate pad including a contact reinforcement layer and an IZO layer electrically connected to the data line and the gate line exposed through the contact hole are formed on the passivation layer. And an auxiliary data pad.

Description

The manufacturing method of a thin film transistor substrate {METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL}

1 is a layout view of a thin film transistor substrate according to an embodiment of the present invention,

FIG. 2 is a cross-sectional view taken along line II-II 'of FIG. 1,

3A is a layout view of a thin film transistor substrate in a first step of manufacturing a thin film transistor substrate for a liquid crystal display according to an embodiment of the present invention;

3B is a cross sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

FIG. 4a is a layout view in the next step of FIG. 3a;

4B is a cross sectional view taken along the line IVb-IVb ′ in FIG. 4A;

FIG. 5A is a layout view of the next step of FIG. 4A;

FIG. 5B is a cross sectional view taken along the line Vb-Vb ′ in FIG. 5A;

FIG. 6a is a layout view in the next step of FIG. 5a;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A.

The present invention relates to a thin film transistor substrate.

In general, since the wiring in the thin film transistor substrate is used as a means for transmitting a signal, it is required to minimize the signal delay.

In this case, in order to prevent signal delay, the wiring generally uses a low-resistance metal material, particularly an aluminum-based metal material such as aluminum (Al) or aluminum alloy. However, since aluminum-based wiring is weak in physical or chemical properties, corrosion occurs when connected to other conductive materials at the contact portion, thereby degrading the characteristics of the semiconductor device. In the liquid crystal display, in order to eliminate such a problem, it is common to reinforce aluminum by using indium tin oxide (ITO), which is used as a pixel electrode, as an auxiliary pad in a pad part.

However, corrosion due to battery effect occurs between aluminum or aluminum alloy and ITO, and the aluminum-based wiring may be disconnected by the ITO etchant during the ITO etching process, so that the IZO ( indium zinc oxide) has been introduced.

However, aluminum is a well-oxidized material and IZO is an oxide-based material. Therefore, the surface of aluminum or aluminum alloy is oxidized while undergoing annealing during thin film transistor substrate and liquid crystal process, and thus the contact resistance with IZO is increased. An increasing problem is occurring.

Therefore, the technical problem to be achieved by the present invention is to minimize the signal delay by minimizing the contact resistance between the IZO and the wiring of aluminum or aluminum alloy.

The thin film transistor substrate according to the present invention for achieving the above object has a pixel electrode or an auxiliary pad made of a contact reinforcing layer and a transparent conductive film.

Specifically, in the thin film transistor substrate according to the present invention, a gate wiring including a gate line and a gate electrode is formed on the insulating substrate in a horizontal direction, and a gate insulating film is formed on the gate wiring. A data line including a data line, a source electrode, and a drain electrode is formed on the gate insulating layer, and a pixel electrode made of a contact reinforcement layer and a transparent conductive film is formed in a pixel region where the gate line and the data line cross each other. The thin film transistor is formed by being connected to the gate wiring, the data wiring, and the pixel electrode.

In addition, the semiconductor device may further include a passivation layer formed between the data line and the pixel electrode and having a first contact hole for connecting the drain electrode and the pixel electrode, wherein the drain electrode is in contact with the contact reinforcing layer.

The auxiliary gate pad and the auxiliary data pad may further include a gate pad connected to an end of the gate line and a data pad connected to an end of the data line, the auxiliary gate pad and the auxiliary data pad including a contact reinforcement layer formed of the same layer as the pixel electrode and a transparent conductive film. The semiconductor device may further include a passivation layer formed between the data line and the pixel electrode and having a second contact hole and a third contact hole connected to the gate pad and the data pad. The second contact hole and the third contact hole may be further included. The data pad and the gate pad are preferably in contact with the contact reinforcement layer of the auxiliary gate pad and the auxiliary data pad.                     

On the other hand, the contact reinforcing layer is preferably made of any one of chromium, chromium alloy, molybdenum, molybdenum alloy, silver, silver alloy. In addition, the contact reinforcing layer may be formed in the same pattern as the transparent conductive film, it is preferable that the thickness of the contact reinforcing layer is formed to 500 Å or less.

Moreover, it is preferable that the said transparent conductive film is IZO.

Then, a thin film transistor substrate and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art can easily carry out the present invention.

First, the structure of a thin film transistor substrate manufactured according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1.

Gate wirings 22, 24, and 26 are formed on the insulating substrate 10 including a conductive film made of a material having a low specific resistance such as aluminum (Al) or aluminum alloy (Al alloy). The gate wire is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate lines 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 30 of the gate electrode 24, and n + hydrogenation in which silicide or n-type impurities are heavily doped is formed on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as amorphous silicon are formed by separating two portions around the gate electrode 24.

On the ohmic contacts 55 and 56 and the gate insulating layer 30, data lines 62, 65, 66, and 68 made of aluminum (Al), an aluminum alloy, or the like are formed.

The data wires 62, 65, 66, and 68 are formed in the vertical direction and are connected to the data line 62 and the data line 62 defining the pixel by crossing the gate line 22, and the ohmic contact layer 55. It is connected to one end of the source electrode 65 and the data line 62 which extends to the upper part of the data pad 68 and the gate electrode 26 which are separated from the data pad 68 and the source electrode 65 to which an image signal from the outside is applied. ) And a drain electrode 66 formed over the ohmic contact layer 56 opposite the source electrode 65.

A protective film 70 made of silicon nitride is formed on the data lines 62, 65, 66, and 68.

In the passivation layer 70, contact holes 76 and 78 exposing the drain electrode 66 and the data pad 68 and contact holes 74 exposing the gate pad 24 are formed. Here, the contact hole 74 exposing the gate pad 24 is also formed in the gate insulating film 30.

On the passivation layer 70, contact reinforcement layers 861, 821, and 881 are electrically connected to the gate pads 24, the drain electrodes 66, and the data pads 68 through the contact holes 74, 76, and 78. The auxiliary gate pad 862, the pixel electrode 822, and the auxiliary data pad 882 are formed on the upper portion of the substrate in the same pattern as the contact reinforcement layers 861, 821, and 881. Here, the contact reinforcing layers 821, 861, and 881 may be made of a material such as chromium or chromium alloy, molybdenum or molybdenum alloy, silver or silver alloy, and the pixel electrode 822 and the auxiliary gate and auxiliary data pads 862 and 882. ) May consist of IZO or ITO.

In other words, the pixel electrode 822, the auxiliary gate pad 862, and the auxiliary data pad 882 are connected to the drain electrode 66 and the gate pad 24 through the contact reinforcement layers 821, 861, and 881 formed thereunder. And is electrically connected to the data pad 68 to prevent corrosion or an oxide film from being formed between the wires 24, 66, 68 made of aluminum or an aluminum alloy, and the IZO films 822, 862, and 882. The resistance of the contact can be minimized.

1 and 2, the pixel electrode 822 overlaps the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 822 is disposed on the same layer as the gate lines 22, 24, and 26. It is also possible to add a storage capacitor wiring.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 6B.

First, as illustrated in FIGS. 3A and 3B, a gate electrode 22 which is a part of the gate line 22 and the gate line 22 extending in the horizontal direction by stacking and patterning a material such as aluminum or an aluminum alloy on the substrate 10 is formed. A gate wiring including a 26 and a gate pad 24 is formed.

Next, as shown in FIGS. 4A and 4B, three layers of the gate insulating film 30 made of silicon nitride, the semiconductor layer 40 made of amorphous silicon, and the ohmic contact layer 50 made of doped amorphous silicon are successively formed. The semiconductor layer 40 and the ohmic contact layer 50 are formed on the gate insulating layer 30 positioned on the gate electrode 24 by patterning the semiconductor layer 40 and the doped amorphous silicon layer 50 by laminating and photolithography. Form. In this case, although the semiconductor layer and the ohmic contact layer are formed only on the gate electrode, they may be formed along the data line.

Next, as shown in FIGS. 5A to 5B, a conductive film made of aluminum or an aluminum alloy is stacked and patterned by a photolithography process using a mask to intersect the data line 62 and the data line (intersecting the gate line 22). A source electrode 65 connected to 62 and extending to an upper portion of the gate electrode 26, a data pad 68 and a source electrode 64 connected to one end of the data line 62, and separated from the gate electrode ( A data line including a drain electrode 66 facing the source electrode 65 is formed around 26.

Subsequently, the doped amorphous silicon layer pattern 50 is separated by etching by removing the doped amorphous silicon layer pattern 50 that is not covered by the data lines 62, 65, 66, and 68, thereby forming the semiconductor layer pattern 40. Expose Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform an oxygen plasma treatment.

Next, as shown in FIGS. 6A and 6B, an inorganic insulating film such as silicon nitride is deposited or an organic film is coated to form a protective film 70. Subsequently, the passivation layer 70 is patterned together with the gate insulating layer 30 by a photolithography process using a mask to expose the gate pads 24, the drain electrodes 66, and the data pads 68. 78).

Next, as shown in FIGS. 1 and 2, the contact reinforcement layer and the IZO film are sequentially stacked and photo-etched to connect the contact reinforcement layer 821 and the pixel electrode connected to the drain electrode 66 through the second contact hole 76. The contact reinforcement layers 861 and 881 and the auxiliary gate pad 862 and the auxiliary data pad, which are connected to the gate pad 24 and the data pad 68 through the 822 and the first and third contact holes 74 and 78, respectively. 882 is formed respectively.

At this time, it is preferable to use chromium or chromium alloy, molybdenum or molybdenum alloy, silver or silver alloy as the material of the contact reinforcing layers 821, 861 and 881. Further, the contact reinforcing layers 821, 861, and 881 are formed so thin that they do not interfere with light transmission in the transmissive panel, and the thickness thereof is preferably 500 kPa or less.

The invention is susceptible to various modifications and implementations without departing from the scope of the following claims.

 According to the present invention, by forming a contact reinforcing layer for reinforcing contact characteristics between the wiring of aluminum or aluminum alloy and the IZO film, it is possible to prevent the formation of an oxide film therebetween, thereby minimizing the contact resistance of the contact portion.

Claims (9)

delete delete delete delete delete delete delete Forming a gate wiring including a gate line and a gate electrode on the insulating substrate, Forming a gate insulating film on the gate wiring; Forming a data line including a data line, a source electrode, and a drain electrode on the gate insulating layer; Forming a passivation layer on the data line; Sequentially stacking a contact reinforcement layer and a transparent conductive film on the protective film, and Forming a pixel electrode by photo-etching the transparent conductive layer and the contact reinforcement layer using the same mask Method of manufacturing a thin film transistor substrate comprising a. In claim 8, The contact reinforcing layer is a method of manufacturing a thin film transistor substrate including any one selected from chromium, chromium alloy, molybdenum, molybdenum alloy, silver, silver alloy.

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