KR100783696B1 - Thin film transistor substrate for liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

A horizontal gate line including a gate line, a gate electrode, and a gate pad is formed of an aluminum-based conductive film on the insulating substrate. Next, a gate insulating film is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. Subsequently, a conductive film of a double film made of chromium and an upper film of AlNd is stacked and patterned in order to form a data line including a data line, a source electrode, a drain electrode, and a data pad crossing the gate line. Next, after the protective layer is stacked, the mask is patterned by dry etching in a dry etching chamber together with the gate insulating layer in a photolithography process to form contact holes that expose the drain electrode, the data pad, and the gate pad, respectively. Subsequently, in the dry etching chamber, N ₂ gas and Ar gas are mixed to form a plasma reaction layer on the AlNd surface of the drain electrode, the data pad, and the gate pad exposed through the contact hole. Subsequently, ITO or IZO is stacked and patterned to form pixel electrodes, auxiliary data pads, and auxiliary gate pads connected to the drain electrodes, the data pads, and the gate pads, respectively.

Aluminum, ITO, IZO, Contact Characteristics, Plasma, Chamber

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method thereof {THIN FILM TRANSISTOR SUBSTRTE ADDRESSED LIQUID CRYSTAL DISPLAY INCLUDING THE CONTACT STRUCTURE AND METHOD MANUFACTURING THE SAME}

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

2A and 2B are cross-sectional views of the thin film transistor substrate for the liquid crystal display device shown in FIG. 1 taken along a line П- П ',

3A, 4A, 5A, and 6A are layout views of a thin film transistor substrate in an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIG. 2A according to a first embodiment of the present invention;

3B is a cross-sectional view taken along line IIIb-IIIb 'in FIG. 3A,

FIG. 4B is a cross-sectional view taken along line IVb-IVb 'in FIG. 4A and is a cross-sectional view showing the next step of FIG. 3B;

FIG. 5B is a cross-sectional view taken along the line Vb-Vb 'of FIG. 5a and illustrates the next step of FIG. 4b;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A and is a cross-sectional view showing the next step of FIG. 5B;                 

7A and 7B are diagrams illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIG. 2B.

FIG. 7A is a cross-sectional view taken along line IVb-IVb 'of FIG. 4A and is a cross-sectional view showing the next step of FIG. 3B;

FIG. 7B is a cross-sectional view taken along the line Vb-Vb 'of FIG. 5a and is a cross-sectional view showing the next step of FIG. 4b;

8 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

9A and 9B are cross-sectional views of the thin film transistor substrate for the liquid crystal display device shown in FIG. 8 taken along the lines Ⅷ'- '' and Ⅸ- '',

10A is a layout view of a thin film transistor substrate for a liquid crystal display device in the first step of manufacturing according to the second embodiment of the present invention;

10B and 10C are cross-sectional views taken along the lines 'b-'b' and 'c -'- c' of FIG. 10A, respectively.

11A and 11B are cross-sectional views at the next stage of FIGS. 10B and 10C, respectively;

12A is a layout view of a thin film transistor substrate for a liquid crystal display device in the following steps of FIGS. 11A and 11B;

12B and 12C are cross-sectional views taken along the lines IIb-IIb 'and IIC-IIc' of FIG. 12A, respectively;

13A, 14A, 15A, and 13B, 14B, and 15B are cross-sectional views taken along the lines IIb-XIIb 'and XIIc-XIIc' of FIG. 12A, respectively, and are cross-sectional views at the next steps of FIGS. 12B and 12C,

FIG. 16A is a layout view of a thin film transistor substrate for a liquid crystal display device in the following steps of FIGS. 15A and 15B;

16B and 16C are cross-sectional views taken along the lines VIB-VIVI 'and VIVI-VIVI' in FIG. 16A, respectively.

The present invention relates to a structure of a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

 Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

In such a liquid crystal display, a wiring for transmitting a scan signal or a data signal to a thin film transistor or an electrode such as a gate line or a data line is made of aluminum (Al) or an aluminum alloy having a low resistance to minimize signal delay. It is preferable to form an aluminum-based metal material such as the like. However, because aluminum-based wiring is weak in physical or chemical properties, when connected with other conductive materials at the contacts, corrosion occurs due to battery effects, resulting in an increase in contact resistance.

In particular, when used as an indium tin oxide (ITO) or indium zinc oxide (IZO) as an auxiliary pad to reinforce the pixel electrode or the pad part, the contact resistance increases due to corrosion of the aluminum-based metal in contact with it, thereby reducing the reliability of the contact part. There is a problem.

In the liquid crystal display device manufacturing method, the substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, in order to reduce the production cost, it is desirable to reduce the number of masks.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same, which can have low resistance wiring and ensure reliability of a contact portion.

In order to solve this problem, in the present invention, the wiring is formed of an aluminum-based conductive material having a low resistance, and a plasma reaction layer is formed at the contact portion of the wiring to improve the contact characteristics of the wiring.                     

In the method for manufacturing a substrate of a thin film transistor according to the present invention, first, a gate wiring including an aluminum-based first conductive film and including a gate line and a gate electrode is formed on an insulating substrate, and is insulated from the gate wiring, and the second aluminum-based A data line including a data line including a conductive film, a source electrode, and a drain electrode is formed. Next, a protective film covering the gate wiring and the data wiring is laminated and patterned to form a contact hole exposing the gate wiring or the data wiring. Next, a transparent conductive film pattern connected to the gate wiring or the data wiring is formed through the contact hole. At this time, the surface of the first or second conductive film of the gate wiring or the data wiring is subjected to plasma treatment.

       Here, the plasma treatment step may be performed in the sputter chamber after etching the protective film or before laminating the ITO or IZO.

      It can also be performed after data wiring is stacked.

At this time, the plasma treatment step is used by mixing N ₂ or NH ₃ gas and Ar gas.

      The gate wiring further includes a gate pad connected to the gate line, the data wiring further includes a data pad connected to the data line, and the contact hole includes first and second openings exposing the drain electrode, the data pad, and the gate pad, respectively. A transparent conductive film pattern including a second and third contact hole, wherein the transparent conductive film pattern is connected to the drain electrode through the first contact hole, and auxiliary data connected to the data pad and the gate pad through the second and third contact holes, respectively. It is preferable to form a transparent conductive film pattern from ITO or IZO, including a pad and an auxiliary gate pad.

      Next, a thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. do.

First, the structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1, 2A, and 2B.

FIG. 1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, and FIGS. 2A and 2B are cross-sectional views illustrating the thin film transistor substrate shown in FIG.

First, as shown in FIGS. 1 and 2A, in the thin film transistor substrate according to the first embodiment of the present invention, the gate wirings 22 and 24 including aluminum (Al) or aluminum alloy (Al alloy) on the insulating substrate 10 may be used. , 26). The gate wirings 22, 24, and 26 are connected to the gate lines 22 extending in the horizontal direction, the gate pads 24 connected to the ends of the gate lines 22 to receive gate signals from the outside, and to transfer the gate signals to the gate lines. And a gate electrode 26 of the thin film transistor connected to the gate line 22.

Here, the gate wirings 22, 24, and 26 are preferably formed of a single aluminum-based film as in the exemplary embodiment of the present invention, but chromium (Cr), molybdenum (Mo), and the like, which have excellent contact properties with other materials, are described. It may be formed of a multilayer including a conductive film made of.                     

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiNx) covers the gate wirings 22, 24, and 26, and the gate insulating film 30 is formed along with a protective pad 70 formed thereafter. Has a contact hole 74 exposing 24.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24, and n having a high concentration of silicide or n-type impurities is formed on the semiconductor layer 40. ⁺ Resistance contact layers 55 and 56 made of a material such as hydrogenated amorphous silicon are formed, respectively.

On the resistive contact layers 55 and 56 and the gate insulating layer 30, an upper layer made of a lower layer 650, 660, 680 made of chromium (Cr) or molybdenum (Mo), or an aluminum-based conductive material such as Al-Nd. Double data structures 62, 65, 66, and 68 including films 651, 661, and 681 are formed.

The data line is formed in the vertical direction and intersects with the gator line 22 and is connected to the data line 62 and the data line 62 defining unit pixels, and extends to the upper portion of the ohmic contact layer 55. 65, a data pad 68 connected to one end of the data line 62 and separated from the source electrode 65 for receiving an image signal from the outside, and the source electrode 65 with respect to the gator electrode 26; And a drain electrode 66 formed over the opposite ohmic contact layer 56.

The passivation layer 70 is formed on the data wires 62, 65, 66, and 68 and the semiconductor layer 40 not covered by the data lines 62. In the passivation layer 70, contact holes 76 and 78 are formed to expose the drain electrode 66 and the data pad 68, respectively. The drain electrode 66 and the data pad exposed through the contact holes 76 and 78 are formed. The plasma reaction layer 630 is formed on the surface 68. A contact hole 74 exposing the gate pad 24 is formed together with the gate insulating layer 30, and a plasma reaction layer 630 is formed on the surface of the gate pad 24 through the contact hole 74.

On the passivation layer 70, the pixel electrode 82 positioned in the pixel while being in electrical contact with the drain electrode 66 by contacting the plasma reaction layer 630 on the surface of the drain electrode upper layer 661 through the contact hole 76, Auxiliary gate pads 86 electrically connected to the pads 24 and 68 in contact with the plasma reaction layer 630 on the surface of the gate pad 24 and the data pad upper layer 681 through the contact holes 74 and 78, respectively. ) And an auxiliary data pad 88, and a transparent conductive film pattern made of ITO or IZO is formed.

Here, the drain electrode 66, the data pad 68, and the gate pad 24 exposed through the contact holes 76, 78, and 74 pass through the low-resistance plasma reaction layer 630 to indium tin oxide (ITO). Alternatively, the contact resistances between the transparent conductive film patterns 82, 86, and 88 of indium zinc oxide (IZO) are reduced.

In this case, as shown in FIGS. 1 and 2A, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate lines 22, 24, and 26. It is also possible to add a storage capacitor wiring.

Meanwhile, as shown in FIG. 2B, a plasma reaction layer 630 may be formed on the entire surface of the data line upper layers 651, 661, and 681 in the thin film transistor substrate.

In the structure according to the exemplary embodiment of the present invention, the gate wiring and the data wiring including the aluminum series having low resistance are used, and thus the present invention can be applied to a large screen high-definition liquid crystal display device. In addition, the plasma reaction layer 630 is formed on the surface of the gate pad 24, the drain electrode 66, and the data pad 68 exposed through the contact hole to form the auxiliary gate pad 86 and the pixel electrode 82 of ITO or IZO. ) And the auxiliary data pad 88 are electrically connected to each other to improve contact characteristics at the pad portion.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having a structure according to a first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2A and 2B and FIGS. 3A to 7B.

First, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIG. 2A will be described with reference to FIGS. 3A to 6B.

First, as shown in FIGS. 3A and 3B, a low-resistance aluminum-based conductive film is laminated and patterned to a thickness of about 2,500 GPa to include a gate line 22, a gate electrode 26, and a gate pad 24. A gate wiring in the horizontal direction is formed.

4A and 4B, the gate insulating film 30, the semiconductor layer 40 made of amorphous silicon, and the upper layer film of the doped amorphous silicon layer 50 are successively laminated and patterned using a mask. The semiconductor layer 40 and the doped amorphous silicon layer 50 are patterned to form the semiconductor layer 40 and the ohmic contact layer 50 on the gate insulating layer 30 facing the gate electrode 24.                     

Next, as shown in FIGS. 5A to 5B, the lower layers 650, 660 and 680 of chromium and the upper layers 651, 661 and 681 are sequentially stacked with Al-Nd and patterned by a photolithography process using a mask. The source electrode 65 intersecting the gate line 22, the source electrode 65 connected to the data line 62, and extending up to the upper portion of the gate electrode 26; A data line including a data pad 68 is formed at one end connected to the drain electrode 66 and the data line 62 facing each other.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer 40 between 55 and 56 is exposed.

Next, as shown in FIGS. 6A and 6B, a protective film 70 made of silicon nitride or an organic insulating film is stacked, and a dry etching chamber together with the gate insulating film 30 in a photolithography process using a mask. Patterning by dry etching at to form contact holes 74, 76, 78 exposing the gate pad 24, the drain electrode 66 and the data pad 68, respectively. Subsequently, the surface of the AlNd 241, 661, and 681 of the gate pad 24, the drain electrode 66, and the data pad 68 exposed through a contact hole by mixing N ₂ gas and Ar gas in a dry etching chamber. The plasma reaction layer 630 is formed. In this case, NH ₃ gas may be used instead of N ₂ gas, and the thickness of the plasma reaction layer 630 may be 50 kPa to 100 kPa.

In addition, another process of forming the plasma reaction layer 630 may include a gate pad 24, a drain electrode 66, and a data pad exposed through contact holes in an ITO or IZO sputter chamber before ITO or IZO deposition. The plasma reaction layer 630 is formed by performing N ₂ plasma treatment on the AlNd 241, 661, 681 surface of the substrate 68. At this time, NH ₃ gas may be used instead of N ₂ gas.

      Next, as shown in FIGS. 1 and 2A, IZO or ITO is laminated and patterned using a mask to contact the plasma reaction layer 630 of the drain electrode upper layer 661 through the contact hole 76. Auxiliary gates connected to the plasma reaction layer 630 formed on the gate pad 24 and the data pad upper layer 681 through the pixel electrodes 82 connected to the drain electrode 66 and the contact holes 74 and 78, respectively. Pads 86 and auxiliary data pads 88 are formed, respectively.

      Meanwhile, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIG. 2B will be described with reference to FIGS. 7A and 7B.

As shown in FIG. 7A, data wirings 62, 65, 66, and 68 formed of a lower layer 610 of chromium and an upper layer 620 of AlNd on the formed semiconductor layer 40 and the ohmic contact layer 50. ) Is sequentially stacked and N ₂ gas is mixed with Ar gas in the stacking chamber to form a plasma reaction layer 630 on the AlNd surface.

      Subsequently, as shown in FIG. 7B, the doped amorphous silicon layer pattern 50 that is not covered by the data lines 62, 65, 66, and 68 is etched by a photolithography process using a mask, and then etched to both sides of the gate electrode 26. The semiconductor layer pattern 40 between the doped amorphous silicon layers 55 and 56 is exposed.

In the manufacturing method according to this embodiment of the invention by N ₂ plasma to AlNd in order to improve the contact characteristics between the ITO or IZO and AlNd it had a plasma reaction layer 630, an N ₂ plasma to AlNd in several process steps It can be processed to reduce the number of process steps.

      In the first embodiment, as described above, the present invention can be applied to a manufacturing method using five masks, but can also be applied to a manufacturing method of a thin film transistor substrate for liquid crystal display devices using four masks. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to an embodiment of the present invention will be described in detail with reference to FIGS. 8 to 9B.

FIG. 8 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 9A and 9B illustrate a thin film transistor substrate shown in FIG. 8, respectively. A cross-sectional view taken along the line.

First, a gate wiring including a gate line 22, a gate electrode 26, and a gate pad 24 made of aluminum (Al) or an aluminum alloy (Al alloy) on the insulating substrate 10 in the same manner as in the first embodiment. Is formed. In addition, the gate wiring includes a storage electrode 28 formed on the insulating substrate 10 in parallel with the gate line 22 and having the same structure as the gate wiring that receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. Include. The sustain electrode 28 overlaps the conductor pattern 64 for the sustain capacitor connected to the pixel electrode 82 to be described later to form a sustain capacitor which improves the charge retention capability of the pixel, and the pixel electrode 82 and the gate line to be described later. If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

In this case, the gate wirings 22, 24, 26 and the storage electrode 28 are preferably formed of a single aluminum-based film, but are made of chromium (Cr) or molybdenum (Mo), which are excellent in contact properties with other materials. It may be formed of a double layer including a lower layer made of a top layer made of an aluminum-based conductive material having a low resistance, such as Al-Nd.

A gate insulating film 30 made of silicon nitride (SiNx) is formed on the gate wirings 22, 24, and 26 and the storage electrode 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and silicon doped with n-type impurities such as phosphorus (P) on the semiconductor pattern at high concentration. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 is formed.

On the resistive contact layer patterns 55, 56, and 58, the lower layers 620, 640, 650, 660, and 680 made of chromium (Cr) or molybdenum (Mo) and the like are made of an aluminum-based conductive material such as Al-Nd. Data wirings are formed on the upper films 621, 641, 651, 661, and 681. The data line is connected to the data line 62 formed in the vertical direction, the source electrode 65 of the thin film transistor which is a branch of the data line, the gate electrode 26 or the channel portion C of the thin film transistor. A data pad 68 connected to one end of the drain electrode 66 and the data line 62 of the thin film transistor positioned on the opposite side to apply an image signal from the outside, and a conductor for a storage capacitor on the sustain electrode 28. The pattern 64 is also included. When the sustain electrode 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. Have exactly the same shape. That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 65 and 68, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.

      The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the source electrode 65 in the channel portion C of the thin film transistor. ) And the drain electrode 66 are separated, and the data line intermediate layer 55 and the contact layer pattern 56 for the drain electrode are also separated, but the semiconductor pattern 42 of the thin film transistor is continuously connected here. Create a channel.

      A protective film 70 made of an organic insulating material such as silicon nitride or acrylic is formed on the data wires 62, 64, 65, 66, and 68. The protective film 70 is a data pad 68 and a conductor for a storage capacitor. It has contact holes 73, 74, and 76 that expose the upper layers 681, 641, and 661 of the pattern 64 and the drain electrode 66, respectively, and exposes the gate pad 24 together with the gate insulating film 30. It has a contact hole 72.

      Here, plasma reaction is performed on the AlNd surfaces of the data pads 68 exposed through the contact holes 73, 74, 76, and 72, the conductive capacitor pattern 64 for the storage capacitor, the drain electrode 66, and the gate pad 24. Layer 630 is formed.

      On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 82 is in contact with the plasma reaction layer 630 through the contact hole 76 and electrically connected to the drain electrode 66. Connected to receive an image signal. In addition, the pixel electrode 82 contacts the plasma reaction layer 630 of the conductive pattern upper layer 640 for the storage capacitor through the contact hole 74, and is also connected to the conductive pattern 64 to transmit an image signal. The auxiliary gate pad 84 and the auxiliary data pad electrically connected to the gate pad 24 and the data pad 68 on which the plasma reaction layer 630 is exposed through the contact holes 72 and 74 are formed. 86) are formed, and these are not essential to serve to protect the pads and to protect the pads 24 and 68 from the external circuit device, and their application is optional.

      Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 8 to 9B using four masks will be described in detail with reference to FIGS. 8 to 9A and 10A to 16C. do.

      First, as shown in FIGS. 10A to 10C, as in the first embodiment, the gate line 22 is formed on the insulating substrate 10 by a photolithography process using a first mask by laminating an aluminum-based conductive film having a low resistance. A gate wiring including the gate pad 24, the gate electrode 26, and the sustain electrode 28 is formed.

      Next, as shown in FIGS. 11A and 11B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 mV to 5,000 mV, 500 mV to 2,000 mV, 300 mV using chemical vapor deposition. After the continuous deposition to a thickness of 600 kPa, the conductor layer 60 composed of the lower film 600 of chromium and the upper film 601 of Al-Nd is sequentially deposited to about 1,500 kPa to 3,000 kPa by sputtering or the like. do.

       Next, the photosensitive film 110 is applied thereon to a thickness of 1 μm to 2 μm. Thereafter, when the photoresist film 110 is irradiated with light through the second mask and developed, the photoresist patterns 112 and 114 are formed as shown in FIGS. 12B and 12C. At this time, among the photoresist patterns 112 and 114, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, which is the channel portion C of the thin film transistor, is the data wiring portion A, that is, the data wiring. The thickness of the second portion 112 is smaller than that of the second portion 112 positioned at the portion where the 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in an etching process which will be described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, 4,000 Pa or less.

       As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

       At this time, the width of the slit is preferably smaller than the resolution of the exposure machine used during exposure, in the case of using a semi-transparent film may use a thin film having a different transmittance or a different thickness in order to control the transmittance when manufacturing a mask.

       When the light is irradiated to the photosensitive film through the mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. When the next photoresist film is developed, only the portion where the polymer molecules are not decomposed is left, and a thinner photoresist film is left at the center portion where the light is not irradiated. In this case, if the exposure time is extended, all molecules are decomposed, and this should be avoided.

      The thin photoresist film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot completely transmit light, and then develops and ripples. It can also be formed by making a part of the photosensitive film flow to the part in which the photosensitive film does not remain.

      Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

       First, as shown in FIGS. 13A and 13B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, since only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not easily found, the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than in the case of wet etching, and the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

In the case where the conductor layer 60 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, any of dry etching and wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW alloy, a mixed gas or CF of CF ₄ and HCl may be used as an etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this case, as shown in Figs. 13A and 13B, only the source / drain conductor pattern 67 and the storage capacitor conductor pattern 64 remain, and the conductor layer of the other portion B is removed so that the intermediate layer thereunder is removed. 50 is revealed. In this case, the remaining conductor patterns 64 and 67 are the same as those of the data lines 62, 64, 65, 66, and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. .

Next, as shown in FIGS. 14A and 14B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 thereunder are simultaneously removed by the dry etching method together with the first portion 114 of the photosensitive film. do. In this case, the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 are simultaneously etched, and the gate insulating layer 30 should be performed under an unetched condition. In particular, the photoresist patterns 112 and 114 and the semiconductor layer 40 must be etched. It is desirable to etch under conditions where the etch ratio to layer 40 is approximately equal. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

      This removes the first portion 114 of the channel portion 114 to reveal the source / drain conductor patterns, as shown in FIGS. 14A and 14B, and the intermediate layer 50 and the semiconductor layer of the other portion B. 40 is removed to expose the gate insulating film 30 below. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. At this stage, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductor patterns 64, respectively.

        Subsequently, ashing removes the photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as illustrated in FIGS. 15A and 15B, the source / drain conductor pattern 67 of the channel portion C and the source / drain intermediate layer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57, and the source / drain intermediate layer pattern 57 may be wet-etched, and the intermediate layer pattern 57 may be formed. It may also be performed by dry etching. In the case of dry etching only, it is preferable to perform etching under the condition that the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in the portion (C). For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the case of the wet etching and the dry etching alternately, the side surface of the wet patterned source / drain conductor pattern 67 is etched, but the dry layered intermediate layer pattern 57 is hardly etched and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 14B, a part of the semiconductor pattern 42 may be removed to reduce the thickness, and the second part 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching should be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

     In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

       Finally, the second photosensitive layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

After forming the data lines 62, 64, 65, 66, and 68 in this manner, as shown in FIGS. 16A to 16C, silicon nitride is deposited by chemical vapor deposition or spin-coated an organic insulating material to obtain a thickness of 3,000 kPa or more. The branches form a protective film 70. Subsequently, the protective layer 70 is etched together with the gate insulating layer 30 in the dry etching chamber by using the third mask to form the gate pad 24, the data pad 64, the drain electrode 66, and the conductive capacitor pattern. Expose 68 to form contact holes 72, 73, 74, and 76. The gate pad 24, the data pad 64, and the drain electrode 66 exposed through the contact holes 72, 73, 74, and 76 by mixing N ₂ gas or Ar gas with NH ₃ in a dry etching chamber to form a plasma. And a plasma reaction layer 630 having a thickness of 50 kPa to 100 kPa on the AlNd surface, which is the upper films 241, 641, 661, and 681 of the conductive capacitor pattern 68 for the storage capacitor.

       In addition, in the ITO or IZO sputter chamber before the deposition of ITO or IZO, the plasma reaction layer 630 may be formed on the AlNd surface exposed through the contact holes 72, 73, 74, and 76 by the above-described plasma surface treatment method. Can be.

Meanwhile, as in the first embodiment, after the data wires are stacked, the plasma reaction layer 630 is formed by treating N ₂ plasma on the AlNd surface, which is the upper layer of the data wires 62, 64, 65, 66, and 68, in the stacking chamber. Can be formed.

       Finally, the IZO layer having a thickness of 400 kV to 500 kV is deposited and etched using a fourth mask to contact the plasma reaction layer 630 and the pixel electrode 82 connected to the drain electrode 60 and the conductive pattern 64 for the storage capacitor. ), An auxiliary gate pad 84 connected to the gate pad 24, and an auxiliary data pad 88 connected to the data pad 68 are formed. In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48) may be formed using one mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.

As described above, according to the present invention, a plasma reaction layer is formed on the surface of the drain electrode, the data pad, and the gate pad exposed through the contact hole by plasma treatment of N ₂ or NH ₃ to form a plasma reaction layer. The contact characteristics can be improved, and the plasma reaction layer can be formed by treating the plasma in several process steps, thereby reducing the number of process steps. Also, since the process is performed in the same chamber, the effect caused by moving the chamber during the process can be reduced. Yield is improved.

Claims (11)

Forming a gate wiring including a gate line and a gate electrode on the insulating substrate, the first conductive film having an aluminum base; Forming a data line insulated from the gate line and including a data line, a source electrode, and a drain electrode including a second conductive layer of chromium or molybdenum and a third conductive layer of aluminum series; Stacking and patterning a passivation layer covering the gate line and the data line to form a contact hole exposing the gate line or the data line; Mixing an argon gas with nitrogen gas or ammonia gas on the surface of the gate wiring exposed by the contact hole or the first or third conductive film of the data wiring to form a plasma reaction layer, Forming a transparent conductive layer pattern connected to the gate line or the data line through the contact hole Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a.        In claim 1,         The transparent conductive film pattern is formed of ITO or IZO manufacturing method of a thin film transistor substrate for a liquid crystal display device.        In claim 1,       The gate line further includes a gate pad connected to the gate line, and the data line further includes a data pad connected to the data line.       The contact hole includes first, second and third contact holes exposing the drain electrode, the data pad and the gate pad, respectively, The transparent conductive layer pattern may include a pixel electrode connected to the drain electrode through the first contact hole, and an auxiliary data pad and an auxiliary gate pad connected to the data pad and the gate pad through the second and third contact holes, respectively. The manufacturing method of the thin film transistor substrate for liquid crystal display devices containing. In claim 1, And forming the plasma reaction layer after the protective layer is etched. In claim 1, The plasma reaction layer forming step is a method for manufacturing a thin film transistor substrate for a liquid crystal display device performed in the sputter chamber before ITO or IZO lamination. In claim 1, And the plasma reaction layer forming step is performed after stacking data lines. delete A gate wiring formed on an insulating substrate and including a gate line, a gate electrode, and a gate pad, A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film, A data line formed on the gate insulating layer or the semiconductor layer and including a data line, a source electrode, a drain electrode, and a data pad, the data line including a lower conductive layer of chromium or molybdenum and an upper conductive layer of aluminum series; A protective film covering the semiconductor layer, A plasma reaction layer formed on a surface of an upper conductive film of the gate wiring or the data wiring; A transparent conductive film pattern electrically connected to the gate line or the data line via the plasma reaction layer Thin film transistor substrate for a liquid crystal display device comprising a.         In claim 8,        The gate line is a thin film transistor substrate for a liquid crystal display device including an aluminum-based metal.         In claim 8,         The transparent conductive film pattern is a thin film transistor substrate for a liquid crystal display device made of ITO or IZO.         In claim 8,         The passivation layer has first, second, and third contact holes through which the drain electrode, the data pad, and the gate pad are exposed, respectively.         The transparent conductive layer pattern may include a pixel electrode connected to the drain electrode through the first contact hole on the passivation layer, and an auxiliary data pad connected to the data pad and the gate pad through the second and third contact holes, respectively. And an auxiliary gate pad.

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