KR100749265B1 - Image sensor - Google Patents

Abstract

The present invention is to provide an image sensor that can improve the image quality of the image sensor by preventing the crack (Crack) generated in the LTO during the wafer back surface polishing or wafer cutting, the present invention for this purpose The scribe lines arranged in a matrix form for cutting, the pixel array formed between the scribe lines, and the cracks generated when cutting the scribe lines are spaced apart from each other at regular intervals to prevent the cracks from being transferred to the pixel array. An image sensor including a dummy pattern array including a plurality of dummy patterns formed between the scribe line and the pixel array is provided so that cracks generated during cutting of the scribe line do not affect actual microlenses formed in the pixel array. Could The.

 Image sensors, scribe lines, pixel arrays, microlenses, dummy patterns.

Description

Image sensor {IMAGE SENSOR}

1 is a circuit diagram showing a unit pixel of a general CMOS image sensor.

FIG. 2 is a cross-sectional view illustrating a cross-sectional structure of a CMOS image sensor including a unit pixel, a color filter, and a microlens shown in FIG. 1.

3 is a plan view illustrating a CMOS image sensor formed in a wafer according to an embodiment of the present invention.

4 is an enlarged plan view of a portion 'A' shown in FIG. 3;

FIG. 5 is an enlarged plan view of a part of the dummy pattern array unit DPA in FIG. 4.

FIG. 6 is a plan view illustrating the entire dummy pattern array unit DPA shown in FIG. 4.

FIG. 7 is an enlarged plan view illustrating a TL (Top-Left) part shown in FIG. 6;

FIG. 8 is an enlarged plan view of a portion 'A' shown in FIG. 7; FIG.

FIG. 9 is an enlarged plan view illustrating a top-right portion shown in FIG. 6; FIG.

FIG. 10 is an enlarged plan view of a portion 'A' shown in FIG. 9; FIG.

FIG. 11 is an enlarged plan view of a bottom-right portion shown in FIG. 6; FIG.

12 is an enlarged plan view of a portion 'A' shown in FIG. 11;

FIG. 13 is an enlarged plan view illustrating a Bottom-Left (BL) portion illustrated in FIG. 6.

14 is an enlarged plan view of a portion 'A' shown in FIG. 13.

<Description of the symbols for the main parts of the drawings>

DP: dummy pattern

PA: pixel array

SL: scribe line

OCL: Overcoat Layer

GD: Green Pile

SP: Spacer

100, DM1, DM2: dummy pattern

C: crack

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to an image sensor for preventing a low temperature oxide (LTO) crack for protecting a micro lens.

Recently, the demand for digital cameras is exploding with the development of video communication using the Internet. Moreover, the demand for small camera modules increases as the popularity of mobile communication terminals such as PDAs equipped with cameras, International Mobile Telecommunications-2000 (IMT-2000), Code Division Multiple Access (CDMA) terminals, etc. increases. Doing.

The camera module basically includes an image sensor. In general, an image sensor refers to a device that converts an optical image into an electrical signal. As such an image sensor, a charge coupled device (hereinafter referred to as a CCD) and a CMOS (Complementary Metal-Oxide-Semiconductor) image sensor are widely used.

CCD has a complicated driving method, high power consumption, complicated process due to the large number of mask processes in the manufacturing process, and it is difficult to realize a signal processing circuit in a chip, making it difficult to make one chip. There are disadvantages. In contrast, CMOS image sensors are receiving more attention recently because of the monolithic integration of control, drive, and signal processing circuitry on a single chip. In addition, CMOS image sensors offer potentially lower cost than conventional CCDs due to low voltage operation and low power consumption, compatibility with peripherals, and the availability of standard CMOS fabrication processes.

In general, the CMOS image sensor is composed of a light sensing unit for detecting light and a logic circuit unit for processing the light detected by the light sensing unit into an electrical signal and converting the data into light. Efforts are underway to increase the fill fraction. However, there is a limit to this effort under a limited area since the logic circuit part cannot be removed essentially. Accordingly, in order to increase the light sensitivity, a condensing technology that changes the path of light incident to an area other than the light sensing unit and collects the light sensing unit has emerged. For this purpose, an image sensor forms a microlens on a color filter. I'm using the method.

FIG. 1 is a circuit diagram showing a unit pixel of a general CMOS image sensor having four transistors and two capacitors. A CMOS image sensor including a photodiode (PD) as a light sensing means and four NMOS transistors is shown. Showing unit pixels.

Referring to FIG. 1, a transfer transistor Tx of four NMOS transistors transmits a signal for transferring photocharges generated in the photodiode PD to the floating diffusion region FD, and the reset transistor Rx is floating diffusion. A signal for resetting the region FD to the supply voltage VDD level is transmitted, the drive transistor Dx serves as a source follower, and the select transistor Sx performs pixel data enable. It receives a signal and transmits a pixel data signal to an output.

Operation of the unit pixel of the image sensor configured as described above is performed as follows.

First, the reset pixel Rx, the transfer transistor Tx, and the select transistor Sx are turned on to reset the unit pixel. At this time, the photodiode PD begins to deplete, and carrier charging occurs, and in the floating diffusion region FD, charge is accumulated up to the supply voltage VDD. Then, the transfer transistor Tx is turned off, the select transistor Sx is turned on, and the reset transistor Rx is turned off. In such an operation state, the output voltage V1 is read from the unit pixel output terminal Vout, stored in the buffer, and the transfer transistor Tx is turned on to float the charges of the photodiode PD changed according to the light intensity. After transferring to the diffusion region FD, the output voltage V2 is read again from the output terminal Out, and the analog data of the difference values V1 -V2 are converted into digital data, thereby completing the operation cycle for the unit pixel. do.

2 is a cross-sectional view illustrating a CMOS image sensor according to the related art illustrated in FIG. 1.

As shown in FIG. 2, the conventional CMOS image sensor includes a unit pixel 14, a plurality of metal wires M1, M2, and M3, and a plurality of interlayer insulating layers 17, 19, and 21 for insulation therebetween. And a passivation layer 23 formed to cover the final metal wiring M3, a plurality of color filters 24 formed on the passivation layer 23 corresponding to the unit pixel array 14, and a color filter. A flattening film 25 formed to cover the 24, such as an over coating layer (OCL), a microlens 26 formed on the flattening film 25 so as to correspond to the color filter 24, and a microlens 26. It is made of LTO (Low Temperature Oxide, 27) formed to cover.

Among these components, the LTO 27, which is a low temperature oxide film, is mainly formed to cover the microlens 26 in the unit pixel array unit where the unit pixels 14 are formed. Forming a Pad In the pad open portion, it is formed directly on the passivation film 23.

As a result, foreign matter penetrates between the passivation layer 23 and the LTO 27 during the photoresist pattern strip process used as an etching mask for forming the pad opening, thereby causing the LTO 27 to float around the pad. Done. In this state, when the wafer back grinding or wafer sawing process is performed, an LTO crack is generated in which the LTO 27 is pulled out by the physical force applied at this time.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, an image sensor that can improve the image quality of the image sensor by preventing cracks in the LTO during polishing the wafer backside or cutting the wafer. The purpose is to provide.

According to an aspect of the present invention, a scribe line arranged in a matrix form for cutting the wafer on a wafer, a pixel array formed between the scribe lines, and a scribe line generated during cutting of the scribe line In order to prevent cracks from being transferred to the pixel array, the scribe line and the pixel array are arranged to be spaced apart from each other at regular intervals so as to overlap each other, and are formed on the left side, the right side, the upper side, and the lower side. The micro pattern in the pixel array such that the dummy pattern and the second dummy pattern formed at the left side and the upper side, the left side and the lower side, the right side and the upper side, and the right side and the bottom side are in contact with each other and the pixel array have different sizes. Image containing dummy pattern array formed simultaneously with lens Provide documentation.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

3 is a plan view illustrating an image sensor formed in a wafer in order to describe an image sensor according to an exemplary embodiment of the present invention, and FIG. 4 is an enlarged plan view of a portion 'A' illustrated in FIG. 3.

3 and 4, an image sensor according to an embodiment of the present invention includes a scribe line SL and a scribe line SL arranged in a matrix form for cutting a wafer on a wafer. Pixel arrays (PA) formed in the center portion between the scribe line (SL) and the scribe line (SL) and spaced apart from each other at regular intervals to prevent the cracks generated when cutting the scribe line (SL) and the pixel array (PA) A plurality of dummy pattern arrays (DPAs) formed between the pixel arrays PA are included.

The dummy pattern array DPA has a structure in which a plurality of dummy patterns 100 are partially overlapped with each other in the direction of the pixel array PA in the scribe line SL so as to surround the pixel array PA.

The dummy pattern 100 is a microlens dummy pattern formed at the same time as the microlens to be formed in the pixel array PA, and is disposed to be spaced apart from each other at a predetermined interval S. For example, the spacing S between them should be at least 0.3 μm or more. The reason for this is to prevent a short circuit between the dummy patterns 100, because when a short circuit occurs between the dummy patterns 100, the micro vibration transmitted from the scribe line SL cannot be blocked.

In addition, the dummy pattern 100 is formed to have a width CD smaller than the width of the actual micro lens formed in the pixel array PA. For example, the dummy pattern 100 is formed to have a width of 0.3 μm to 0.5 μm smaller than the actual micro lens width formed in the pixel array PA. Preferably, the width CD of the dummy pattern 100 has a value of 0.4 μm smaller than the actual microlens width formed in the pixel array PA. This is because the critical dimension of the width of the microlens formed in the pixel array PA tends to increase, which may cause a short circuit between the dummy patterns 100.

Accordingly, when the width of the microlens used to form the actual microlens in the pixel array PA is 2.8 μm and the distance between the lenses is 0.4 μm with the mask, the width CD of the dummy pattern 100 is It is set to 2.4 micrometer and the space | interval S between dummy patterns is set to 0.8 micrometer.

The dummy pattern array DPA is disposed to be spaced apart from the pixel array PA at a predetermined interval SP. At this time, it is preferable that the space | interval SP, ie, D1, becomes at least 10 micrometers or more.

As such, according to the exemplary embodiment of the present invention, the plurality of dummy patterns 100 arranged in the multilayer structure in the scribe line SL direction to the pixel array PA are disposed between the scribe line SL and the pixel array PA. , LTO crack can be prevented when cutting the scribe line (SL).

On the other hand, the image sensor according to an embodiment of the present invention may further include a planarization film, that is, an overcoating layer (OCL) and a green dummy pattern (GD) formed before forming the micro lens. In this case, the green dummy pattern GD is formed to overlap the pixel array PA and the dummy pattern array DPA, but is wider than the dummy pattern array DPA. For example, it is formed to extend from 5 to 10 μm (D ₂ ) in the scribe line SL direction from the outside of the dummy pattern DPA. In addition, the overcoating layer OCL is formed to overlap all of the pixel array PA, the dummy pattern array DPA, and the green dummy pattern GD, and is wider than the green dummy pattern GD.

On the other hand, in the image sensor according to the embodiment of the present invention, the dummy pattern 100 is disposed so that a predetermined portion overlaps each other in the array (M). That is, odd and even numbers are arranged in a zigzag form. The dummy patterns 100 disposed on the same plane to overlap each other, and the odd and even numbers are arranged to overlap each other.

The reason for arranging the dummy patterns 100 in a zigzag form is to block the generation of crack paths between the dummy patterns 100 when the dummy patterns 100 are arranged side by side.

FIG. 5 is an enlarged view of a portion of the dummy pattern array PDA illustrated in FIG. 4, and FIG. 6 illustrates a state in which the dummy pattern array PDA illustrated in FIG. 4 is disposed in the same shape on the top, bottom, left, and right sides. Figure is shown.

FIG. 7 is a plan view of a dummy pattern of TL (Top-Left) in FIG. 6, in which sizes of dummy patterns are formed differently, and FIG. 8 is an enlarged plan view of part 'A' shown in FIG. 7. to be. As shown in FIG. 7 and FIG. 8, in FIG. 6, dummy patterns disposed in TL portions of the dummy pattern array PA are formed to have different sizes. That is, the second dummy pattern DM2 is formed larger than the first dummy pattern DM1. At this time, the first dummy pattern DM1 has an area of 2.4 μm × 2.4 μm, while the second dummy pattern DM2 has an area of 2.4 μm × 4 μm.

FIG. 9 is a layout view of a dummy pattern of top-right (TR) in FIG. 6, and FIG. 10 is an enlarged plan view of a portion 'A' illustrated in FIG. 9. As shown in FIGS. 9 and 10, the gap S between the dummy pattern array DPA disposed on the right side of the pixel array PA and the spacing part SP is about 2.4 μm. To be

In addition, FIG. 11 is a layout view of a dummy pattern of BR (bottom-right) in FIG. 6, wherein the dummy patterns are formed in different sizes, and FIG. 12 is an enlarged plan view of a portion 'A' shown in FIG. 11. to be. As shown in FIGS. 11 and 12, in FIG. 6, dummy patterns disposed in BR portions of the dummy pattern array PA are formed to have different sizes. That is, the second dummy pattern DM2 is formed larger than the first dummy pattern DM1. At this time, the first dummy pattern DM1 has an area of 2.4 μm × 2.4 μm, while the second dummy pattern DM2 has an area of 2.4 μm × 4 μm.

 FIG. 13 is a layout view of a dummy pattern of BL (bottom-left) in FIG. 6, wherein the dummy patterns are formed in different sizes, and FIG. 14 is an enlarged plan view of a portion 'A' shown in FIG. 13. to be. As shown in FIG. 13 and FIG. 14, in FIG. 6, dummy patterns disposed in the BL portion of the dummy pattern array PA are formed to have different sizes. That is, the second dummy pattern DM2 is formed larger than the first dummy pattern DM1. At this time, the first dummy pattern DM1 is formed to have a size of 2.4 μm × 2.4 μm, whereas the second dummy pattern DM2 is formed to have a size of 2.4 μm × 4 μm.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a plurality of microlens dummy patterns arranged in a multilayer structure in the direction of the scribe line in the pixel array is disposed between the scribe line and the pixel array so that LTO cracks generated during cutting of the scribe line become pixels. It is possible to avoid affecting the actual microlenses formed in the array.

In addition, according to the present invention, a plurality of microlens dummy patterns arranged in a multilayer structure in a scribe line in a pixel array direction are disposed between the scribe line and the pixel array, and even-numbered microlens dummy patterns are arranged in odd numbers. By arranging to overlap with the region between the microlens dummy patterns, it is possible to prevent the LTO crack generated during scribe cutting from being transferred along the region between the microlens dummy patterns.

Therefore, it is possible to reliably solve the problem that the LTO cracks generated from the scribe line during wafer cutting are transferred to the pixel array to degrade the image quality of the image sensor.

Claims (11)

Scribe lines arranged in a matrix to cut the wafer onto the wafer; A pixel array including a plurality of micro lenses formed between the scribe lines; And In order to prevent cracks generated during cutting of the scribe line from being transferred to the pixel array, the scribe line and the pixel array are disposed to be spaced apart from each other at regular intervals so as to overlap each other. The first dummy pattern formed on the lower side and the second dummy pattern formed on the left side and the upper side, the left side and the lower side, the right side and the upper side, and the right side and the lower side are in contact with each other surround the pixel array with different sizes. A dummy pattern array simultaneously formed with the microlenses in the pixel array Image sensor comprising a. delete delete delete delete The method of claim 1, The first dummy pattern has an image sensor having a size of 2.4 μm × 2.4 μm. delete delete delete delete delete

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