CN101236978B

CN101236978B - Photosensitive chip packaging structure and manufacturing method thereof

Info

Publication number: CN101236978B
Application number: CN2007100079812A
Authority: CN
Inventors: 刘建宏
Original assignee: XinTec Inc
Current assignee: XinTec Inc
Priority date: 2007-02-01
Filing date: 2007-02-01
Publication date: 2011-05-18
Anticipated expiration: 2027-02-01
Also published as: CN101236978A

Abstract

The invention provides a photosensitive chip package structure and a manufacturing method thereof, wherein a photosensitive chip is constructed on one side of a wafer by utilizing a bonding layer, a color filter array is arranged above the photosensitive chip, a glass substrate with a weir wall is constructed, the glass substrate covers the color filter array, a proper gap is formed between the glass substrate and the color filter array, and the light penetration rate can be increased by directly receiving light by the photosensitive chip constructed above the wafer.

Description

Sensitized chip encapsulation structure and manufacture method thereof

Technical field

The present invention relates to a kind of sensitized chip encapsulation structure and manufacture method thereof, relate in particular to a kind of light penetration rate that increases, to improve the sensitized chip encapsulation structure and the manufacture method thereof of resolution.

Background technology

Along with prevailing of audio-visual multimedia, digital image device releases one after another, and the status of its key core part diagram image-position sensor also becomes more and more important.Imageing sensor mainly is responsible for converting the picture signal of light to the signal of telecommunication, and can be divided into charge coupled cell (Charge Coupled Device usually according to the type of sensing element, be called for short CCD) imageing sensor and CMOS (Complementary Metal Oxide Semiconductor) (Complementary Metal Oxide Semiconductor is called for short CMOS) imageing sensor etc.Wherein, because complement metal oxide semiconductor image sensor has low price, low power consumption, pixel can read at random and advantage such as high degree of integration, therefore be used at present shooting mobile phone and network camera (webcam) etc. comparatively in the product of par more.

And Figure 13 is the generalized section of known image transducer, the sensitive chip 81 of this imageing sensor 80 is configured in the substrate 82, and wherein sensitive chip 81 is made of a plurality of optical diodes (photo diode) with p-n junction (p-n junction) in the substrate 82.In more detail, sensitive chip 81 normally is made of the p-n junction that forms naturally between n type doped region, p type doped region and n type doped region in the substrate 82 and the p type doped region.

Internal connecting layer (interconnection layer) 84 is configured in the substrate 82, and wherein include many metal interconnectings and the dielectric layer between these metal interconnectings (not indicating among the figure), these metal interconnectings are suitable for sensitive chip 81 received signals are transferred to circuit board 85, to carry out subsequent image processing.And colored filter 86 is configured on the internal connecting layer 84 in the arrayed mode, and correspond to sensitive chip 81 in the substrate 82, and each colored filter 86 top all is coated with the lenticule 87 in order to collected light, the top of lenticule 87 then disposes glass substrate 88, and is connected with internal connecting layer 84 by supporter 89.

Extraneous light 91 is incident in the internal connecting layer 84 via lenticule 87 and colored filter 86, and then is received by sensitive chip 81.Therefore, the layout of the metal interconnecting in the internal connecting layer 84 must be avoided the top of sensitive chip 81, reduce sensitive chip 81 light intensity that sensed to avoid metal level (not indicating among the figure) reflection ray, so comparatively numerous and diverse on the technology as metal interconnecting.

In addition, the incident ray (also promptly absorbing or reflection ray) that the dielectric layer in the internal connecting layer 84 (among the figure indicate) also can stop portions, and make light intensity decay gradually in internal connecting layer 84, and then cause the sensitive chip 81 light intensity deficiency that senses.

Summary of the invention

In view of this, main purpose of the present invention is promptly providing a kind of light penetration rate that increases, to improve the sensitized chip encapsulation structure and the manufacture method thereof of resolution.

For achieving the above object, technical scheme of the present invention is:

A kind of sensitized chip encapsulation structure, it includes at least: wafer, be provided with first and second surface, its first surface combines with a sensitive chip by being provided with knitting layer; This sensitive chip is arranged on the first surface of wafer by knitting layer, and this sensitive chip top is provided with colour filter array; Glass substrate, its glass substrate one side is provided with a plurality of weirs wall, and be arranged at by this weir wall above the interval of this sensitive chip, and make glass substrate and colour filter array form appropriate gap, wherein do not contain metal interconnecting and the dielectric layer between metal interconnecting between this sensitive chip and this glass substrate.

According to sensitized chip encapsulation structure of the present invention, wherein this wafer second surface construction in regular turn has substrate, first insulating barrier, has the conductive layer that is connected with external circuit with sensitive chip and wafer, and second insulating barrier of outermost and circuit pin, each circuit pin passes second insulating barrier and contacts with conductive layer.

According to sensitized chip encapsulation structure of the present invention, wherein this colour filter array utilizes knitting layer to be arranged at each sensitive chip top respectively.

According to sensitized chip encapsulation structure of the present invention, wherein this weir wall is a photoresist.

According to sensitized chip encapsulation structure of the present invention, wherein this photoresist is anti-welding green lacquer.

The present invention also provides a kind of manufacture method of photosensitizing type Chip Packaging, and this method comprises the following steps: in wafer one side knitting layer to be set, and construction has a plurality of sensitive chips on knitting layer; Colour filter array is set on sensitive chip; The glass substrate that is provided with the weir wall is provided; This glass substrate is covered in the colour filter array top, and utilize the weir wall to make glass substrate and colour filter array form appropriate gap, wherein do not contain metal interconnecting layer and the dielectric layer between the metal interconnecting layer between this sensitive chip and this glass substrate; Be provided with at this wafer on the opposite side of this sensitive chip substrate, construction first insulating barrier be set in regular turn, carry out one for the first time cutting step with the conductive layer, construction second insulating barrier that differ from substrate that this first insulating barrier place forms one first road chase, construction has and be electrically connected with external circuit with sensitive chip and wafer and the circuit pin is set; And carry out the second time cutting step so that respectively this sensitive chip separate.

According to the manufacture method of photosensitizing type Chip Packaging of the present invention, wherein in steps d, also be included in before construction first insulating barrier, carry out substrate adhesion step.

According to the manufacture method of photosensitizing type Chip Packaging of the present invention, wherein this substrate adhesion step side in addition of corresponding to sensitive chip in wafer is by the knitting layer substrate of adhering.

According to the manufacture method of photosensitizing type Chip Packaging of the present invention, wherein this first insulating barrier construction step is coated with insulating material on substrate, utilizes the exposure imaging mode to form first insulating barrier at the ad-hoc location of substrate again.

According to the manufacture method of photosensitizing type Chip Packaging of the present invention, wherein the degree of depth of this one chase is thought and is touched the weir wall.

According to the manufacture method of photosensitizing type Chip Packaging of the present invention, wherein this weir wall is a photoresist.

According to the manufacture method of photosensitizing type Chip Packaging of the present invention, wherein this photoresist is anti-welding green lacquer.

During enforcement, this wafer one side utilizes the knitting layer construction that sensitive chip is arranged, this sensitive chip top then is provided with colour filter array, other has a glass substrate that is provided with the weir wall, and this glass substrate is covered in the colour filter array top, utilize glass substrate and colour filter array to form appropriate gap simultaneously, directly receive light, can increase the penetrance of light by the sensitive chip that is built in the wafer top.

Description of drawings

Fig. 1 is sensitized chip encapsulation structure structure cutaway view among the present invention.

Fig. 2 is provided with the procedure of processing schematic diagram of sensitive chip for wafer among the present invention.

Fig. 3 is provided with the procedure of processing schematic diagram of colour filter array for sensitive chip among the present invention.

Fig. 4 is the structural representation of glass substrate among the present invention.

Fig. 5 is covered in the procedure of processing schematic diagram of colour filter array for glass substrate among the present invention.

Fig. 6 is substrate adhesion procedure of processing schematic diagram among the present invention.

Fig. 7 (A), Fig. 7 (B) are the first insulating barrier construction procedure of processing schematic diagram among the present invention.

Fig. 8 is cutting processing step schematic diagram for the first time among the present invention.

Fig. 9 is conductive layer procedure of processing schematic diagram among the present invention.

Figure 10 (A), Figure 10 (B) are the second insulating barrier procedure of processing schematic diagram among the present invention.

Figure 11 is provided with circuit pin procedure of processing schematic diagram among the present invention.

Figure 12 is cutting processing step schematic diagram for the second time among the present invention.

Figure 13 is the generalized section of known image transducer.

Wherein, description of reference numerals is as follows:

10---sensitized chip encapsulation structure

1---wafer

11---first surface

12---second surface

2---knitting layer

3---sensitive chip

31---at interval

4---colour filter array

5---glass substrate

51---the weir wall

61---substrate

62---first insulating barrier

621-insulating material

63---conductive layer

64---second insulating barrier

641-passage

65---the circuit pin

71---the first road chase

72---the second road chase

80---imageing sensor

81---sensitive chip

82-substrate

84---internal connecting layer

85---circuit board

86---colored filter

87---lenticule

88---glass substrate

89---supporter

91---extraneous light

Embodiment

Characteristics of the present invention can be consulted the detailed description of illustrations and embodiment and obtained to be well understood to.

The present invention's " sensitized chip encapsulation structure and manufacture method thereof ", the basic structure of this sensitized chip encapsulation structure 10 is formed as shown in Figure 1, and it includes at least:

Wafer 1 is provided with first and

second surface

11,12, and its first surface 11 combines with several sensitive chips 3 by being provided with knitting layer 2.

Several

sensitive chips

3,3 of each sensitive chips have interval 31, are arranged on by a knitting layer 2 on the first surface 11 of wafer 1, and its each sensitive chip 3 tops are respectively equipped with colour filter array 4.

Colour filter array 4 utilizes knitting layer 2 to be arranged at each sensitive chip 3 top respectively.

Glass substrate 5, its glass substrate 5 one sides are provided with a plurality of weirs wall 51, and be arranged at by this weir wall 51 above 31 places, interval of each sensitive chip 3, and make glass substrate 5 and colour filter array 4 form appropriate gap, wherein this weir wall 51 is photoresist (a for example anti-welding green lacquer).

And second surface 12 construction in regular turn of wafer 1 has substrate 61, first insulating barrier 62, conductive layer 63, and second insulating barrier 64 and circuit pin 65 of outermost, each circuit pin 65 passes second insulating barrier 64 and contacts with conductive layer 63, the electric connection that constitutes between wafer 1 and the circuit pin 65 by conductive layer 63 again, and can be used as the solder joint that this sensitized chip encapsulation structure 10 is connected with printed circuit board (PCB).

With this, constitute a kind of this photo-sensitive cell and directly be established on the wafer, can reduce and stop light, increasing light penetration rate and sensitization usefulness, and the advantage that can improve this resolution and have high pixel when being applied to the pickup image device.

As for, the encapsulation flow process of whole sensitized chip encapsulation structure 10 such as Fig. 2 include in regular turn to shown in Figure 12:

First surface 11 at wafer 1 is provided with knitting layer 2, and construction has a plurality of sensitive chips 3 on knitting layer 2, and as shown in Figure 2,3 of each sensitive chips have interval 31.

On sensitive chip 3, utilize knitting layer 2 that colour filter array 4 is set, as shown in Figure 3.

The glass substrate 5 that is provided with weir wall 51 is provided, and as shown in Figure 4, these glass substrate 5 one sides are provided with a plurality of weirs wall 51.

This glass substrate 5 is covered in colour filter array 4 tops, and as shown in Figure 5, and each weir wall 51 is arranged at interval 31 places, and utilizes this weir wall 51 to make glass substrate 5 and colour filter array 4 form appropriate gap.

Substrate is adhered step as shown in Figure 6, and the second surface 12 that corresponds to sensitive chip 3 at wafer 1 has substrate 61 by knitting layer 2 adhesions, and this substrate 61 also can be glass material.

The first insulating barrier construction step is shown in Fig. 7 (A), (B), on substrate 61, be coated with insulating material 621, when implementing, insulating material 621 can be photoresist or resin, and after imposing suitable planarization, utilize the exposure imaging mode to form first insulating barrier 62 again in the ad-hoc location of substrate 61.

Cutting step differs from first insulating barrier, 62 places in substrate 61 and is formed with the first road chase 71 as shown in Figure 8 for the first time, and the degree of depth of this first road chase 71 is to touch weir wall 51 or to stretch into weir wall 51.

The conductive layer construction be coated with the metal material of one deck as encapsulation conductive layer 63 at first insulating barrier, 62 bottoms, and this conductive layer 63 extends to the first road chase, 71 surfaces as shown in Figure 9.

The second insulating barrier construction is shown in Figure 10 (A), (B), bottom at conductive layer 63 is coated with insulating material to form second insulating barrier 64, this second insulating barrier 64 is similarly photoresist or resin, and utilizes the useful passage 641 that continues for conductive layer 63 and circuit pin of processing mode construction such as exposure, development.

The circuit pin is set as shown in figure 11,641 places are provided with circuit pin 65 at passage, its circuit pin 65 passes second insulating barrier 64 and contacts with conductive layer 63, the electric connection that constitutes between wafer 1 and the circuit pin 65 by conductive layer 63 again, and can be used as the solder joint that this sensitized chip encapsulation structure is connected with printed circuit board (PCB).

Cutting step is formed with the second road chase 72 that stretches into glass substrate 5 at the first road chase, 71 places as shown in figure 12 for the second time, so that each sensitive chip 3 is separated, makes each sensitized chip encapsulation structure 10 become complete individuality; Certainly, when sensitized chip encapsulation structure 10 encapsulated separately, this step can be saved equally.

Technology contents of the present invention and technical characterstic are open as above, yet those skilled in the art still may do various variation and the modifications that do not deviate from creation spirit of the present invention based on disclosure of the present invention.Therefore, it is disclosed that protection scope of the present invention should be not limited to embodiment, and should comprise various do not deviate from variation of the present invention and modifications, and contained by following claim.

Claims

1. A photosensitive chip packaging structure, which at least includes:

The wafer is provided with first and second surfaces, the first surface of which is combined with several photosensitive chips through a bonding layer, and there is a gap between each photosensitive chip;

The photosensitive chip is arranged on the first surface of the wafer through the bonding layer, and a color filter array is arranged above the photosensitive chip;

A glass substrate, one side of the glass substrate is provided with a plurality of dams, and the dams are arranged above the interval of the photosensitive chip, and a proper gap is formed between the glass substrate and the color filter array, wherein the photosensitive chip and the glass There is no metal interconnection between the substrates and a dielectric layer between the metal interconnections;

Wherein the second surface of the chip is sequentially constructed with a substrate, a first insulating layer, a conductive layer electrically connected to the photosensitive chip and the chip and an external circuit, and the outermost second insulating layer and circuit pins, each circuit pin wears contact with the conductive layer through the second insulating layer.

2 . The photosensitive chip packaging structure according to claim 1 , wherein the color filter arrays are respectively disposed above the photosensitive chips by using bonding layers. 3 .

3. The photosensitive chip package structure as claimed in claim 1, wherein the barrier wall is a photoresist material.

4. The photosensitive chip package structure as claimed in claim 3, wherein the photoresist material is solder resist green paint.

5. A method for manufacturing a photosensitive chip package, comprising the following steps:

A bonding layer is provided on one side of the wafer, and a plurality of photosensitive chips are constructed on the bonding layer;

A color filter array is set on the photosensitive chip;

Provide glass substrates with weir walls;

The glass substrate is covered on the color filter array, and a suitable gap is formed between the glass substrate and the color filter array by using a dam wall, wherein the dam wall is located at the space between each photosensitive chip, wherein the photosensitive chip and the glass substrate Does not contain metal interconnection layers and dielectric layers between metal interconnection layers;

On the other side of the wafer where the photosensitive chip is disposed, the substrate is sequentially arranged, the first insulating layer is constructed, a first cutting step is performed to form a first groove on the substrate different from the first insulating layer, and the substrate is constructed. Having a conductive layer electrically connected to the photosensitive chip and the chip and external circuits, constructing a second insulating layer, and setting circuit pins; and

A second dicing step is performed to separate each of the photosensitive chips.

6 . The method for manufacturing a photosensitive chip package as claimed in claim 5 , wherein in the substrate bonding step, a substrate is bonded to the other side of the wafer corresponding to the photosensitive chip through a bonding layer. 7 .

7. The method for manufacturing a photosensitive chip package as claimed in claim 5, wherein in the step of constructing the first insulating layer, an insulating material is coated on the substrate, and then the first insulating layer is formed on a specific position of the substrate by means of exposure and development.

8 . The method for manufacturing photosensitive chip packages as claimed in claim 5 , wherein the depth of the groove reaches the weir wall. 9 .

9. The method for manufacturing a photosensitive chip package as claimed in claim 5, wherein the barrier wall is a photoresist material.

10. The method for manufacturing a photosensitive chip package as claimed in claim 9, wherein the photoresist material is solder resist green paint.