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KR100674238B1 - Manufacturing method of high mobility self-aligning TF - Google Patents

Manufacturing method of high mobility self-aligning TF Download PDF

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KR100674238B1
KR100674238B1 KR1020000087247A KR20000087247A KR100674238B1 KR 100674238 B1 KR100674238 B1 KR 100674238B1 KR 1020000087247 A KR1020000087247 A KR 1020000087247A KR 20000087247 A KR20000087247 A KR 20000087247A KR 100674238 B1 KR100674238 B1 KR 100674238B1
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layer
forming
source
patterning
gate insulating
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KR20020057016A (en
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인태형
최대림
손곤
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비오이 하이디스 테크놀로지 주식회사
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]

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Abstract

본 발명은 대면적에 적합하고 기생용량을 최소화할 수 있는 고이동도 자기정렬 TFT 제조방법을 개시하며, 개시된 본 발명의 방법은, 절연성 기판 상에 비정질 실리콘층을 도포하고 마스크를 사용해서 패터닝하여 액티브 패턴을 형성하는 단계; 상기 액티브 패턴이 덮혀지도록 상기 절연성 기판 전면 상에 게이트 절연층을 형성하는 단계; 상기 게이트 절연층 전면 상에 게이트 전극층을 형성하는 단계; 상기 게이트 전극층 및 게이트 절연층을 패터닝하여 게이트 절연층 패턴과 게이트 전극을 형성하는 단계; 상기 게이트 전극이 형성된 기판 결과물에 대해 RF PECVD(Plasma Enhanced Chemical Vapor Deposition) 챔버내에서 PH3 플라즈마를 도핑해서 오믹층을 형성하는 단계; 상기 오믹층이 형성된 기판 결과물 상에 연속적으로 패시베이션층을 증착한 후 콘택홀을 형성하는 단계; 상기 패시베이션층 상에 소스/드레인 층을 형성한 후 이를 패터닝하여 소스/드레인 전극을 형성하는 단계; 및 상기 소스/드레인 전극을 포함한 패시베이션층 상에 픽셀 전극층을 형성한 후 이를 패터닝하여 픽셀전극을 형성해서 픽셀 TFT 영역과 캐패시턴스 저장영역을 형성하는 단계;를 포함하는 것을 특징으로 한다.The present invention discloses a method of fabricating a high mobility self-aligning TFT that is suitable for large areas and minimizes parasitic capacitance, and the disclosed method of the present invention comprises applying an amorphous silicon layer on an insulating substrate and patterning it using a mask. Forming an active pattern; Forming a gate insulating layer on the entire surface of the insulating substrate so that the active pattern is covered; Forming a gate electrode layer on an entire surface of the gate insulating layer; Patterning the gate electrode layer and the gate insulating layer to form a gate insulating layer pattern and a gate electrode; Doping a PH3 plasma in an RF Plasma Enhanced Chemical Vapor Deposition (PECVD) chamber to form a ohmic layer on the substrate product on which the gate electrode is formed; Depositing a passivation layer continuously on the substrate product on which the ohmic layer is formed, and then forming a contact hole; Forming a source / drain layer on the passivation layer and then patterning the source / drain electrode to form a source / drain electrode; And forming a pixel electrode layer on the passivation layer including the source / drain electrodes and patterning the pixel electrode layer to form a pixel electrode to form a pixel TFT region and a capacitance storage region.

Description

고이동도 자기정렬 티에프티 제조방법{METHOD FOR MANUFACTURING SELF-ALIGNMENT TFT HAVING HIGH MOBILITY}Manufacturing method of high mobility self-aligning TF {METHOD FOR MANUFACTURING SELF-ALIGNMENT TFT HAVING HIGH MOBILITY}

도 1 은 BCE구조를 갖는 박막트랜지스터를 도시한 단면도.1 is a cross-sectional view showing a thin film transistor having a BCE structure.

도 2a 내지 도 2f는 본 발명의 실시예에 따른 BCE구조의 고이동도 자기정렬 TFT 제조방법을 설명하기 위한 공정 단면도이다.2A to 2F are cross-sectional views illustrating a method of manufacturing a high mobility self-aligning TFT of a BCE structure according to an embodiment of the present invention.

(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

11 : 유리기판 12 : 액티브 패턴11: glass substrate 12: active pattern

13 : 게이트 절연층 14 : 게이트 전극13 gate insulating layer 14 gate electrode

15 : PH3 플라즈마 15: PH3 plasma

본 발명은 고이동도 자기정렬 TFT 제조방법에 관한 것으로, 보다 상세하게는, 대면적에 적합하고, 기생용량을 최소화할 수 있는 고이동도 자기정렬 TFT 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a high mobility self-aligning TFT, and more particularly, to a method of manufacturing a high mobility self-aligning TFT capable of minimizing parasitic capacitance.

텔레비젼 및 그래픽 디스플레이 등의 표시 장치에 이용되는 액정표시소자(Liquid Crystal Display : 이하, LCD)는 CRT(Cathode-ray tube)를 대 신하여 개발되어져 왔다. 특히, 매트릭스 형태로 배열된 각 화소마다 박막 트랜지스터(Thin Film Transistor : 이하, TFT)가 구비되는 TFT LCD는 고속 응답 특성을 갖는 잇점과 고화소수에 적합하다는 잇점 때문에 CRT에 필적할만한 화면의 고화질화 및 대형화, 컬러화 등을 실현하고 있다. Liquid crystal displays (LCDs) used in display devices such as televisions and graphic displays have been developed in place of the CRT (Cathode-ray tube). In particular, TFT LCDs equipped with thin film transistors (TFTs) for each pixel arranged in a matrix form have high speed response characteristics and are suitable for high pixel numbers, so that the screen quality comparable to the CRT is increased and the size of the screen is comparable. Colorization is realized.

도 1은 종래 기술에 따른 BCE(Back Channel Etch) 구조의 TFT를 도시한 도면으로서, 이를 참조하여 그 제조방법을 설명하도록 한다. 우선, 절연성 기판, 예컨데, 유리기판(1) 상에 게이트 전극(2)을 형성하고, 상기 게이트 전극(2)을 포함한 유리기판(1)의 전면 상에 게이트 절연층(3)을 도포한다. 그런 다음, 게이트 절연층(3) 상에 도핑되지 않은 비정질 실리콘층과 도핑된 비정질 실리콘층을 순차적으로 증착한다. 여기서, 도핑되지 않은 비정질실리콘층은 TFT에서 채널층으로 이용되는 층이며, 특히, 그 특성 향상을 위해 수소 이온이 함유되어 있다. 그리고, 도핑된 비정질 실리콘층은 TFT의 채널층과 후속에서 형성되는 금속 재질의 소오스/드레인 전극과의 접촉 특성을 향상시키기 위한 오믹층으로 이용되는 층이다. 계속해서, 도핑된 비정질실리콘층 및 도핑되지 않은 비정질 실리콘층을 패터닝하여 게이트 전극(2) 상부의 게이트 절연층(3) 상에 패턴의 형태로 오믹층(5) 및 채널층(4)을 형성한다. 그런 다음, 전체 상부에 소정의 금속막을 증착하고, 이를 식각하여 TFT의 소오스/드레인 전극(6, 7)을 형성한다. 이때, 소오스 전극(6)과 드레인 전극(7)은 분리되게 형성하며, 이에 따라, 오믹층(5)의 중심 부분은 노출된다. 그리고 나서, 소오스 전극(6)과 드레인 전극(7)이 전기적으로 분리되도록, SF6 가스를 이용한 식각 공정으로 노출된 오믹층(5) 부분을 제거하여 BCE 구조의 TFT를 완성한다.FIG. 1 is a view illustrating a TFT having a BCE (Back Channel Etch) structure according to the related art, and a method of manufacturing the same will be described with reference to the TFT. First, a gate electrode 2 is formed on an insulating substrate, for example, a glass substrate 1, and a gate insulating layer 3 is applied on the entire surface of the glass substrate 1 including the gate electrode 2. Then, an undoped amorphous silicon layer and a doped amorphous silicon layer are sequentially deposited on the gate insulating layer 3. Here, the undoped amorphous silicon layer is a layer used as a channel layer in the TFT, and especially contains hydrogen ions to improve its properties. The doped amorphous silicon layer is a layer used as an ohmic layer to improve contact characteristics between a channel layer of the TFT and a metal source / drain electrode formed subsequently. Subsequently, the doped amorphous silicon layer and the undoped amorphous silicon layer are patterned to form the ohmic layer 5 and the channel layer 4 in the form of a pattern on the gate insulating layer 3 above the gate electrode 2. do. Then, a predetermined metal film is deposited on the whole and etched to form source / drain electrodes 6 and 7 of the TFT. At this time, the source electrode 6 and the drain electrode 7 are formed to be separated, whereby the central portion of the ohmic layer 5 is exposed. Then, the portion of the ohmic layer 5 exposed by the etching process using SF6 gas is removed so that the source electrode 6 and the drain electrode 7 are electrically separated, thereby completing the TFT of the BCE structure.

현재 일반적으로 TFT-LCD를 제작하기 위해서는 BCE형 구조의 5 마스크(mask) 스텝(step)을 적용해서 TFT 어레이를 제작하고 있다. 그러나 대면적에 적합한 TFT 어레이를 제작하기 위해서는 유효 전계이동도가 1cm2/Vs 이상인 TFT를 제작하여 기생용량을 최소화할 수 있도록 자기정렬 구조의 a-Si TFT를 제작하는 것이 필요하다. Currently, in order to manufacture a TFT-LCD, a TFT array is manufactured by applying five mask steps of a BCE type structure. However, in order to manufacture a TFT array suitable for a large area, it is necessary to manufacture a self-aligned a-Si TFT to minimize parasitic capacitance by manufacturing a TFT having an effective field mobility of 1 cm 2 / Vs or more.

그러나 자기정렬형의 TFT를 제작하기 위해서는 이온 주입(Ion Implantation), 이온 도핑시스템(Ion Doping System)등의 장비가 추가되어야만 한다. 따라서 초기 생산투자비가 많이 들어가고 공정수가 증가함에 따라 TAT의 증가가 발생하는 문제점이 있었다.However, in order to manufacture self-aligned TFTs, equipment such as ion implantation and ion doping system must be added. Therefore, there is a problem that the increase in the TAT occurs as the initial production investment costs go up and the number of processes increases.

본 발명의 목적은 TFT 어레이의 생산성을 높이기 위한 방법으로 5 마스크 스텝만에 의해 TFT 어레이를 제작하는 공정과 자기 정렬형의 TFT 구조를 적용하여 전계이동도를 증가시키는 공정을 적용한 고이동도 자기정렬 TFT 제조방법을 제공하는데 있다.An object of the present invention is a method for increasing the productivity of a TFT array, a high mobility self-alignment applying a process of manufacturing a TFT array by only 5 mask steps and a process of increasing the field mobility by applying a self-aligning TFT structure It is to provide a TFT manufacturing method.

상기한 바와 같은 목적을 달성하기 위하여 본 발명의 바람직한 실시예에 따르면, 절연성 기판 상에 비정질 실리콘층을 도포하고 마스크를 사용해서 패터닝하여 액티브 패턴을 형성하는 단계; 상기 액티브 패턴이 덮혀지도록 상기 절연성 기판 전면 상에 게이트 절연층을 형성하는 단계; 상기 게이트 절연층 전면 상에 게이트 전극층을 형성하는 단계; 상기 게이트 전극층 및 게이트 절연층을 패터닝하여 게이트 절연층 패턴과 게이트 전극을 형성하는 단계; 상기 게이트 전극이 형성된 기판 결과물에 대해 RF PECVD(Plasma Enhanced Chemical Vapor Deposition) 챔버내에서 PH3 플라즈마를 도핑해서 오믹층을 형성하는 단계; 상기 오믹층이 형성된 기판 결과물 상에 연속적으로 패시베이션층을 증착한 후 콘택홀을 형성하는 단계; 상기 패시베이션층 상에 소스/드레인 층을 형성한 후 이를 패터닝하여 소스/드레인 전극을 형성하는 단계; 및 상기 소스/드레인 전극을 포함한 패시베이션층 상에 픽셀 전극층을 형성한 후 이를 패터닝하여 픽셀전극을 형성해서 픽셀 TFT 영역과 캐패시턴스 저장영역을 형성하는 단계;를 포함하는 것을 특징으로 하는 고이동도 자기정렬 TFT 제조방법이 제공된다.According to a preferred embodiment of the present invention to achieve the object as described above, forming an active pattern by applying an amorphous silicon layer on an insulating substrate and patterning using a mask; Forming a gate insulating layer on the entire surface of the insulating substrate so that the active pattern is covered; Forming a gate electrode layer on an entire surface of the gate insulating layer; Patterning the gate electrode layer and the gate insulating layer to form a gate insulating layer pattern and a gate electrode; Doping a PH3 plasma in an RF Plasma Enhanced Chemical Vapor Deposition (PECVD) chamber to form a ohmic layer on the substrate product on which the gate electrode is formed; Depositing a passivation layer continuously on the substrate product on which the ohmic layer is formed, and then forming a contact hole; Forming a source / drain layer on the passivation layer and then patterning the source / drain electrode to form a source / drain electrode; And forming a pixel electrode layer on the passivation layer including the source / drain electrodes and patterning the pixel electrode layer to form a pixel electrode to form a pixel TFT region and a capacitance storage region. TFT manufacturing method is provided.

또한, 본 발명에 있어서 상기 PH3 도핑단계에서 혼합하는 가스는 H2, He, N2, Ar, N2O, NH3를 이용하는 것을 특징으로 한다.In the present invention, the gas mixed in the PH3 doping step is characterized by using H2, He, N2, Ar, N2O, NH3.

또한, 본 발명에 있어서 상기 PH3 도핑은 파워(POWER)는 1000∼2000W, 스페이싱(spacing)은 500∼1000mils, 도핑시간은 1∼5분, 그리고, 압력은 1000∼2000mTorr로 하는 조건으로 수행하는 것을 특징으로 한다.In the present invention, the PH3 doping is performed under conditions such that the power is 1000 to 2000 W, the spacing is 500 to 1000 mils, the doping time is 1 to 5 minutes, and the pressure is 1000 to 2000 mTorr. It features.

본 발명에 적용된 기술은 오믹층을 형성하기 위해 기존의 RF PECVD 장비 내에서 PH3 플라즈마만으로 소오스/드레인 영역을 형성할 수 있도록 하는 기술이다.The technique applied to the present invention is a technique for forming a source / drain region using only PH3 plasma in existing RF PECVD equipment to form an ohmic layer.

기존에는 자기정렬의 TFT를 제작하기 위해서는 이온도핑 또는 이온 주입 장 치등을 이용하였으나 기존 생산 라인을 자기 정렬형의 TFT 어레이를 생산하는 라인으로 바꾸기 위해서는 기존의 장비를 최대한 활용하는 것이 바람직하다.Conventionally, ion doping or ion implantation devices have been used to fabricate self-aligned TFTs, but it is desirable to make the most of existing equipment to convert existing production lines into lines that produce self-aligned TFT arrays.

이를 위해 본 발명에서는 기존의 PECVD 장비를 이용하여 최적의 도핑조건을 개발하여 고효율의 도핑이 이루어지도록 하였다. 고효율의 도핑이 이루어지기 위해 주요한 요소는 파워, 스페이싱, 압력등이다.To this end, in the present invention, an optimal doping condition was developed using a conventional PECVD equipment to achieve high efficiency doping. The main elements for high efficiency doping are power, spacing and pressure.

이하, 본 발명의 바람직한 일 실시예에 대하여 첨부도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention will be described in detail.

도 2a 내지 도 2f는 본 발명에 따른 고이동도 자기정렬 TFT 제조방법을 설명하기 위한 공정 단면도로서, 이에 도시한 바와 같이, 절연성 기판, 예컨데, 유리기판(11) 상에 비정질 실리콘층(a-Si:H)을 도포하고 제 1 마스크(도시안됨)를 사용하여 패터닝하여 액티브 패턴(12)을 형성하고, 상기 액티브 패턴(12)이 덮혀지도록 유리기판(11) 전면 상에 게이트 절연층(13)을 도포한다. 상기 게이트 절연층(13)은 SiNx, SiON, SiO2가 사용되는데 단일층을 사용하거나 이중층 이상의 박막을 증착할 수 있으며, 이 실시예에서는 500Å의 SiNx와 3500Å의 SiON의 이중막을 사용하였다.2A to 2F are cross-sectional views illustrating a method of manufacturing a high mobility self-aligning TFT according to the present invention. As shown therein, an amorphous silicon layer (a-) is formed on an insulating substrate, for example, a glass substrate 11. Si: H) is applied and patterned using a first mask (not shown) to form the active pattern 12, and the gate insulating layer 13 on the entire surface of the glass substrate 11 so that the active pattern 12 is covered. ) Is applied. SiNx, SiON, SiO2 is used as the gate insulating layer 13, and a single layer may be used or a thin film of two or more layers may be deposited. In this embodiment, a double layer of 500 ns of SiNx and 3500 ns of SiON is used.

그런 다음, 상기 게이트 절연층(13) 전면 상에 게이트 전극층(14)을 형성한다. 상기 게이트 전극층(14)은 Mo,W,Al, MoW, Cu, Ag 중의 단일층을 사용하거나 2종류 이상의 합금 또는 2중 혹은 3중 층을 이용해서 형성하였다.Then, the gate electrode layer 14 is formed on the entire surface of the gate insulating layer 13. The gate electrode layer 14 was formed using a single layer of Mo, W, Al, MoW, Cu, Ag, or using two or more kinds of alloys or double or triple layers.

다음으로, 도 2c에 도시된 바와 같이, 상기 게이트 전극층(14)까지 형성한 뒤 마스크(두번째)를 사용하여 게이트 전극을 형성한다. 이때 게이트 절연층(13)도 한꺼번에 식각시키는데, 즉, 상기 게이트 절연층(13)과 게이트 전극층(14)을 패터닝하여 게이트 절연막(13a,13b)과 게이트 전극(14a,14b)을 형성한다.Next, as shown in FIG. 2C, the gate electrode layer 14 is formed and then the gate electrode is formed using a mask (second). At this time, the gate insulating layer 13 is also etched at once, that is, the gate insulating layer 13 and the gate electrode layer 14 are patterned to form the gate insulating layers 13a and 13b and the gate electrodes 14a and 14b.

이어서, 도 2d에 도시한 바와 같이, 게이트 전극(14a,14b)을 포함한 전면상에 오믹층을 형성하기 위하여 RF PECVD(Plasma Enhanced Chemical Vapor Deposition)내에서 PH3 플라즈마(15)를 도핑한다. 이과정에서 이종의 가스를 혼합시켜 P도핑 효율을 증가시킨다. 이때, 혼합하는 가스는 H2, He, N2, Ar, N2O, NH3를 이용한다. 또한, 상기 P도핑 조건은 파워(POWER)는 1000W이상, 스페이싱(spacing)은 1000mils이하이며, 도핑시간은 1분 이상, 압력은 1000mTorr이상으로 한다. 바람직하게, P도핑 조건은 파워는 1000∼2000W, 스페이싱(spacing)은 500∼1000mils, 도핑시간은 1∼5분, 그리고, 압력은 1000∼2000mTorr 정도로 한다.Then, as shown in FIG. 2D, the PH3 plasma 15 is doped in RF PECVD (Plasma Enhanced Chemical Vapor Deposition) to form an ohmic layer on the front surface including the gate electrodes 14a and 14b. In this process, heterogeneous gases are mixed to increase the P doping efficiency. At this time, the gas to be mixed uses H2, He, N2, Ar, N2O, NH3. In addition, the P doping condition is the power (POWER) is more than 1000W, the spacing (spacing) is less than 1000mils, the doping time is more than 1 minute, the pressure is more than 1000mTorr. Preferably, the P doping conditions are such that the power is 1000 to 2000 W, the spacing is 500 to 1000 mils, the doping time is 1 to 5 minutes, and the pressure is about 1000 to 2000 mTorr.

상기 PECVD를 이용해서 PH3를 도핑해서 오믹 접합층을 형성하고 이를 통해 탑 게이트(Top Gate)방식의 TFT를 제작할 수도 있다.The PECVD may be used to form an ohmic junction layer by doping PH3, thereby manufacturing a top gate TFT.

이어서, 도 2e에 도시한 바와 같이, PECVD를 이용하여 PH3를 도핑후에 연속적으로 패시베이션 층(16)을 증착한 후 마스크(세번째)를 이용하여 콘택 패터닝과정을 통해 콘택홀(17)을 형성한다.Next, as shown in FIG. 2E, the passivation layer 16 is continuously deposited after the doping of PH3 using PECVD, and then the contact hole 17 is formed through the contact patterning process using a mask (third).

이후, 도 2f에 도시한 바와 같이, 소스/드레인 층을 형성한 후 마스크(네번째)를 이용하여 소스/드레인 전극 패터닝 공정을 통해 소스/드레인 전극(18)을 형성한다.Thereafter, as shown in FIG. 2F, after the source / drain layer is formed, the source / drain electrode 18 is formed through the source / drain electrode patterning process using a mask (fourth).

이후, 도 2g에 도시한 바와 같이, 픽셀 전극층을 형성한 후 마스크(다섯번째)를 이용하여 패터닝 공정을 통해 픽셀전극(19)을 형성하는데, 이로써 픽셀 TFT 영역과 캐패시턴스 저장영역이 형성된다.Thereafter, as shown in FIG. 2G, the pixel electrode layer is formed using a mask (fifth) and then the pixel electrode 19 is formed through a patterning process, thereby forming a pixel TFT region and a capacitance storage region.

한편, 상기 소스/드레인 층위에는 다른 층을 올리지 않음으로써 5마스크 이 내의 공정으로 단축할 수도 있다.On the other hand, by not raising another layer on the source / drain layer it can be shortened to a process within 5 masks.

상기 설명한 바와 같이, 본 발명에 따른 고이동도 자기정렬 TFT 제조방법에 의하면, 5마스크 만을 이용해서 자기 정렬형의 TFT를 형성할 수 있게 되었고, 소스/드레인의 오믹(ohmic)도 추가적인 장비 없이 패시베이션 층 증착전에 인시튜(in-situ)로 PH3만을 이용해서 형성하게 되어 장비 및 공정 수를 획기적으로 감소시킨 효과가 있고, 이상의 공정 개발을 통해 유효전계 이동도는 기존의 바텀 게이트(Bottom Gate)형 TFT에 비해 획기적으로 증가된 효과가 있다.As described above, according to the method of manufacturing a high mobility self-aligning TFT according to the present invention, it is possible to form a self-aligning TFT using only 5 masks, and even ohmic of source / drain without passivation. It is formed by using only PH3 in-situ before layer deposition, which has the effect of drastically reducing the number of equipment and processes, and the effective field mobility is the existing bottom gate type through the above process development. Compared to TFT, there is a drastically increased effect.

상기한 본 발명의 바람직한 실시예는 예시의 목적을 위해 개시된 것이며, 당업자라면 본 발명의 사상과 범위 안에서 다양한 수정, 변경, 부가 등이 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구의 범위에 속하는 것으로 보아야 할 것이다.The preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, and such modifications and changes belong to the following claims Should be seen.

Claims (3)

절연성 기판 상에 비정질 실리콘층을 도포하고 마스크를 사용해서 패터닝하여 액티브 패턴을 형성하는 단계; Applying an amorphous silicon layer on the insulating substrate and patterning using a mask to form an active pattern; 상기 액티브 패턴이 덮혀지도록 상기 절연성 기판 전면 상에 게이트 절연층을 형성하는 단계; Forming a gate insulating layer on the entire surface of the insulating substrate so that the active pattern is covered; 상기 게이트 절연층 전면 상에 게이트 전극층을 형성하는 단계; Forming a gate electrode layer on an entire surface of the gate insulating layer; 상기 게이트 전극층 및 게이트 절연층을 패터닝하여 게이트 절연층 패턴과 게이트 전극을 형성하는 단계; Patterning the gate electrode layer and the gate insulating layer to form a gate insulating layer pattern and a gate electrode; 상기 게이트 전극이 형성된 기판 결과물에 대해 RF PECVD(Plasma Enhanced Chemical Vapor Deposition) 챔버내에서 PH3 플라즈마를 도핑해서 오믹층을 형성하는 단계; Doping a PH3 plasma in an RF Plasma Enhanced Chemical Vapor Deposition (PECVD) chamber to form a ohmic layer on the substrate product on which the gate electrode is formed; 상기 오믹층이 형성된 기판 결과물 상에 연속적으로 패시베이션층을 증착한 후 콘택홀을 형성하는 단계; Depositing a passivation layer continuously on the substrate product on which the ohmic layer is formed, and then forming a contact hole; 상기 패시베이션층 상에 소스/드레인 층을 형성한 후 이를 패터닝하여 소스/드레인 전극을 형성하는 단계; 및 Forming a source / drain layer on the passivation layer and then patterning the source / drain electrode to form a source / drain electrode; And 상기 소스/드레인 전극을 포함한 패시베이션층 상에 픽셀 전극층을 형성한 후 이를 패터닝하여 픽셀전극을 형성해서 픽셀 TFT 영역과 캐패시턴스 저장영역을 형성하는 단계;를 포함하는 것을 특징으로 하는 고이동도 자기정렬 TFT 제조방법.Forming a pixel electrode layer on the passivation layer including the source / drain electrodes and patterning the pixel electrode layer to form a pixel electrode to form a pixel TFT region and a capacitance storage region; Manufacturing method. 제 1 항에 있어서, 상기 PH3 도핑단계에서 혼합하는 가스는 H2, He, N2, Ar, N2O, NH3를 이용하는 것을 특징으로 하는 고이동도 자기정렬 TFT 제조방법.The method of claim 1, wherein the gas mixed in the PH3 doping step uses H2, He, N2, Ar, N2O, NH3. 제 1 항에 있어서, 상기 PH3 도핑은 파워(POWER)는 1000∼2000W, 스페이싱(spacing)은 500∼1000mils, 도핑시간은 1∼5분, 그리고, 압력은 1000∼2000mTorr로 하는 조건으로 수행하는 것을 특징으로 하는 고이동도 자기정렬 TFT 제조방법.The method of claim 1, wherein the PH3 doping is performed under conditions such that the power is 1000 to 2000 W, the spacing is 500 to 1000 mils, the doping time is 1 to 5 minutes, and the pressure is 1000 to 2000 mTorr. A high mobility self-aligning TFT manufacturing method characterized by the above-mentioned.
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