JPH07273336A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPH07273336A JPH07273336A JP5927094A JP5927094A JPH07273336A JP H07273336 A JPH07273336 A JP H07273336A JP 5927094 A JP5927094 A JP 5927094A JP 5927094 A JP5927094 A JP 5927094A JP H07273336 A JPH07273336 A JP H07273336A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor layer
- type semiconductor
- thin film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 108
- 239000010408 film Substances 0.000 claims abstract description 70
- 239000007789 gas Substances 0.000 claims abstract description 34
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 25
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 22
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 19
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000001257 hydrogen Substances 0.000 claims abstract description 9
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 9
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims abstract description 7
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 139
- 239000000758 substrate Substances 0.000 description 24
- 239000011521 glass Substances 0.000 description 17
- 239000011241 protective layer Substances 0.000 description 14
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910000077 silane Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003028 elevating effect Effects 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- JZLMRQMUNCKZTP-UHFFFAOYSA-N molybdenum tantalum Chemical compound [Mo].[Ta] JZLMRQMUNCKZTP-UHFFFAOYSA-N 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、薄膜トランジスタの製
造方法に係り、特に液晶表示装置に用いられる薄膜トラ
ンジスタの製造に有効な薄膜トランジスタの製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly to a method of manufacturing a thin film transistor which is effective in manufacturing a thin film transistor used in a liquid crystal display device.
【０００２】[0002]
【従来の技術】薄膜トランジスタは、液晶表示装置や密
着センサなどですでに実用化されている。特にその液晶
表示装置は、可搬性、薄型、軽量、省スペースなどの特
徴を備え、将来性が大きく注目されている。この液晶表
示装置の中でも、高コントラスト、高画質、中間調表示
が可能で応答速度の速い薄膜トランジスタ方式の液晶表
示装置が最も大きく注目されている。2. Description of the Related Art Thin film transistors have already been put to practical use in liquid crystal display devices and contact sensors. In particular, the liquid crystal display device has characteristics such as portability, thinness, light weight, and space saving, and its future potential has attracted great attention. Among these liquid crystal display devices, a thin film transistor type liquid crystal display device capable of high contrast, high image quality and halftone display and having a high response speed has been receiving the most attention.
【０００３】この液晶表示装置の薄膜トランジスタとし
ては、活性層の大面積化が可能であり、かつ比較的低温
度で形成可能な非晶質シリコン（ａ−Ｓi ）系の半導体
が用いられている。この非晶質シリコン系の薄膜トラン
ジスタには、透明絶縁基板上に活性層である非晶質シリ
コン層を挟んで、下層にゲート電極が配置され、上層に
ソース電極およびドレイン電極が配置された逆スタガー
型構造が多く採用されている。As a thin film transistor of this liquid crystal display device, an amorphous silicon (a-Si) based semiconductor is used, which has a large active layer area and can be formed at a relatively low temperature. This amorphous silicon-based thin film transistor has an inverted staggered structure in which a gate electrode is arranged in a lower layer and a source electrode and a drain electrode are arranged in an upper layer with an amorphous silicon layer which is an active layer sandwiched on a transparent insulating substrate. Many mold structures are used.
【０００４】この逆スタガー型構造の薄膜トランジスタ
は、透明絶縁基板に形成されたゲート電極上にプラズマ
ＣＶＤ法によりゲート絶縁層、半導体層およびｎ型半導
体層を連続的に形成するか、あるいはゲート絶縁層、半
導体層および半導体保護層を連続的に形成したのち、そ
の半導体保護層を所望の形状に加工し、ついでｎ型半導
体層を形成することにより得られる。In this inverted stagger type thin film transistor, a gate insulating layer, a semiconductor layer and an n-type semiconductor layer are continuously formed by a plasma CVD method on a gate electrode formed on a transparent insulating substrate, or the gate insulating layer is formed. It is obtained by continuously forming a semiconductor layer and a semiconductor protective layer, processing the semiconductor protective layer into a desired shape, and then forming an n-type semiconductor layer.
【０００５】そのｎ型半導体層は、ソース電極およびド
レイン電極と半導体層とのオーミックコンタクトをとる
ために、きわめて重要な役割を果たしている。The n-type semiconductor layer plays an extremely important role for making ohmic contact between the source electrode and the drain electrode and the semiconductor layer.
【０００６】従来、上記ｎ型半導体層を形成する場合、
インライン式プラズマＣＶＤ装置を用い、反応圧力１３
３Pa（１．０Torr）程度の雰囲気中で、１０nm/min程度
の成膜速度で成膜している。この場合、半導体層とｎ型
半導体層との界面を清浄にするため、水素ガス雰囲気中
で半導体層表面をプラズマ処理することがおこなわれて
いる。このようなプラズマ処理の一方法として、水素ガ
ス雰囲気中でプラズマ放電を励起して半導体層表面をエ
ッチングし、一旦プラズマ放電を停止したのち、成膜ガ
スを導入してｎ型半導体層を成膜する方法が、特公昭５
９−１４５４９号公報に示されている。Conventionally, when forming the n-type semiconductor layer,
Reaction pressure of 13 using an in-line type plasma CVD apparatus
The film is formed in an atmosphere of about 3 Pa (1.0 Torr) at a film forming rate of about 10 nm / min. In this case, in order to clean the interface between the semiconductor layer and the n-type semiconductor layer, the surface of the semiconductor layer is plasma-treated in a hydrogen gas atmosphere. As one method of such plasma treatment, plasma discharge is excited in a hydrogen gas atmosphere to etch the surface of the semiconductor layer, the plasma discharge is stopped once, and then a film forming gas is introduced to form an n-type semiconductor layer. How to do it
No. 9-14549.
【０００７】[0007]
【発明が解決しようとする課題】上記のように、従来、
薄膜トランジスタのｎ型半導体層の形成は、インライン
式プラズマＣＶＤ装置を用いておこなわれている。しか
し近年、このインライン式プラズマＣＶＤ装置にくらべ
て、省スペース、低パーティクル、高稼働率が特徴の枚
葉式プラズマＣＶＤ装置が主流になりつつある。この枚
葉式プラズマＣＶＤ装置では、絶縁基板を１枚ごとに処
理するため、インライン式プラズマＣＶＤ装置と同数程
度の絶縁基板を処理するためには、従来の成膜速度より
も数倍の高い成膜速度が必要となる。このことは、プラ
ズマＣＶＤ法による成膜のすべてに当はまる。特にｎ型
半導体層の成膜については、従来の８倍以上の成膜速度
（８０nm/min以上）が要求される。またこのｎ型半導体
層の成膜については、薄膜トランジスタのスループット
（throughput）を向上させるために、成膜に際し、基板
を急激に加熱冷却する場合がある。As described above, as described above,
The n-type semiconductor layer of the thin film transistor is formed using an in-line type plasma CVD device. However, in recent years, compared with this in-line type plasma CVD apparatus, a single-wafer type plasma CVD apparatus characterized by space saving, low particles, and high operation rate is becoming mainstream. In this single-wafer plasma CVD apparatus, since the insulating substrates are processed one by one, in order to process the same number of insulating substrates as in the in-line plasma CVD apparatus, the deposition rate is several times higher than the conventional film formation rate. Membrane speed is required. This applies to all film formation by the plasma CVD method. Particularly for the film formation of the n-type semiconductor layer, a film formation speed that is 8 times or more (80 nm / min or more) that of the conventional method is required. Regarding the film formation of the n-type semiconductor layer, in order to improve the throughput of the thin film transistor, the substrate may be rapidly heated and cooled during the film formation.
【０００８】したがって枚葉式プラズマＣＶＤ装置を用
いて従来の成膜速度の数倍高い成膜速度でおこなうプロ
セスでは、半導体層とｎ型半導体層との界面を清浄にす
るために、従来のように水素ガス雰囲気中でプラズマ放
電によるエッチング処理をおこなうと、その半導体層と
ｎ型半導体層との界面に膨れが発生し、基板が白濁する
など、半導体層表面に水素プラズマ・ダメージを与え
る。また成膜速度が高いため、界面近傍を良好に形成す
ることがむずかしく、良好な薄膜トランジスタ特性が安
定に得られなくなるなどの問題がある。Therefore, in a process in which a single-wafer plasma CVD apparatus is used at a film formation rate several times higher than the conventional film formation rate, a conventional method is used to clean the interface between the semiconductor layer and the n-type semiconductor layer. When an etching process by plasma discharge is performed in a hydrogen gas atmosphere, swelling occurs at the interface between the semiconductor layer and the n-type semiconductor layer, and the substrate becomes cloudy, causing hydrogen plasma damage to the semiconductor layer surface. Further, since the film forming rate is high, it is difficult to form the vicinity of the interface satisfactorily, and there is a problem that good thin film transistor characteristics cannot be stably obtained.
【０００９】本発明は、上記問題点を解決するためにな
されたものであり、半導体層とｎ型半導体層との界面を
良好に形成し、均一な特性を有する高品質な薄膜トラン
ジスタが得られる製造方法を得ることを目的とする。The present invention has been made in order to solve the above-mentioned problems, and manufactures a high quality thin film transistor having a uniform characteristic by forming an interface between a semiconductor layer and an n-type semiconductor layer well. Aim to get a way.
【００１０】[0010]
【課題を解決するための手段】少なくともゲート電極、
ゲート絶縁層、半導体層、ｎ型半導体層、ソース電極お
よびドレイン電極を有する薄膜トランジスタのｎ型半導
体層をプラズマＣＶＤ法により形成する薄膜トランジス
タの製造方法において、はじめに水素とホスフィンと成
膜時の総ガス流量に占める割合いが０．１〜５容量％以
下のモノシランとを含む成膜用ガス雰囲気中でプラズマ
放電を励起させかつこのプラズマ放電を０．１秒以上持
続させてｎ型半導体層の第１層を成膜し、ついでこのプ
ラズマ放電中にモノシランを導入してｎ型半導体層の第
２層を成膜するようにした。Means for Solving the Problems At least a gate electrode,
In a method of manufacturing a thin film transistor in which an n-type semiconductor layer of a thin film transistor having a gate insulating layer, a semiconductor layer, an n-type semiconductor layer, a source electrode and a drain electrode is formed by a plasma CVD method, first, hydrogen, phosphine, and a total gas flow rate at the time of film formation are formed. Of the first n-type semiconductor layer by exciting plasma discharge in a film forming gas atmosphere containing 0.1 to 5% by volume or less of monosilane and continuing this plasma discharge for 0.1 second or more. A layer was deposited and then monosilane was introduced during this plasma discharge to deposit the second layer of the n-type semiconductor layer.
【００１１】また、ｎ型半導体層の第１層を成膜すると
きの成膜用ガス雰囲気の圧力を第２層を成膜するときの
成膜用ガス雰囲気の圧力よりも低くした。Further, the pressure of the film forming gas atmosphere when forming the first layer of the n-type semiconductor layer is set to be lower than the pressure of the film forming gas atmosphere when forming the second layer.
【００１２】さらに、ｎ型半導体層の第１層の成膜速度
を第２層の成膜速度よりも遅くした。Further, the film forming rate of the first layer of the n-type semiconductor layer is set to be slower than the film forming rate of the second layer.
【００１３】[0013]
【作用】上記方法により薄膜トランジスタを製造する
と、半導体層とその上に形成されるｎ型半導体層との界
面を良好にすることができ、均一な特性を有する高品質
な薄膜トランジスタを製造することができる。When the thin film transistor is manufactured by the above method, the interface between the semiconductor layer and the n-type semiconductor layer formed thereon can be improved, and a high quality thin film transistor having uniform characteristics can be manufactured. .
【００１４】[0014]
【実施例】以下、図面を参照して本発明を実施例に基づ
いて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described based on embodiments with reference to the drawings.
【００１５】図１にその一実施例に係るアクティブマト
リックス型液晶表示装置に使用される薄膜トランジスタ
を示す。この薄膜トランジスタは、ガラス絶縁基板１上
にゲート線（図示せず）と一体に形成されたモリブデン
−タンタルからなる所定形状のゲート電極２と、このゲ
ート電極２を覆うように絶縁基板１上に形成された窒化
シリコンからなるゲート絶縁層３と、上記ゲート電極２
に対応してこのゲート絶縁層３を覆うように積層形成さ
れた非晶質シリコン（ａ−Ｓi ）または微結晶シリコン
または多結晶シリコンからなる所定形状の半導体層４
と、この半導体層４の一部を覆うように積層形成された
所定形状の半導体保護層５と、この半導体保護層５の一
部および上記半導体層４を覆うように積層形成されたｎ
型半導体層６と、このｎ型半導体層６上に積層形成さ
れ、一部が上記ゲート絶縁層３上のソース領域に延在す
るソース電極７と、同じくｎ型半導体層６上に積層形成
され、一部が上記ゲート絶縁層３上のドレイン領域に延
在する信号線（図示せず）と一体のドレイン電極８と、
これらソース電極７、ドレイン電極８および上記ｎ型半
導体層６の露出部を覆う窒化シリコンからなる絶縁保護
層９から構成されている。そのドレイン電極８は、ゲー
ト絶縁層３上に積層形成されたＩＴＯ（Imdium Tin Oxi
de）からなる画素電極１０に接続されている。FIG. 1 shows a thin film transistor used in an active matrix type liquid crystal display device according to the embodiment. This thin film transistor is formed on the insulating substrate 1 so as to cover the gate electrode 2 and a gate electrode 2 of molybdenum-tantalum having a predetermined shape, which is integrally formed with a gate line (not shown) on the glass insulating substrate 1. And a gate insulating layer 3 made of silicon nitride and the gate electrode 2
Corresponding to the gate insulating layer 3, a semiconductor layer 4 formed in a predetermined shape and made of amorphous silicon (a-Si), microcrystalline silicon or polycrystalline silicon laminated to cover the gate insulating layer 3.
A semiconductor protective layer 5 having a predetermined shape which is laminated so as to cover a part of the semiconductor layer 4, and n which is laminated so as to cover a part of the semiconductor protective layer 5 and the semiconductor layer 4.
The type semiconductor layer 6, a source electrode 7 laminated on the n-type semiconductor layer 6, and a part of which extends to the source region on the gate insulating layer 3, and a source electrode 7 also laminated on the n-type semiconductor layer 6. A part of the drain electrode 8 integrated with a signal line (not shown) extending to the drain region on the gate insulating layer 3,
The source electrode 7, the drain electrode 8 and the insulating protection layer 9 made of silicon nitride covering the exposed portion of the n-type semiconductor layer 6 are formed. The drain electrode 8 is formed by stacking ITO (Imdium Tin Oxide) on the gate insulating layer 3.
de) connected to the pixel electrode 10.
【００１６】この薄膜トランジスタの製造は、図２
（ａ）に示すように、まずガラス絶縁基板１上に、スパ
ッタ法によりモリブデン−タンタルからなる金属膜を成
膜し、この金属膜をフォトリソグラフィ法により、ゲー
ト線とともに所定形状のゲート電極２に形成する。The manufacture of this thin film transistor is shown in FIG.
As shown in (a), first, a metal film made of molybdenum-tantalum is formed on a glass insulating substrate 1 by a sputtering method, and this metal film is formed on a gate electrode 2 having a predetermined shape together with a gate line by a photolithography method. Form.
【００１７】つぎにこのゲート電極２の形成されたガラ
ス絶縁基板１を３５０℃に加熱し、シラン、アンモニ
ヤ、窒素からなるゲート絶縁層形成用ガスを導入して、
グロー放電によるプラズマＣＶＤ法により、上記ゲート
電極２を覆うようにガラス絶縁基板１上に膜厚０．３μ
m の窒化シリコン膜からなるゲート絶縁層３を形成す
る。さらにこの窒化シリコン膜成膜時のグロー放電を維
持させた状態で、導入ガスをゲート絶縁層形成用ガスか
ら水素ガスに切換え、グロー放電を持続させる。そして
シランガス（Ｓi Ｈ4 ）を導入して、膜厚０．０５μm
の非晶質シリコン（ａ−Ｓi ）膜からなる半導体層４を
形成する。Next, the glass insulating substrate 1 on which the gate electrode 2 is formed is heated to 350 ° C., and a gate insulating layer forming gas consisting of silane, ammonia and nitrogen is introduced,
A film thickness of 0.3 μm is formed on the glass insulating substrate 1 so as to cover the gate electrode 2 by plasma CVD method using glow discharge.
A gate insulating layer 3 made of a silicon nitride film of m 2 is formed. Further, while the glow discharge at the time of forming the silicon nitride film is maintained, the introduced gas is switched from the gate insulating layer forming gas to the hydrogen gas, and the glow discharge is continued. Then, silane gas (Si H 4 ) was introduced to obtain a film thickness of 0.05 μm.
The semiconductor layer 4 made of the amorphous silicon (a-Si) film is formed.
【００１８】さらに上記非晶質シリコン膜からなる半導
体層４形成時のグロー放電を維持させた状態で、シラ
ン、アンモニヤ、窒素からなる成膜ガスを導入し、グロ
ー放電によるプラズマＣＶＤ法により、膜厚０．３μm
の窒化シリコン膜１３を成膜する。そして同（ｂ）に示
すように、フォトリソグラフィ法によりその窒化シリコ
ン膜を所定形状の半導体保護層５に形成する。Further, while maintaining glow discharge at the time of forming the semiconductor layer 4 made of the amorphous silicon film, a film forming gas made of silane, ammonia and nitrogen is introduced, and the film is formed by a plasma CVD method by glow discharge. Thickness 0.3 μm
Then, the silicon nitride film 13 is formed. Then, as shown in (b), the silicon nitride film is formed on the semiconductor protective layer 5 having a predetermined shape by photolithography.
【００１９】つぎに上記半導体保護層５の形成されたガ
ラス絶縁基板１を後述するプラズマＣＶＤ装置の反応室
内に設置して加熱したのち、その反応室内に水素３００
sccmと、濃度１％のホスフィン（ＰＨ3 ）８００sccm
と、成膜時の総ガス流量に占める割合いが０．１〜５容
量％以下のモノシラン（シランガス）とを導入し、プラ
ズマ放電を励起させ、かつこのプラズマ放電を０．１秒
以上持続させ、このプラズマ放電中にモノシランの導入
量（流量）を増加して、プラズマＣＶＤ法により、同
（ｃ）に示すように、膜厚が約０．０５μm のｎ型半導
体層６を成膜する。このｎ型半導体層６の成膜は、後述
する第１ないし第３の成膜方法により、半導体層４側に
第１層６a を成膜し、ついでこの第１層６a 上に第２層
６b を積層する方法により成膜される。Next, the glass insulating substrate 1 on which the semiconductor protective layer 5 is formed is placed in a reaction chamber of a plasma CVD apparatus, which will be described later, and heated, and then hydrogen 300 is introduced into the reaction chamber.
sccm and phosphine (PH 3 ) 800 sccm with a concentration of 1%
And monosilane (silane gas), which accounts for 0.1 to 5% by volume of the total gas flow rate during film formation, to excite plasma discharge and to maintain this plasma discharge for 0.1 second or longer. Then, the introduction amount (flow rate) of monosilane is increased during this plasma discharge, and an n-type semiconductor layer 6 having a film thickness of about 0.05 μm is formed by the plasma CVD method as shown in (c). The n-type semiconductor layer 6 is formed by forming a first layer 6a on the semiconductor layer 4 side by the first to third film forming methods described later, and then forming a second layer 6b on the first layer 6a. Is formed by a method of laminating.
【００２０】上記ｎ型半導体層６を成膜したのち、上記
ゲート絶縁層３上に形成された半導体層４およびｎ型半
導体層６を、同（ｄ）に示すように、フォトリソグラフ
ィ法によりそれぞれ所定形状に形成する。After forming the n-type semiconductor layer 6, the semiconductor layer 4 and the n-type semiconductor layer 6 formed on the gate insulating layer 3 are respectively formed by photolithography as shown in (d). It is formed into a predetermined shape.
【００２１】その後、上記ｎ型半導体層６の形成された
ガラス絶縁基板１上に、スパッタ法によりＩＴＯの透明
導電膜を成膜し、フォトリソグラフィ法により、同
（ｂ）に示すように、ガラス絶縁基板１上に形成されて
いるゲート絶縁層３上の所定位置に透明導電膜からなる
所定形状の画素電極１０を形成する。After that, a transparent conductive film of ITO is formed on the glass insulating substrate 1 on which the n-type semiconductor layer 6 is formed by the sputtering method, and the glass is formed by the photolithography method as shown in FIG. A pixel electrode 10 of a predetermined shape made of a transparent conductive film is formed at a predetermined position on the gate insulating layer 3 formed on the insulating substrate 1.
【００２２】さらにこの画素電極１０の形成されたガラ
ス絶縁基板１上に、スパッタ法により、クロムまたはア
ルミニウムからなる金属膜を成膜する。そしてフォトリ
ソグラフィ法により、ｎ型半導体層６と画素電極１０と
を接続するドレイン電極８、およびｎ型半導体層６に接
続されたソース電極７を信号線とともに一体に形成す
る。その後、これらソース電極７およびドレイン電極８
の形成されたガラス絶縁基板１上に、プラズマＣＶＤ法
により窒化シリコン膜からなる絶縁保護層９を成膜する
ことにより製造される（図１参照）。Further, a metal film made of chromium or aluminum is formed on the glass insulating substrate 1 on which the pixel electrode 10 is formed by the sputtering method. Then, by photolithography, the drain electrode 8 connecting the n-type semiconductor layer 6 and the pixel electrode 10 and the source electrode 7 connected to the n-type semiconductor layer 6 are integrally formed together with the signal line. After that, these source electrode 7 and drain electrode 8
It is manufactured by forming an insulating protective layer 9 made of a silicon nitride film on the glass insulating substrate 1 on which the above is formed by a plasma CVD method (see FIG. 1).
【００２３】図３に上記ｎ型半導体層を形成するときに
使用されるプラズマＣＶＤ装置の構成を示す。このプラ
ズマＣＶＤ装置は、平行平板型のプラズマＣＶＤ装置で
あり、成膜をおこなう反応室１２内に直径が約１５cmの
円板状の高周波電極１３が設置され、この高周波電極１
３に対向して、その下部にほぼ同一直径の円板状の接地
電極１４が設置されている。この接地電極１４は、反応
室１２外に設けられた昇降装置１５により、高周波電極
１３との間隔を±０．０１mmの精度で任意に変更できる
ように上下動可能となっている。また反応室１２は、真
空排気装置１６に接続されている。さらに反応室１２外
には、高周波電極１３側から反応室１２内に成膜用ガス
を導入するための成膜用ガス導入装置１７が設けられて
いる。さらにまた接地電極１４には、この接地電極１４
上に載置された成膜用ガラス絶縁基板１を加熱するため
の抵抗加熱ヒータ１８が設けられている。なお、１９は
高周波電極１３に接続された高周波電源である。FIG. 3 shows the structure of a plasma CVD apparatus used when forming the n-type semiconductor layer. This plasma CVD apparatus is a parallel plate type plasma CVD apparatus, and a disk-shaped high frequency electrode 13 having a diameter of about 15 cm is installed in a reaction chamber 12 for film formation.
A disk-shaped ground electrode 14 having substantially the same diameter is installed in the lower part of the ground electrode 14 so as to face the same. The ground electrode 14 can be moved up and down by an elevating device 15 provided outside the reaction chamber 12 so that the distance between the ground electrode 14 and the high frequency electrode 13 can be arbitrarily changed with an accuracy of ± 0.01 mm. Further, the reaction chamber 12 is connected to a vacuum exhaust device 16. Further, outside the reaction chamber 12, a film-forming gas introduction device 17 for introducing a film-forming gas into the reaction chamber 12 from the high frequency electrode 13 side is provided. Furthermore, this ground electrode 14 is
A resistance heater 18 is provided for heating the glass insulating substrate 1 for film formation placed thereon. A high frequency power source 19 is connected to the high frequency electrode 13.
【００２４】前記ｎ型半導体層６を成膜する第１の方法
は、ゲート電極、ゲート絶縁層、半導体層、半導体保護
層の形成された成膜用ガラス絶縁基板１を上記プラズマ
ＣＶＤ装置の接地電極１４上に固定し、反応室１２内を
排気する。そして接地電極１４上に設けられた抵抗加熱
ヒータ１８により成膜用ガラス絶縁基板１を所定温度に
加熱したのち、反応室１２内に水素３００sccm、濃度１
％のホスフィン３００sccmおよびモノシラン２０sccmを
導入し、反応室１２内の成膜用ガス雰囲気の圧力を１３
３Paに調整する。そして高周波電極１３と接地電極１４
との間隔を３５mmに保ち、高周波電源１９から５０Ｗの
高周波電力を供給して、高周波電極１３と接地電極１４
間に放電を発生させる。この放電を５秒間維持して、そ
の間に上記ゲート電極、ゲート絶縁層、半導体層、半導
体保護層の形成された成膜用ガラス絶縁基板１上にｎ型
半導体層６の第１層６a を成膜する。ついで上記放電中
にモノシランを２００sccm導入し、高周波電源１９から
１００Ｗの高周波電力を供給して、上記第１層６a 上に
膜厚０．０５μm の第２層６b を成膜する（図２（ｃ）
参照）。The first method for forming the n-type semiconductor layer 6 is as follows. The glass insulating substrate 1 for film formation on which the gate electrode, the gate insulating layer, the semiconductor layer and the semiconductor protective layer are formed is grounded in the plasma CVD apparatus. It is fixed on the electrode 14 and the inside of the reaction chamber 12 is evacuated. Then, the glass insulating substrate 1 for film formation is heated to a predetermined temperature by a resistance heater 18 provided on the ground electrode 14, and then 300 sccm of hydrogen and a concentration of 1 are introduced into the reaction chamber 12.
% Phosphine (300 sccm) and monosilane (20 sccm) are introduced, and the pressure of the film forming gas atmosphere in the reaction chamber 12 is set to 13
Adjust to 3Pa. The high frequency electrode 13 and the ground electrode 14
The distance between the high frequency electrode 13 and the ground electrode 14 is kept at 35 mm by supplying high frequency power of 50 W from the high frequency power source 19.
A discharge is generated in the meantime. This discharge is maintained for 5 seconds, during which the first layer 6a of the n-type semiconductor layer 6 is formed on the film-forming glass insulating substrate 1 on which the gate electrode, the gate insulating layer, the semiconductor layer, and the semiconductor protective layer are formed. To film. Then, 200 sccm of monosilane was introduced into the discharge, and a high frequency power of 100 W was supplied from the high frequency power source 19 to form a second layer 6b having a thickness of 0.05 μm on the first layer 6a (FIG. 2 (c). )
reference).
【００２５】前記ｎ型半導体層６を成膜する第２の方法
として、ゲート電極、ゲート絶縁層、半導体層、半導体
保護層が形成された成膜用ガラス絶縁基板１を前記プラ
ズマＣＶＤ装置の接地電極１４上に固定し、反応室１２
内を排気する。そして接地電極１４上に設けられた抵抗
加熱ヒータ１８により所定温度に加熱したのち、その反
応室内に水素３００sccm、濃度１％のホスフィン８００
sccmおよび成膜時の総ガス流量に占める割合いが０．１
〜５容量％以下のモノシランを導入して、反応室内の成
膜用ガス雰囲気の圧力を１０６Pa以下の低圧に調整し、
プラズマ放電を励起させてｎ型半導体層６の第１層６a
を成膜する。その後、上記プラズマ放電中にモノシラン
の導入量を増加して、反応室１２内の成膜用ガス雰囲気
の圧力を１０６Pa以上の高圧に調整し、プラズマ放電に
より、上記第１層６a 上に第２層６b を成膜する（図２
（ｃ）参照）。このように成膜しても、所要のｎ型半導
体層を成膜することができる。As a second method of forming the n-type semiconductor layer 6, the film forming glass insulating substrate 1 on which the gate electrode, the gate insulating layer, the semiconductor layer, and the semiconductor protective layer are formed is grounded in the plasma CVD apparatus. The reaction chamber 12 is fixed on the electrode 14.
Exhaust the inside. Then, after being heated to a predetermined temperature by a resistance heater 18 provided on the ground electrode 14, phosphine 800 containing 300 sccm of hydrogen and 1% concentration in the reaction chamber.
The ratio of sccm and total gas flow rate during film formation is 0.1
By introducing monosilane of 5% by volume or less, the pressure of the film forming gas atmosphere in the reaction chamber is adjusted to a low pressure of 106 Pa or less,
The first layer 6a of the n-type semiconductor layer 6 is excited by exciting plasma discharge.
To form a film. Then, the amount of monosilane introduced during the plasma discharge is increased to adjust the pressure of the film forming gas atmosphere in the reaction chamber 12 to a high pressure of 106 Pa or higher, and the plasma discharge causes the second layer to be formed on the first layer 6a. Deposit layer 6b (Fig. 2
(See (c)). Even if the film is formed in this manner, the required n-type semiconductor layer can be formed.
【００２６】前記ｎ型半導体層６を成膜する第３の方法
として、ゲート電極、ゲート絶縁層、半導体層、半導体
保護層の形成された成膜用ガラス絶縁基板１を前記プラ
ズマＣＶＤ装置の接地電極１４上に固定し、所定温度に
加熱したのち、導入ガス量、導入ガス圧力、高周波電極
１３と接地電極１４の間隔、高周波電極１３に供給する
高周波電力などを調整して、第１層の成膜速度を１０nm
/min以下、第２層の成膜速度を１１nm/min以上として
も、所要のｎ型半導体層を成膜することができる。As a third method of forming the n-type semiconductor layer 6, the film forming glass insulating substrate 1 on which the gate electrode, the gate insulating layer, the semiconductor layer and the semiconductor protective layer are formed is grounded in the plasma CVD apparatus. After being fixed on the electrode 14 and heated to a predetermined temperature, the amount of introduced gas, the introduced gas pressure, the distance between the high-frequency electrode 13 and the ground electrode 14, the high-frequency power supplied to the high-frequency electrode 13, etc. are adjusted to adjust the first layer. Film formation speed is 10 nm
/ min or less, the required n-type semiconductor layer can be formed even if the film forming rate of the second layer is 11 nm / min or more.
【００２７】すなわち、成膜用ガラス絶縁基板１を反応
室１２内の接地電極１４に固定し、反応室１２内を排気
する。そして接地電極１４上に設けられた抵抗加熱ヒー
タ１８により所定温度に加熱したのち、水素３００scc
m、濃度１％のホスフィン８００sccmおよびモノシラン
２０sccmを反応室１２内に導入して、反応室１２内の成
膜用ガス雰囲気の圧力を８０Paに調整し、高周波電極１
３と接地電極１４の間隔を３５mmに保ち、高周波電源１
９から２０Ｗの電力を供給して、まず膜厚０．０１５μ
m の第１層６a を成膜速度８nm/minで成膜する。ついで
導入ガス流量を変えることなく、反応室１２内の成膜用
ガス雰囲気の圧力を１６０Paに調整し、放電を持続させ
て、膜厚０．０３５μm の第２層６b を成膜速度８０nm
/minで成膜する（図２（ｃ）参照）。このようにして
も、所要のｎ型半導体層を成膜することができる。That is, the glass insulating substrate 1 for film formation is fixed to the ground electrode 14 in the reaction chamber 12, and the inside of the reaction chamber 12 is evacuated. Then, after heating to a predetermined temperature by the resistance heater 18 provided on the ground electrode 14, 300 sccc of hydrogen
800 sccm of phosphine with a concentration of 1% and 20 sccm of monosilane were introduced into the reaction chamber 12, and the pressure of the gas atmosphere for film formation in the reaction chamber 12 was adjusted to 80 Pa.
Keep the distance between 3 and the ground electrode 14 at 35 mm, and use the high frequency power supply 1
Power of 9 to 20 W is applied first to a film thickness of 0.015 μ
The m first layer 6a is deposited at a deposition rate of 8 nm / min. Then, without changing the flow rate of the introduced gas, the pressure of the film forming gas atmosphere in the reaction chamber 12 was adjusted to 160 Pa and the discharge was continued to form the second layer 6b having a film thickness of 0.035 μm at the film forming rate of 80 nm.
A film is formed at a rate of / min (see FIG. 2C). Even in this case, the required n-type semiconductor layer can be formed.
【００２８】上記のように薄膜トランジスタのｎ型半導
体層を形成すると、従来おこなわれていたプラズマ処理
あるいは水素ガス雰囲気中でのプラズマ放電によるエッ
チングにくらべ、半導体層とｎ型半導体層との界面のメ
ージを軽減でき、半導体層４とｎ型半導体層６との界面
を最適な条件で良好に形成することができ、薄膜トラン
ジスタのソース電極７およびドレイン電極８と半導体層
４とのオーミックコンタクト特性を向上させることがで
きる。また第１のｎ型半導体層６a に対して第２のｎ型
半導体層６b を高速で成膜することにより、スループッ
トが従来の薄膜トランジスタと同等もしくはそれ以上に
向上する。その結果、この薄膜トランジスタを組込んだ
アクティブマトリックス型液晶表示装置は、きわめて良
好なスイッチング特性をもつものとなる。When the n-type semiconductor layer of the thin film transistor is formed as described above, the image of the interface between the semiconductor layer and the n-type semiconductor layer is different from the conventional plasma treatment or etching by plasma discharge in a hydrogen gas atmosphere. Can be reduced, the interface between the semiconductor layer 4 and the n-type semiconductor layer 6 can be formed favorably under optimum conditions, and ohmic contact characteristics between the source electrode 7 and the drain electrode 8 of the thin film transistor and the semiconductor layer 4 can be improved. be able to. By forming the second n-type semiconductor layer 6b at a high speed with respect to the first n-type semiconductor layer 6a, the throughput is improved to the same level as that of the conventional thin film transistor or more. As a result, an active matrix type liquid crystal display device incorporating this thin film transistor has extremely good switching characteristics.
【００２９】なお、上記実施例では、半導体層上に半導
体保護層を形成したが、この半導体保護層は、薄膜トラ
ンジスタの種類により不要の場合がある。本発明は、こ
のような薄膜トランジスタにも適用可能である。Although the semiconductor protective layer is formed on the semiconductor layer in the above embodiment, this semiconductor protective layer may be unnecessary depending on the type of thin film transistor. The present invention can be applied to such a thin film transistor.
【００３０】[0030]
【発明の効果】少なくともゲート電極、ゲート絶縁層、
半導体層、ｎ型半導体層、ソース電極およびドレイン電
極を有する薄膜トランジスタのｎ型半導体層をプラズマ
ＣＶＤ法により形成する薄膜トランジスタの製造方法に
おいて、はじめに水素とホスフィンと成膜時の総ガス流
量に占める割合いが０．１〜５容量％以下のモノシラン
とを含む成膜用ガス雰囲気中でプラズマ放電を励起させ
かつこのプラズマ放電を０．１秒以上持続させてｎ型半
導体層の第１層を成膜し、ついでこのプラズマ放電中に
モノシランを導入してｎ型半導体層の第２層を成膜する
か、またはｎ型半導体層の第１層を成膜するときの成膜
用ガス雰囲気の圧力を第２層を成膜するときの成膜用ガ
ス雰囲気の圧力よりも低くするか、またはその第１層の
成膜速度を第２層の成膜速度よりも遅くすると、半導体
層とその上に形成されるｎ型半導体層との界面を良好に
することができ、均一な特性を有する高品質な薄膜トラ
ンジスタを製造することができる。その結果、アクティ
ブマトリックス型液晶表示装置に組込んで良好なスイッ
チング特性が得られる。At least a gate electrode, a gate insulating layer,
In a method of manufacturing a thin film transistor in which an n type semiconductor layer of a thin film transistor having a semiconductor layer, an n type semiconductor layer, a source electrode and a drain electrode is formed by a plasma CVD method, first, hydrogen, phosphine, and the proportion of the total gas flow rate during film formation Is excited in a film forming gas atmosphere containing 0.1 to 5% by volume or less of monosilane, and the plasma discharge is continued for 0.1 second or more to form the first layer of the n-type semiconductor layer. Then, monosilane is introduced into this plasma discharge to form the second layer of the n-type semiconductor layer, or the pressure of the film-forming gas atmosphere at the time of forming the first layer of the n-type semiconductor layer is controlled. When the pressure of the gas atmosphere for forming the second layer is set lower than that of the film forming gas atmosphere or the film forming rate of the first layer is set lower than that of the second layer, the semiconductor layer and Formation Are the interface between the n-type semiconductor layer can be improved, it is possible to produce a high quality thin film transistor having uniform properties. As a result, good switching characteristics can be obtained by incorporating it in an active matrix type liquid crystal display device.
【図１】この発明の一実施例に係る薄膜トランジスタの
構成を示す図である。FIG. 1 is a diagram showing a configuration of a thin film transistor according to an embodiment of the present invention.
【図２】図２（ａ）ないし（ｅ）はそれぞれ上記薄膜ト
ランジスタの製造方法を説明するための図である。FIGS. 2A to 2E are views for explaining a method of manufacturing the thin film transistor.
【図３】図３はそれぞれ上記薄膜トランジスタのｎ型半
導体層の成膜に使用されるプラズマＣＶＤ装置の構成を
示す図である。FIG. 3 is a diagram showing a configuration of a plasma CVD apparatus used for forming an n-type semiconductor layer of the thin film transistor.
１…ガラス絶縁基板 ２…ゲート電極 ３…ゲート絶縁層 ４…半導体層 ５…半導体保護層 ６…ｎ型半導体層 ６a …ｎ型半導体層の第１層 ６b …ｎ型半導体層の第２層 ７…ソース電極 ８…ドレイン電極 ９…絶縁保護層 １０…画素電極 １２…反応室 １３…高周波電極 １４…接地電極 １５…昇降装置 １６…真空排気装置 １７…成膜用ガス導入装置 １８…抵抗加熱ヒータ １９…高周波電源 DESCRIPTION OF SYMBOLS 1 ... Glass insulating substrate 2 ... Gate electrode 3 ... Gate insulating layer 4 ... Semiconductor layer 5 ... Semiconductor protective layer 6 ... N-type semiconductor layer 6a ... 1st layer of n-type semiconductor layer 6b ... 2nd layer of n-type semiconductor layer 7 Source electrode 8 Drain electrode 9 Insulation protection layer 10 Pixel electrode 12 Reaction chamber 13 High frequency electrode 14 Ground electrode 15 Elevating device 16 Vacuum exhaust device 17 Film forming gas introducing device 18 Resistance heating heater 19 ... High frequency power supply
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/205 21/31 Continuation of front page (51) Int.Cl. 6 Identification number Office reference number FI technical display area H01L 21/205 21/31
Claims (3)
半導体層、ｎ型半導体層、ソース電極およびドレイン電
極を有する薄膜トランジスタの上記ｎ型半導体層をプラ
ズマＣＶＤ法により形成する薄膜トランジスタの製造方
法において、 はじめに水素とホスフィンと成膜時の総ガス流量に占め
る割合いが０．１〜５容量％以下のモノシランとを含む
成膜用ガス雰囲気中でプラズマ放電を励起させ、このプ
ラズマ放電を０．１秒以上持続させて上記ｎ型半導体層
の第１層を成膜し、ついでこのプラズマ放電中にモノシ
ランを導入して上記ｎ型半導体層の第２層を成膜するこ
とを特徴とする薄膜トランジスタの製造方法。1. At least a gate electrode, a gate insulating layer,
In a method of manufacturing a thin film transistor having a semiconductor layer, an n-type semiconductor layer, and a thin film transistor having a source electrode and a drain electrode, in which the n-type semiconductor layer is formed by a plasma CVD method, hydrogen, phosphine, and a proportion of the total gas flow rate during film formation are first described. However, plasma discharge is excited in a film forming gas atmosphere containing 0.1 to 5% by volume or less of monosilane, and this plasma discharge is continued for 0.1 second or more to form the first layer of the n-type semiconductor layer. A method of manufacturing a thin film transistor, which comprises forming a film and then introducing monosilane into the plasma discharge to form a second layer of the n-type semiconductor layer.
成膜用ガス雰囲気の圧力を第２層を成膜するときの成膜
用ガス雰囲気の圧力よりも低くしたことを特徴とする請
求項１記載の薄膜トランジスタの製造方法。2. The pressure of the film forming gas atmosphere when forming the first layer of the n-type semiconductor layer is lower than the pressure of the film forming gas atmosphere when forming the second layer. The method of manufacturing a thin film transistor according to claim 1.
層の成膜速度よりも遅くしたことを特徴とする請求項１
記載の薄膜トランジスタの製造方法。3. The deposition rate of the first layer of the n-type semiconductor layer is set to the second
The layer forming speed is slower than the layer forming speed.
A method for manufacturing the thin film transistor described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5927094A JPH07273336A (en) | 1994-03-29 | 1994-03-29 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5927094A JPH07273336A (en) | 1994-03-29 | 1994-03-29 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07273336A true JPH07273336A (en) | 1995-10-20 |
Family
ID=13108522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5927094A Pending JPH07273336A (en) | 1994-03-29 | 1994-03-29 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07273336A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10333181A (en) * | 1997-05-30 | 1998-12-18 | Nec Corp | Active matrix type liquid crystal display device and its manufacture |
| KR100674238B1 (en) * | 2000-12-30 | 2007-01-25 | 비오이 하이디스 테크놀로지 주식회사 | Manufacturing method of high mobility self-aligning TF |
-
1994
- 1994-03-29 JP JP5927094A patent/JPH07273336A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10333181A (en) * | 1997-05-30 | 1998-12-18 | Nec Corp | Active matrix type liquid crystal display device and its manufacture |
| KR100674238B1 (en) * | 2000-12-30 | 2007-01-25 | 비오이 하이디스 테크놀로지 주식회사 | Manufacturing method of high mobility self-aligning TF |
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