JP3281777B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, in particular, to a liquid crystal display (LCD).
Thin film transistor (TFT)
nsistor).

[0002]

2. Description of the Related Art LCDs have advantages such as small size, thin shape, and low power consumption, and are being put to practical use in fields such as OA equipment and AV equipment. In particular, an active matrix type using a TFT as a switching element can perform static driving with a duty ratio of 100% in principle in a multiplex manner, and is used for a large-screen, high-definition moving image display.

An active matrix LCD has a substrate in which TFTs are connected to display electrodes arranged in a matrix (TFF substrate) and a substrate having a common electrode (counter substrate).
Are bonded together with a liquid crystal interposed therebetween. The opposing portion between the display electrode and the common electrode is a pixel capacitance using a liquid crystal as a dielectric layer, and is selected line by line by a TFT and a voltage is applied. The voltage applied to the pixel capacitance is O
The data is held for one field period by the FF resistor. The liquid crystal has electro-optical anisotropy, and the amount of transmitted light is finely adjusted according to the intensity of the electric field formed by the pixel capacitance. In this way, the distribution of light and dark whose transmittance is controlled for each pixel is visually recognized as a desired display image.

In recent years, a driving circuit integrated type LCD in which a matrix pixel portion and a peripheral driving circuit portion are formed on the same substrate by using polycrystalline silicon (poly-Si) as a channel layer of a TFT has been developed. In general,
Poly-Si has higher mobility than amorphous silicon (a-Si). Therefore, the size of the TFT is reduced, and high definition is realized. Further, since high-speed operation is achieved by miniaturization by the gate self-aligned structure and reduction of parasitic capacitance, a high-speed driving circuit is formed by forming an electrically complementary connection structure of n-ch TFT and p-ch TFT, that is, CMOS. be able to. As described above, by integrally forming the driving circuit portion and the matrix pixel portion on the same substrate, reduction in manufacturing cost and downsizing of the LCD module can be realized.

FIG. 14 shows such an LCD integrated with a driving circuit.
Is shown. A portion surrounded by a dotted line in the center is a matrix pixel portion, which includes a gate line (G1, G2,..., Gm) for controlling ON / OFF of a TFT and a drain line (D1, D2,...) For pixel signals. Dn) are arranged crossing each other. At each intersection, a TFT and a display electrode (not shown) connected to the TFT are formed. A gate driver (GD) for selecting a gate line (G1, G2,..., Gm) is disposed on the left and right of the pixel unit. ), The drain lines (D1, D1)
, Dn), a drain driver (DD) for applying a pixel signal voltage is arranged. The drain driver (DD) mainly includes a shift register circuit and a sampling circuit, and in some cases, a hold capacitor, and the gate driver (GD) mainly includes a shift register. Outside these gate driver (GD) and drain driver (DD), supply pads for external input signals such as a clock signal, a start pulse, a video signal, and a power supply voltage are formed.

FIG. 15 shows the structure of such a p-Si TFT. An island-patterned p-Si (101) is formed on a substrate (100) of glass or the like.
A gate electrode (103) is opposed to a gate insulating film (102) such as O2. Gate electrode (10
3) is formed of, for example, a doped poly-Si and a polycide layer of silicide.

The p-Si (101) has a self-aligned structure using the gate electrode (103) as a mask, and has an n-type heavily doped source / drain region (1).
01S, 101D) and a non-doped or p-type doped channel region (101N) immediately below the gate electrode (103), and between the channel region (101N) and the source and drain regions (101S, 101D). Is an n-type lightly doped LD region (101)
L) is formed.

In the pixel portion, the gate electrode (103) is formed integrally with the gate line which is a scanning line, and in the drive circuit portion, it is connected to a connection having a complementary structure. On the gate electrode (103), an injection stopper (104) for preventing counter doping during the process, and a gate electrode (10).
3) Spacers (105) are formed on the side walls of the injection stopper (104). These p-Si (10
1) and an entire surface covering the gate electrode (103) and its line is covered with a first interlayer insulating film (106) such as SiO2, and Ti / Al is formed on the first interlayer insulating film (106).
A drain electrode (107) and a source electrode (108) made of Si or the like are provided, and are provided through contact holes (CT4, CT5) opened in the gate insulating film (102) and the first interlayer insulating film (106). Each is connected to the drain / source region (101D, 101S). In the pixel portion, the drain electrode (107) is integrated with the drain line which is a signal line. In the drive circuit portion, the drain electrode (107) and the source electrode (108).
Is extended to the connection of the complementary structure. A second interlayer insulating film (109) having a flattening action such as SOG (Spin On Glass) is formed on the entire surface covering the drain electrode (107) and the source electrode (108). In the pixel portion, ITO (in) is formed on the second interlayer insulating film (109).
A display electrode made of dium tin oxide) is formed, and by forming a contact hole in the second interlayer insulating film (109) on the source electrode (108), the source electrode (1) is formed.
08).

[0009] As shown here, the drain region (10
1S) and the channel region (101N), and between the source region (101S) and the channel region (101N) with the low concentration LD region (101L) interposed therebetween.
Generally called LDD (lightlydoped drain), the strong electric field at the end of the channel region (101N) is reduced, so that the acceleration of carriers is suppressed and the withstand voltage is high. Since the LD region (101L) is also interposed as a resistor, the transconductance is reduced.
In the pixel portion, the OFF current can be suppressed, and the voltage holding ratio can be increased. On the other hand, since a sufficiently high ON current value is originally obtained with a p-Si TFT, an ON / OFF ratio can be improved by adopting an LDD structure.

[0010] Such a TFT having the LDD structure is manufactured as follows. First, a glass substrate (10
0) on the amorphous silicon (a) by CVD using silane SiH4 or disilane Si2H6 as a material gas.
-Si), and the a-Si is heated to 200 to 4
Polycrystallized by excimer laser annealing at 00 ° C., preferably 400 ° C. to form polysilicon (p-Si) (10
What was set to 1) was a reactive ion etch, that is, RIE.
(Reactive ion etch) to form an island layer of the TFT portion. By using a high heat-resistant quartz glass or the like as the substrate (100), 9
A process including a high-temperature processing step of 00 ° C. or higher is generally called a high-temperature process.
Is a method of solid layer growth or rapid thermal annealing (RTA).
May be polycrystallized. Also, directly high-temperature CVD
May be formed.

If necessary, the n-ch TFT region of the driver is p-type channel-doped.
2 is formed by CVD to form a gate insulating film (102). Then, 600 to 650 using SiH4 as a material gas.
Poly-Si is deposited by CVD at a temperature of .degree. C., phosphorus ions are implanted to reduce the resistance, and then tungsten silicide (WSi) is sputtered.
Then, the polycide layer of WSi and WSi is etched in the same pattern by RIE to form a gate line connecting the gate electrode (103) and the pixel unit in a row, and a connection in the drive circuit unit. poly-Si
A may be formed by excimer laser annealing or rapid thermal annealing of CVD-formed a-Si, and the resistance may be reduced by a diffusion process using POCl3.

Using the gate electrode (103) as a mask, 1 × 1
Phosphorus ions are implanted at a low dose of 0 ↑ 11 to 5 × 10 ↑ 13 cm ↑ -2, and the source and drain regions (101S, 1
01D) and the LD region (101L) are lightly doped. Subsequently, after forming a masking resist larger than the gate electrode (103), ion implantation of phosphorus is performed again by 1 ×.
10 ↑ 14 to 1 × 10 ↑ 16 cm ↑ -2, preferably 7 × 10
A high dose of {14 cm} −2 is used to perform high concentration doping, and the source region (101S) and the drain region (101
D) is formed. Thus, the source and drain regions (101S, 101D) and the channel region (10
1N) and an LDD structure in which a low concentration LD region (101L) is interposed.

[0013] A doped region of p-Si (101S, 1) is formed by lamp annealing or excimer laser annealing.
01D, 101L, and 103), a first interlayer insulating film (106) is formed by depositing SiO2 to a thickness of 3000 to 5000 ° by CVD and annealing. Then, after performing H2 annealing for the purpose of terminating dangling bonds in silicon, the gate insulating film (102) and the first interlayer insulating film (106) on the drain and source regions (101D, 101S) are subjected to RIE. Then, contact holes (CT4, CT5) are formed. And Ti
/ AlSi is sputtered and patterned by RIE to form a drain electrode (107) and a source electrode (108), and further a drain electrode (10
7) are formed for one row, a drain line, a complementary connection of the drive circuit portion, a lead line, and the like are formed.
The drain electrode (107) and the source electrode (108) are connected to the drain and source regions (101D, 101S) via contact holes (CT4, CT5), respectively.

Again, after performing H plasma treatment for terminating dangling bonds in silicon, an SOG film, that is, a planarization insulating film mainly composed of an SiO 2 film formed by spin coating and firing is laminated. Second interlayer insulating film (109)
Is formed. Then, by RIE, in the second interlayer insulating film (109) on the source electrode (108) of the pixel portion,
A contact hole is formed, ITO is formed by sputtering, and this is patterned by RIE to form a display electrode in a pixel portion, and a source electrode (10
8).

In the above steps, p-Si (10
The ion implantation for forming the LDD structure of 1) and reducing the resistance of the gate electrode 103 is performed as follows. First, FIG. 16 is a schematic diagram of an ion implantation apparatus. (50) is an ion source, (51) is an extraction and acceleration system, (52) is a mass analysis system, (53) is an acceleration system,
(54) is a vertical scanning system, (55) is a horizontal scanning system,
(56) is a target system. The ion source (50)
An anode and a cathode are provided in a discharge tube provided with a gas inlet, and a plasma discharge is generated. For example, when performing phosphorus ion implantation, a source gas such as phosphine PH3 or phosphorus pentafluoride PF5 is introduced, and when performing boron ion implantation, a source gas such as boron trifluoride BF3 or diborane B2H6 is introduced. I do. This is ionized by discharge plasma, and P +, H +, H2 + or B +, F +, BF +,
Generates ions such as BF2 +. These generated ions are further extracted to the outside by an extraction electrode arranged at the exit of the extraction system (51), accelerated if necessary, and turned into an ion beam. This ion beam enters the mass spectrometry system (52), where only necessary ions pass. The mass spectrometry system (52) passes an ion beam through a fan-shaped uniform magnetic field, and utilizes the fact that the orbital radius of ions moving in the magnetic field varies depending on the mass, and passes only ions of a specific mass, that is, ions of a specific element. It is. In particular, by providing a slit at the outlet, unnecessary ions are completely removed, and the analysis effect is further enhanced. The ion beam analyzed in this manner is accelerated by an acceleration system (53) comprising a single or multi-stage acceleration tube, and a desired implantation energy is applied. The ion beam is further scanned by a vertical and horizontal scanning system (54, 5) comprising a pair of deflection electrodes.
5) to irradiate the target system (56). In the target system (56), various measures are taken for facilitating the attachment / detachment and transportation of the stage, which supports the target, that is, the predetermined electrode substrate, and the electrode substrate. In particular, the stage is XY
It is also conceivable to adopt a configuration in which the scanning system (54, 55) can be slightly moved in the direction to reduce the load on the device of the scanning system (54, 55).

Such an ion implantation method is particularly called an ion implantation method because only a specific ion to be doped is accelerated and implanted directly into a control layer.

[0017]

In the ion implantation method described above, the controllability is extremely high as compared with the thermal diffusion method and the like, and the ion range is controlled by adjusting the amount of source gas, extraction voltage, and acceleration voltage. The distance is controlled, and the doping amount and the doping depth can be finely adjusted. In particular, the lateral diffusion length of the implanted impurity is small, and the doping region can be accurately defined by the mask pattern. Therefore, by adopting the gate self-aligned structure using the self-alignment technique as described above, the stability and high speed of the transistor can be achieved.

However, on the other hand, there are the following disadvantages. First, as a defect in characteristics, a large amount of lattice defects may occur during ion implantation. Although such lattice defects depend on implantation conditions, for example, implantation of boron B causes 100 to 1000 lattice defects per ion. In particular,
When implanting into a polysilicon film, an amorphous layer, that is, an amorphous silicon layer is formed near the surface, and the sheet resistance increases. Such lattice defects are recovered by annealing. However, in a so-called low-temperature process of forming a TFT on an inexpensive glass substrate by setting the entire heat treatment process to 600 ° C. or lower, such recovery of the crystallinity is prevented. It may not be performed sufficiently and may adversely affect the characteristics.

Another disadvantage in terms of cost is that the throughput is low. That is, since the impurity is uniformly implanted on the substrate by scanning with the focused ion beam, it is usually necessary to reach a predetermined implantation amount for one substrate due to limitations on the spot diameter, beam current, and the like. It takes several minutes to several tens of minutes, the throughput is as low as 40 sheets / day, and furthermore, it gets worse as the substrate area increases.
Further, in terms of the apparatus, the mass spectrometer is large-scale, and the inner wall surface is damaged by unnecessary ions.

[0020]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and a low impurity concentration is obtained by implanting a first impurity having a predetermined conductivity type into a predetermined region of a semiconductor layer at a low dose. A first step of forming a region, and implanting a second impurity having the same conductivity type as the first impurity at a high dose except for a part of the low-concentration region. Forming a high-concentration region in contact with a part of the semiconductor device.
In the step, ions are extracted from the raw material containing the first impurity element by discharge and a high electric field, ions of the first impurity are extracted from these ions by mass spectrometry, and the ions of the first impurity are transferred to the semiconductor layer. And the second step is a step of extracting ions by ion discharge and a high electric field from a raw material containing a second impurity element, and injecting these ions into the semiconductor layer.

In this configuration, the ion implantation of the first impurity having a low dose is performed by using an ion implantation method using mass spectrometry, whereby the controllability of the low-concentration doping region is improved and the ion implantation of a high dose is performed. In the ion implantation of the second impurity, a large amount of impurity ions can be implanted by ion implantation without using mass spectrometry. Thereby, the fine adjustment and uniformity of the doping amount required for the ion implantation of the first impurity are satisfied, and the throughput of the ion implantation of the second impurity can be increased by a large amount of implantation.

Particularly, the raw material containing the second impurity element is configured to be a mixed gas of a hydrogen compound of the second impurity element and hydrogen. With this configuration, in the formation of the high-concentration region, hydrogen ions are implanted into the semiconductor layer together with impurity ions having a predetermined conductivity type, and the recrystallization phenomenon is promoted simultaneously with the lattice defect. For this reason, damage due to ion implantation is minimized, and sufficient crystallinity can be recovered even by heat treatment at a relatively low temperature.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an ion implantation method used in a method of manufacturing a semiconductor device according to the present invention will be described. In this method, unlike the ion implantation method described in the conventional example, the ion implantation is performed once in a large area without performing mass analysis, and is also called an ion shower.

FIG. 1 is a schematic view of an ion implantation apparatus for performing such an ion shower. (1) is a plasma source, (2) is a gas inlet, (3) is an RF high frequency power supply,
(4) is an extraction electrode, (5) is an acceleration electrode, (6) is a suppression electrode, (7) is a ground electrode, and (8) is a stage for supporting an electrode substrate into which ions are to be implanted. The source gas is introduced from the gas inlet (2) to the plasma source (1).
The source gas is phosphine PH3 diluted with hydrogen for n-type doping, and B2H6 diluted with hydrogen for p-type doping.
Are used. These source gases are 13.56M
Hz, and is ionized by high frequency discharge of P +, H +, H2
+, B +, etc. are generated. These ions are 10 keV
Is extracted from the extraction electrode (4) by the extraction voltage and reaches the acceleration electrode (5). Further, it is accelerated from the accelerating electrode (5) to the suppressing electrode (6) and the ground electrode (7) by the accelerating voltage of 90 keV, extracted as an ion beam, and irradiated to the target on the stage (8). Each electrode (4, 5, 6, 7) has thousands of fine holes through which ions pass, and a uniform ion beam is obtained by superimposing the ion beams extracted from these holes. Can be Further, the voltage of the suppression electrode (6) is set lower than the voltage of the ground electrode (7) so that a highly uniform ion beam can be obtained.

Such an ion shower method or an ion shower apparatus has the following advantages. First, since the ion beam is obtained as a large current of the same size as the plasma source, the beam diameter can be increased to 500 mm or more, and the uniformity of the beam current can be improved by optimally setting the acceleration voltage and the extraction voltage. It can be suppressed to ± 10% or less. For this reason, up to 500 mm x 500 mm
Substrates can be processed at one time, scanning with a beam line is not required, the time required for processing one substrate is reduced to 1 to 2 minutes, and the throughput is greatly increased as compared with the ion implantation method.

In addition, since the method is such that phosphorus ions or boron ions are implanted together with hydrogen ions without performing mass spectrometry, the implantation is performed while compensating for implantation damage.
Therefore, at the time of implantation into the polysilicon film, the doping is performed while recrystallizing the amorphous layer formed on the surface, so that the activation annealing temperature can be lowered or becomes unnecessary.

Further, since the mass spectrometry system and the scanning system are not required, the apparatus is simplified, the size can be easily increased, and the area and the throughput can be increased. On the other hand, the ion shower method has a drawback that injection controllability at a low dose is low. For this reason, in the method of manufacturing a semiconductor device of the present invention, doping with a low dose is performed with high accuracy by the conventional ion implantation method, and doping with a high dose is performed with high throughput by the ion shower method.

FIG. 2 shows the relationship between the dose and the sheet resistance in the low dose range in the ion implantation into the polysilicon film. ◆ is the sheet resistance value at ion implantation, and Δ is the sheet resistance value at ion shower. As can be seen from the figure, the sheet resistance is very stable in the ion implantation, while the variation is somewhat noticeable in the ion shower. That is, in low dose ion implantation,
It can be seen that ion implantation of impurities is performed accurately and uniformly in ion implantation, but controllability is somewhat poor in ion showering.

FIG. 3 shows a TFT having an LDD structure.
Regarding the presence or absence of the LD region, transfer characteristics, that is, gate voltage (V)
-Shows a difference in drain current (Id) characteristics. The solid line in the figure is the characteristic curve of the TFT having the LD region, and the broken line is the characteristic curve of the TFT without the LD region. The drain current value I
d is indicated by the standardized unit. Usually p-SiTF
The LDD structure in the TLCD has a large purpose of suppressing a leak current in a pixel portion. That is, while the mobility of the p-Si layer is sufficiently high, the OFF current due to the p-type conduction poses a problem.
Reduce F current.

Such an LD region is formed by ion implantation of a low-dose impurity. However, when an ion shower is used, the amount of impurity implantation varies as shown in FIG. In some cases, the implantation of the region becomes excessive and the resistance of the LD region cannot be sufficiently obtained. When the doping amount of the LD region becomes excessive as described above, the resistance decreases, the suppression of the OFF current becomes ineffective, and the OFF current increases as shown by the broken line in FIG. When the OFF current increases, problems such as a decrease in the voltage holding ratio and a decrease in the contrast ratio occur.

For this reason, according to the present invention, a conventional ion implantation method is used for channel doping of the LD region or the driver portion which requires the control of the implantation amount at a low dose, and other source and drain regions or silicon regions are used. An ion shower is used for a region formed by high-dose implantation such as reduction in resistance of a gate. Hereinafter, an embodiment of a method for manufacturing a p-Si TFT according to the gist of the present invention will be described. 4 to 13 are process cross-sectional views showing the manufacturing process.

First, in FIG. 4, silane SiH4 or disilane Si2H is placed on a glass substrate (10).
Amorphous silicon (a-Si) by CVD using 6 as a material gas to 300-1000Å, preferably 500-
This a-Si is heated to a substrate thickness of
It is polycrystallized by excimer laser annealing at 0 ° C. to obtain polysilicon (p-Si) (11). This is called a reactive ion etch, that is, RIE (reactive ion etch).
To form an island layer in the TFT portion.

Subsequently, as shown in FIG. 5, SiO 2 is laminated to a thickness of about 1000 ° by low pressure CVD at 400 ° C. to form a gate insulating film (12). Next, as shown in FIG. 6, a 2000- [mu] m thick poly-Si (1) was formed thereon by high-temperature CVD at 580 [deg.] C. using SiH4 as a material gas.
3a) is stacked and the resistance is reduced by performing an ion shower of phosphorus, and then tungsten silicide (WSi) (13
b) is sputtered to a thickness of 500-1500 °, preferably 1000 °. Continuously, normal pressure CV of 410 ° C
D to make the SiO2 1000-2000%, preferably 1
After laminating to a thickness of 500 mm, these SiO2 and p
The poly-silicide layer of poly-Si and WSi is etched in the same pattern by RIE, and the gate electrode (13) and a gate line connecting these to each other in a row in the pixel portion, and the gate electrode (13) and the gate line Form a coated injection stopper (14).

As shown in FIG. 7, normal pressure C at 410 ° C.
By depositing SiO2 by VD and etching it by RIE, sidewall spacers (15) are formed on the gate electrode (13) and the injection stopper (14) thereon. Next, as shown in FIG. 8, a first ion implantation of an n-type impurity such as phosphorus (P) is performed by ion implantation using the gate electrode (13) and the side wall spacer (15) as a mask, with an acceleration voltage of 80 keV and a dose of It is performed in an amount of 3 × 10 13 / cm 2. As a result, the source and drain regions (11S, 11D) and the LD region (11) have a self-aligned relationship using the gate electrode (13) and the side wall spacer (14).
The region to be L) is doped at a low concentration (n−). At this time, immediately below the gate electrode (13) is a non-doped channel region (11N). The spacer (1
5) In this step, in order to secure a margin for lateral diffusion due to annealing after phosphorus ion implantation, the function of lowering the impurity concentration at the end of the channel region to reduce the drain electric field and improve the breakdown voltage is provided. are doing.

Subsequently, as shown in FIG. 9, the gate electrode (1
3) A resist (R) having a larger size than that of (3) is coated, and using this as a mask, a second ion implantation of phosphorus (P) is performed by ion shower using an acceleration voltage of 90 keV and an extraction voltage of 10
This is performed at a keV and a dose of 1 × 10 15 / cm 2. As a result, the region immediately below the resist (R) is formed as the LD region (11L) while being kept in the low concentration doping region (n−), and the outside of the LD region (11L) is heavily doped. Source region (1
1S) and a drain region (11D) are formed.

Here, in the doping by the ion shower, a throughput of 200 wafers / day is achieved, which is much higher than the conventional 40 wafers / day. After stripping the resist, the p-Si doped regions (11L, 11S, 11L) are formed by lamp annealing or excimer laser annealing.
After activating D, 13a), as shown in FIG.
2000 ° of SiO 2 is formed by atmospheric pressure CVD at 0 ° C.
After annealing at 600 ° C., further, SiO 2 was formed to a thickness of 3000 ° by plasma CVD at 300 ° C.
A first interlayer insulating film (16) is formed. Then, H2 annealing at 450 ° C. is performed for the purpose of terminating dangling bonds in silicon, and then the drain and source regions (1) are formed by RIE.
1D, 11S) in the gate insulating film (12) and the first interlayer insulating film (16).
2) is formed.

Then, as shown in FIG. 11, Ti / AlS
i is laminated by sputtering to a thickness of 7000 °, and is patterned by RIE to form a drain electrode (17) and a source electrode (18). The drain electrode and the source electrode are contact holes (CT1, CT2), respectively. Connected to areas (11D, 11S). Again, after performing H plasma treatment at 390 ° C. for terminating dangling bonds in silicon, as shown in FIG.
D, after stacking SiO2 to a thickness of 2000 mm,
SOG film, that is, S formed by spin coating and baking
After covering and flattening the iO2 film, a second interlayer insulating film (19) is completed by laminating SiO2 to a thickness of 1000 DEG by CVD at 410.degree. And RIE
Thereby, a contact hole (CT3) is formed in the second interlayer insulating film (19).

Finally, as shown in FIG. 13, an ITO film is formed by sputtering, which is patterned by RIE to form a display electrode (20), and a source electrode (1).
8), the TFT substrate is completed.

[0039]

As is clear from the above description, according to the present invention, in the method of manufacturing the TFT having the LDD structure, the controllability is improved by using the ion implantation method for forming the low concentration region, and the decrease in the throughput is suppressed. In addition, by using the ion implantation method to form the high concentration region, the throughput could be greatly increased. This makes it possible to manufacture a TFT having good characteristics at low cost.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of an ion shower device used in the present invention.

FIG. 2 is a diagram illustrating a relationship between a dose amount and a sheet resistance value by an ion implantation method and an ion shower method.

FIG. 3 shows transfer characteristics of a TFT with respect to the presence or absence of an LD region.

FIG. 4 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 5 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 6 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 7 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 8 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 9 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 10 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 11 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 12 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 13 is a process sectional view illustrating the method for manufacturing the TFT according to the embodiment of the present invention.

FIG. 14 is a configuration diagram of a liquid crystal display device.

FIG. 15 is a sectional view of a TFT.

FIG. 16 is a schematic view of an ion implantation apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Plasma source 2 Gas inlet 3 High frequency power supply 4 Extraction electrode 5 Acceleration voltage 6 Suppression electrode 7 Ground electrode 8 Stage 10 Substrate 11 p-Si 12 Gate insulating film 13 Gate electrode 14 Injection stopper 15 Side wall spacer 16 First interlayer insulating film Reference Signs List 17 source electrode 18 drain electrode 19 second interlayer insulating film 20 display electrode CT1, CT2, CT3 contact hole R resist

──────────────────────────────────────────────────続 き Continued on the front page (72) Koji Suzuki 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Masaru Takeuchi 2-5-5 Keihanhondori, Moriguchi-shi, Osaka No. 5 Inside Sanyo Electric Co., Ltd. (56) References JP-A-4-320345 (JP, A) JP-A-8-51207 (JP, A) JP-A-8-1224872 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 21/336 G02F 1/1368 H01L 21/265 H01L 29/786

Claims (2)

(57) [Claims] 1. A first step of forming a low-concentration region by implanting a first impurity having a predetermined conductivity type into a predetermined region of a semiconductor layer at a low dose, and a part of the low-concentration region. A second step of forming a high-concentration region in contact with a part of the low-concentration region by implanting a second impurity having the same conductivity type as the first impurity at a high dose except for the first impurity. In the method for manufacturing a semiconductor device having the first step, the first step is to extract ions by a discharge and a high electric field from a raw material containing a first impurity element, to extract ions of the first impurity by mass spectrometry from these ions, The first step is a step of implanting ions of the first impurity into the semiconductor layer, and the second step is to extract ions from a raw material containing a second impurity element by electric discharge and electric field, and remove all these ions from the semiconductor. The method of manufacturing a semiconductor device which is a step of injecting into. 2. The method according to claim 1, wherein the raw material containing the second impurity element is a mixed gas of a hydrogen compound of the second impurity element and hydrogen.