KR100667898B1 - Nonvolatile Semiconductor Memory Device - Google Patents

Abstract

The present invention discloses a technique for implementing an MTP (Multi-Time Programmable) cell that can be programmed and erased many times by using a semiconductor process for manufacturing an embedded high voltage device without any additional process. To this end, a plurality of word lines; A plurality of bit lines; Common source line; And a plurality of unit cells, the unit cell comprising: a selection transistor controlled by a selection voltage applied to a selection line to selectively transfer a voltage applied to a word line; A control node for injecting or releasing electrons by capacitance coupling to the floating gate in accordance with the voltage delivered through the selection transistor; And a sense transistor for detecting a cell current according to the charge potential of the floating gate.

Description

Nonvolatile semiconductor memory device

1A and 1B are cross-sectional views showing MTP cells according to the prior art.

2 is a graph illustrating a relationship between a control gate voltage Vcg and a cell current of an MTP cell according to the prior art.

3A is a circuit diagram illustrating a cell array according to the prior art.

3B is a layout diagram illustrating a cell array according to the related art.

FIG. 3C is a circuit diagram illustrating an operation of programming A cell in the cell array shown in FIG. 3A.

FIG. 3D is a graph illustrating a program time for an MTP cell according to the related art and a program disturbance for each voltage applied to a control gate.

4 is a layout diagram illustrating a three transistor type MTP unit cell according to the present invention.

FIG. 5A is a cross-sectional view taken along the line AA ′ of FIG. 4.

5B is a cross-sectional view taken along the line BB ′ in the layout diagram of FIG. 4.

6 is a circuit diagram illustrating a symbol of an MTP unit cell shown in FIG. 4.

7 is a circuit diagram illustrating an MTP cell array according to the present invention.

8A through 8C are conceptual views illustrating the operation of the MTP cell array shown in FIG. 7.

The present invention relates to a non-volatile semiconductor memory device, and more particularly, MTP (Multi Programmable and Efficient) can be programmed and erased many times using a semiconductor process for manufacturing an embedded high voltage (Embedded High Voltage) device without additional processing. -Time Programmable) relates to a technique for implementing a cell.

1A and 1B are cross-sectional views showing MTP cells according to the prior art.

In the case of the MTP cell, a program state and an erase state are determined according to the voltage Vcg, the drain voltage Vds, and the source voltage Vs applied to the control gate.

1A is a cross-sectional view of an MTP cell showing a program condition according to the prior art.

The program condition of the MTP cell according to the prior art is that the voltage Vcg applied to the control gate 1 is the high voltage Vpp, the drain 3 voltage Vds is the ground GND, the source (4) voltage Vs is the power supply voltage Vcc and the bulk (5) voltage. Vbulk is set to ground GND. Thus, electrons are injected into the floating gate 2 and programmed.

1B is a cross-sectional view of an MTP cell showing an erasure condition according to the prior art.

The erase condition of the MTP cell according to the related art is that the voltage Vcg applied to the control gate 1 applies the high voltage Vpp, the drain 3 and the source 4 are floating, and the bulk 5 voltage Vbulk. Is set to the high voltage Vpp. Thus, the electrons from the floating gate 2 are extracted into the bulk 5 and erased.

2 is a graph illustrating a relationship between a control gate voltage Vcg and a cell current of an MTP cell according to the prior art.

3A is a circuit diagram illustrating a cell array according to the prior art, and FIG. 3B is a layout diagram. Here, an example of a stack gate type cell will be described.

The cell array includes a plurality of word lines WL1, WL2, WL3, a plurality of bit lines BL1, BL2, a common source line CS, and a plurality of unit cells UC.

The plurality of word lines WL1, WL2, and WL3 are formed in the X axis direction by using a control gate.

A floating gate is formed under each word line WL1, WL2, and WL3.

The plurality of bit lines BL1 and BL2 are formed in the Y-axis direction and connected to the drains of the unit cells UC through metal contacts.

The common source line CS is formed in the Y-axis direction parallel to the bit lines BL1 and BL2 and commonly connected to the sources of the two unit cells US through one contact.

FIG. 3C is a circuit diagram illustrating an operation of programming A cell in the cell array shown in FIG. 3A.

As illustrated in FIG. 3C, an unwanted high voltage Vpp is applied to an unselected B cell commonly connected to the selected word line WL2 during a program operation on the A cell, thereby shifting the threshold voltage of the unselected B cell upward. Occurs.

FIG. 3D is a graph illustrating a program time for an MTP cell according to the related art and a program disturbance for each voltage applied to a control gate. Here, a change in the reference threshold voltage of the erased cell for each voltage level and pulse width of the high voltage Vpp applied to the control gate during programming is shown.

Referring to FIG. 3D, when the voltage of the high voltage VPP increases or the pulse time increases, the reference threshold voltage of the erased cell should be maintained at a low level (1.5 to 2.0 V) but not selected by the high voltage Vpp applied to the selected cell. An uncelled cell also represents a case where an unwanted threshold voltage shift occurs.

As described above, in the case of MTP cells repeatedly performing program and erase processes, the reliability characteristics of the device may be deteriorated due to high voltage stresses that continue in unwanted cells, causing failure. That is, since the threshold voltage difference between the programmed cell and the erased cell is reduced, there is a problem that the erased cell malfunctions like the programmed cell due to the continuous high voltage stress.

In addition, a non-volatile storage device in the form of a stack gate, which is initially produced, has a structure in which a floating gate and a control gate are stacked up and down on the basis of ONO. -silicon).

However, 1) Tunnel Oxidation Process and 2) Cell Threshold Injection for MTP Cell Formation in CMOS Process, One Layer Poly-silicon, Currently Used in Logic Only Devices Implantation Process, 3) Falling Gate Formation Process, 4) ONO Formation Process, 5) Cell S / D Injection Process, 6) Control Gate Formation Process, etc. are added.

As a result, the process becomes complicated, resulting in a problem of low reliability.

An object of the present invention for solving the above problems is to implement an MTP cell using only a semiconductor process for manufacturing an embedded high voltage device.

Another object of the present invention is to improve the reliability of the device by lowering the device failure rate due to process variables.

It is another object of the present invention to eliminate program failures for unselected cells.

A nonvolatile semiconductor memory device of the present invention for achieving the above object is a plurality of word lines; A plurality of bit lines; Common source line; And a plurality of unit cells, the unit cell comprising: a selection transistor controlled by a selection voltage applied to a selection line to selectively transfer a voltage applied to the word line; A control node for injecting or emitting electrons by capacitance coupling to the floating gate in accordance with the voltage delivered through the selection transistor; And a sense transistor for detecting a cell current according to the charge potential of the floating gate.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the spirit of the present invention is thoroughly and completely disclosed, and the spirit of the present invention to those skilled in the art will be fully delivered. Also, like reference numerals denote like elements throughout the specification.

The present invention can be implemented in a single layer poly silicon type by changing the existing MTP cell of a double layer poly silicon type into a structure arranged in a plane by function, thereby improving the characteristics of the existing MTP cell. The MTP cell, which can be programmed and erased several times, is implemented by using a semiconductor process for fabricating an existing logic device without any additional process for implementation.

4 is a layout diagram illustrating a three transistor type MTP unit cell according to the present invention.

The 3 T MTP unit cell illustrated in FIG. 4 has a structure in which three transistors are connected. That is, the MTP unit cell UC includes a select transistor 100, a control transistor 200, and a sensing transistor 300.

The select transistor 100 is formed in a P-well 10 in a region separated by an isolation layer (STI) 12, and includes a poly gate 14 and an N + junction. And a drain 16 and a source 18 formed therein.

The control transistor 200 is formed in an N-well 20 in a region separated by the device isolation film 12, and has an N-junction 22, a floating gate 24, and The metal line 26 is connected to the source 16 of the select transistor 100.

The sensing transistor 300 is formed in a P-well 30 in a region separated by the device isolation layer 12, and has a drain formed of a floating gate 24 and an N + diffusion junction. 32) and source 34.

The word line 40 is connected to the N + junction 14 of each unit cell UC through the metal line 42. Here, the N + junction 14 serves as the drain 14 of the select transistor 100.

That is, the voltage applied to the word line 40 during the program operation is connected to the N + junction 14 which acts as a drain of the select transistor 100 through the metal line 42.

The selection transistor 100 is selectively turned on according to the gate voltage to transmit the voltage applied to the word line 40 to the N-junction 22 of the control transistor 200 through the metal line 26.

When the select transistor 100 is turned on and a high voltage is applied to the N-junction 22, the potential of the floating gate 24 formed of polysilicon by an inversion layer formed under the N-junction 22. Induce change.

That is, an appropriate voltage is applied to the gate of the sense transistor 300 by the ratio of the floating gate 24 capacitance of the sense transistor 300 to the N-junction 22 capacitance of the control transistor 200.

In this case, the floating gate 24 formed of polysilicon serves as a gate node of the sensing transistor 300, and N + diffusion junctions 32 and 34 are disposed above and below the gate.

The N + diffusion junction 32 formed at the top is connected to the metal line (bit line) 36 to operate as a drain, and the N + diffusion junction 34 formed at the bottom is connected to the metal line (common source line) 38. Act as the source

When a bias of about 3 to 6V is applied to the drain 32 of the sensing transistor 300, hot carriers are generated at the edges of the drain 32 and the floating gate 24 due to the drain voltage.

When a high voltage is applied to the floating gate 24 of the sensing transistor 300 (when the voltage of the floating gate 24 is high), a hot carrier (generated by a vertical electric field) may be used. Electrons) are injected into the floating gate 24 across the barrier of the gate oxide film 44.

FIG. 5A is a cross-sectional view taken along the line AA ′ of FIG. 4.

Referring to FIG. 5A, it can be seen that there is no significant difference from the cross-sectional view of a semiconductor device for implementing a general CMOS logic device.

5B is a cross-sectional view taken along the line BB ′ in the layout diagram of FIG. 4.

Referring to FIG. 5B, the gate oxide layer 44 of the sensing transistor 300 may be an oxide layer having a thickness of about 70 to about 100 μs used for a logic NMOS / PMOS transistor used in a conventional CMOS process without additional process.

The gate oxide layer 44 of the sensing transistor 300 performs the same role as the tunnel oxide layer of the conventional stack gate type cell and also serves as the gate oxide layer for current sensing of the MTP cell.

The drain 32 and the source 34 of the sensing transistor 300 are the same as the semiconductor process for manufacturing an N + junction for a logic NMOS without any additional process.

The minimum design rule of poly length is such that the capacitance of the N-junction 22 of the control transistor 200 and the capacitance of the floating gate 24 of the sense transistor 300 are about 1.5-5. Adjust the diffusion width with the rule fixed.

In addition, when the N-junction 22 capacitance of the control transistor 200 is formed to be relatively larger so that a high voltage is applied to the N-junction 22 of the control transistor 200, the floating gate of the sensing transistor 300 ( 24) Channel Hot Electron Injection (CHEI) or FN tunneling is formed larger.

6 is a circuit diagram illustrating a symbol of an MTP unit cell shown in FIG. 4.

Select line SL is connected to gate 14 of select transistor 100, drain 16 is connected to word line WL, and source 18 is connected to N-junction 22 of control transistor 200. .

The sense transistor 300 includes a gate 24, a drain 32, a source 34, and a substrate 30 formed by extending the floating gate 24 formed on the N-junction 22 of the control transistor 200. Has terminals.

Accordingly, the MTP unit cell performs the program, erase, and read operations according to the word line WL, the select line SL, the drain 32 of the sense transistor 300, the source 34, and the substrate 30.

Table 1 shows word line WL, select line SL, drain 32, source 34, and substrate 30 voltage states of the program, erase, and read operations.

Word line Select line drain sauce Board program VPP VPP VCC + a 0 V 0 V elimination 0 V VPP VPP VPP 0 V lead VCC VCC VCC-a 0 V 0 V

First, in the program method, a high voltage Vpp of about 7 to 14 V is applied to the N + junction 16 of the select transistor 100 through the word line WL, and the word line WL is applied to the gate 14 of the select transistor 200. The same high voltage Vpp as applied high voltage Vpp is applied.

Therefore, the selection transistor 100 is turned on and the voltage Vcc + a, which is dropped by the threshold voltage at the high voltage Vpp, is transferred to the N− junction 22 of the control transistor 200.

The voltage transferred to the N-junction 22 of the control transistor 200 generates coupling with the capacitance of the floating gate 24, thereby increasing the potential of the floating gate 24.

At this time, when a power supply voltage Vcc of about 3-6V is applied to the drain 32 of the sensing transistor 300, a high electric field is generated around the drain 32.

When a high electric field is formed, hot carriers are generated and the remaining hot carriers which are not trapped in the oxide film 44 are transferred to the floating gate 24 by a high potential coupled to the floating gate 24. Is injected.

Hot carriers (electrons) in the channel of the sense transistor 300 occur mainly under the condition that the gate voltage is greater than or equal to the drain voltage.

Channel electrons accelerated sufficiently to have higher energy than the gate oxide barrier around the drain by the lateral field are cuffed to the floating gate 24 of the sense transistor 300 before impacting the silicon (substrate) grating. The vertical electric field is generated by the high gate potential and flows in the direction of the gate oxide film around the pinch off of the drain junction.

In addition, the erasing method uses a method of emitting electrons of the floating gate 24 to the drain 32 and the source 34 by using the FN tunneling mechanism.

Externally applied high voltage Vpp of 7-14V is simultaneously applied to the drain 32 and the source 34 of the sense transistor 300 through the metal contact, at which time the high voltage Vpp is applied to the selection line SL and the word line WL. The selection transistor 100 is turned on by applying a 0V voltage.

A 0V voltage applied to the word line 40 is applied to the N-junction 22 of the control transistor 200 to couple the floating gate 24 to the low potential.

A high electric field is generated in the drain 32 and the source 34 relative to the potential of the coupled floating gate 24, and the electrons of the floating gate 24 pass through the oxide film 44 barrier by this electric field. FN tunneling is then emitted to the drain 32 and source 34.

On the other hand, in the read method, after the program or erase operation is completed in the MTP cell, that is, the transistor is injected into the floating gate 24 in the CHEI method or a high voltage is applied to the source / drain to emit electrons by FN tunneling and then the sensing transistor. The cell current of 300 is performed in a manner of reading.

In order to read the cell current, the power supply voltage Vcc of about 3 to 6V is applied to the word line 40 and the same power supply voltage Vcc is applied to the gate 14 of the selection transistor 100 so that the selection transistor 100 is turned on. .

At this time, the drain 32 of the sensing transistor 300 is applied with a voltage of about 1 to 3 V lower than the power supply voltage Vcc in order to prevent drain disturbance, so that the flow of the cell current between the drain 32 and the source 34 is reduced. Sensing nothing.

If the state, that is, electrons are floating gate voltage is changed by the Q _inj when been injected (charges) as much as Q _inj to the floating gate 24, a program is expressed as Equation 1.

The shift value of the threshold voltage generated while the electric charge is stored in the floating gate 24 is expressed as shown in [Equation 2].

That is, when electrons are injected, Q _inj <0, and thus ΔV _T > 0.

As a result, the threshold voltage of the sense transistor 300 is expressed as shown in [Equation 3].

Since the threshold voltage of the sensing transistor 300 is higher than the initial level due to the electrons injected into the floating gate 24, it is difficult to invert the channel. Cell current does not flow.

Conversely, in the erased state, that is, when electrons are extracted from the floating gate to the source / drain, ΔV _T <0 since Q _inj > 0.

As a result, the threshold voltage of the selection transistor is expressed as shown in [Equation 4].

When the read voltage is applied to the drain 32 of the sense transistor 300 because the threshold voltage is lowered, the potential of the floating gate 24 sufficiently inverts the channel so that the cell current flows due to the potential difference between the source and the drain. do.

7 is a circuit diagram illustrating an MTP cell array according to the present invention.

The MTP cell array includes a plurality of word lines WL1 to WLn, a plurality of bit lines BL1 to BLm, a plurality of select lines SL1 to SLm, a common source line CS, and a plurality of unit cells UC1 to UCnm.

The plurality of word lines WL1 to WLn are connected to the N + junction 16 (drain of the selection transistor 100) of the plurality of unit cells UC1 to UCnm.

The plurality of bit lines BL1 to BLm are connected to the N + diffusion junctions 32 (drains of the sensing transistor 300) of the plurality of unit cells UC1 to UCn.

The plurality of select lines SL1 to SLm are connected to the gate 14 of the select transistor 100 of the plurality of unit cells UC1 to UCn.

The common source line CS is commonly connected to the N + diffusion junctions 34 (sources of the sensing transistor 300) of all the unit cells UC1 to UCnm.

The plurality of unit cells UC1 to UCnm are arranged in a matrix form.

8A through 8C are conceptual views illustrating the operation of the MTP cell array shown in FIG. 7.

First, FIG. 8A is a conceptual diagram illustrating a method of programming a specific cell UC22 in the MTP cell array shown in FIG. 7.

The high voltage Vpp is applied to the selected word line WL2, and the ground voltage 0V is applied to all of the unselected word lines WL1 and WL3 to WLn.

A high voltage Vpp of about 7 to 14 V is applied to the select line SL2 of the selected unit cell UC22 among the unit cells UC21 to UC2m connected to the selected word line WL2, and a ground voltage of 0 V is applied to the unselected select lines SL1 and SL3 to SLm. do.

Therefore, when the select transistor 100 is turned on and the high voltage Vpp applied to the selected word line WL2 is transferred to the N-junction 22 of the control transistor 200, and the power supply voltage Vcc is applied to the selected bit line BL2, the CHEI Inflow of electrons into the floating gate 24

In the other unselected unit cells, a gate disturbance does not occur because the high voltage Vpp applied to the word line WL2 turns off the selection transistor 100 during a program operation.

FIG. 8B is a conceptual diagram illustrating an operation of erasing all unit cells of the MTP cell array shown in FIG. 7. Although the case where all MTP unit cells are simultaneously erased has been described as an example, a specific unit cell may be erased by selectively applying a drain and a source voltage.

When a ground voltage of 0 V is applied to all word lines WL1 to WLn and a high voltage Vpp is applied to all select lines SL1 to SLm, the select transistors 100 of all the unit cells UC11 to UCnm are turned on so that the N-junction 22 is turned on. Low potential.

In this case, when high voltage Vpp is applied to the drain 32 and the source 34 of the sensing transistor 300, electrons stored in the floating gate 24 are discharged to the drain 32 and / or the source 34.

FIG. 8C is a conceptual diagram illustrating an operation of reading data stored in a specific unit cell in the MTP cell array shown in FIG. 7.

To read the data stored in the unit cell, read the cell current. When the power supply voltage Vcc of about 3 to 6V is applied to the selected word line WL2 to read the cell current, and the same power supply voltage Vcc is also applied to the selected selection line SL2, the selection transistor 100 is turned on.

The remaining unselected word lines and the unselected select lines are all applied with a ground voltage of 0V.

In order to prevent drain disturbance, the drain 32 of the selected unit cell is applied with a voltage of about 1 to 3 V lower than the power supply voltage Vcc applied to the word line to prevent the threshold voltage shift. ), Ground voltage 0V is applied.

Accordingly, a potential difference of about 1 to 3 V is generated between the source 34 and the drain 32, so that the source 34 and the drain of the unit cell depend on whether the channel is inverted according to the electron potential of the floating gate 24. The presence or absence of cell current between the 32 can be sensed.

As described above, the nonvolatile semiconductor memory device according to the present invention has an effect of implementing an MTP cell using only a semiconductor process for manufacturing an embedded high voltage device.

In addition, the nonvolatile semiconductor memory device according to the present invention has an effect of improving the reliability of the device by reducing the device failure rate due to process variables.

In addition, the nonvolatile semiconductor memory device according to the present invention has the effect of eliminating the program failure phenomenon for the unselected cells.

In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, substitutions and highlights through the spirit and scope of the appended claims, such modifications, changes, etc. are claimed It should be seen as belonging to a range.

Claims (14)

Multiple word lines; A plurality of bit lines; Common source line; And a plurality of unit cells, the non-volatile semiconductor memory device comprising: The unit cell is A selection transistor controlled by a selection voltage applied to a selection line to selectively transfer a voltage applied to the word line; A control node for injecting or emitting electrons by capacitance coupling to the floating gate in accordance with the voltage delivered through the selection transistor; And And a sensing transistor for detecting a cell current according to the potential of the floating gate. The method of claim 1, The unit cell is formed using a semiconductor process for manufacturing a single layer polysilicon device. The method of claim 1, And the selection transistor is an NMOS transistor formed in a P well. The method of claim 3, wherein the selection transistor A gate connected to the selection line; A drain connected to the word line and formed of an N + junction; And And a source connected to said control node and formed of an N + junction. The method of claim 4, wherein The source of the selection transistor and the control node is connected via a metal line. The method of claim 1, And the control node is formed of an N-junction in an N well. The method of claim 1, And the sense transistor is an NMOS transistor formed in a P well. The method of claim 1, wherein the sense transistor is A floating gate extending from an upper portion of the control node; A drain connected to the bit line and formed of an N + diffusion junction; And And a source connected to said common source line and formed of an N + diffusion junction.  The method of claim 8, And the capacitance of the control node is greater than the capacitance of the floating gate of the sense transistor. The method of claim 8, And controlling the diffusion width of the floating gate in a state where the length of the floating gate is fixed according to a minimum design rule in order to adjust a ratio of the capacitance of the control node and the capacitance of the floating gate of the sensing transistor. The method of claim 1, wherein the unit cell A high voltage is applied to the word line and the select line so that the select transistor is turned on to apply a high voltage to the control node, a power supply voltage is applied to a drain of the sense transistor, and a ground voltage is applied to a source of the sense transistor. And perform a program operation by injecting electrons into the floating gate using CHEI (Channel Hot Electron Injection). The method of claim 1, wherein the unit cell A ground voltage is applied to the word line, a high voltage is applied to the select line, the select transistor is turned on, a ground voltage is applied to the control node, and a high voltage is applied to the drain and source of the sense transistor. A nonvolatile semiconductor memory device, characterized in that to perform an erase operation by the way the electrons of the gate is emitted. The method of claim 1, wherein the unit cell A ground voltage is applied to the word line, a high voltage is applied to the select line so that the select transistor is turned on to apply a ground voltage to the control node, a drain and a source of the sense transistor are floated, and a high voltage is applied to the bulk. And an erase operation is performed by applying electrons of the floating gate to emit the electrons of the floating gate. The method of claim 1, wherein the unit cell A power supply voltage is applied to the word line and the selection line so that the selection transistor is turned on to apply a power supply voltage to the control node, a read voltage lower than the power supply voltage is applied to the drain of the sensing transistor, and grounded to a source. And applying a voltage to sense a cell current according to the potential of the floating gate to perform a read operation.

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