KR102689627B1 - Semiconductor device including single poly non-volatile memory device and manufacturing method thereof - Google Patents

Abstract

The semiconductor device of the present invention includes first, second and third regions on a semiconductor substrate; and first, second, and third semiconductor devices formed in the first, second, and third regions, respectively, wherein the first semiconductor device includes: a first gate insulating film; and a first gate electrode formed on the first gate insulating layer, wherein the second semiconductor device includes a second gate insulating layer thicker than the first gate insulating layer. and a second gate electrode formed on the second gate insulating film, wherein the third semiconductor device includes a plurality of third gate insulating films; a plurality of third gate electrodes each formed on the plurality of third gate insulating films; and an ion implantation layer for increasing the thickness of the gate insulating layer, wherein one of the plurality of third gate insulating layers is formed to be thicker than the second gate insulating layer.

Description

Semiconductor device including non-volatile memory device and manufacturing method using same {SEMICONDUCTOR DEVICE INCLUDING SINGLE POLY NON-VOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF}

The present invention relates to a semiconductor device including a non-volatile memory device and a manufacturing method using the same.

Non-Volatile memory (NVM) devices are used in various applications such as Controller ICs, MCUs, and RFID Tags that require electrical writing and erasing functions and data storage even at low power, and are used for trimming to correct circuit characteristics and improve yield. In addition, it is used in many semiconductor products as data storage.

Using the CMOS process, NVM devices, LV devices, MV devices, and HV devices are formed on one chip. The thickness of the gate insulating film used for each LV, MV, and HV device is different. NVM devices also have various gate insulating films, such as sensing gate insulating films, selection gate insulating films, and control gate insulating films. One chip requires at least 4 to 7 gate insulating films of different thicknesses. There is a problem that the process of forming a plurality of gate insulating films is very complicated and the cost increases significantly.

US Registered Patent Publication US 6,255,169

This application is about a method of manufacturing a non-volatile memory device to solve the problems of the prior art described above. A sensing gate insulating film, a selection gate insulating film, and a control device having various thicknesses are used in an NVM device using an ion implantation process to increase the thickness of the gate insulating film. The purpose is to form a gate insulating film at low cost.

In order to achieve the above-described object, the present invention includes first, second and third regions on a semiconductor substrate; and first, second, and third semiconductor devices formed in the first, second, and third regions, respectively, wherein the first semiconductor device includes: a first gate insulating film; and a first gate electrode formed on the first gate insulating layer, wherein the second semiconductor device includes a second gate insulating layer thicker than the first gate insulating layer. and a second gate electrode formed on the second gate insulating film, wherein the third semiconductor device includes a plurality of third gate insulating films; a plurality of third gate electrodes each formed on the plurality of third gate insulating films; and an ion implantation layer for increasing the thickness of the gate insulating layer, wherein one of the plurality of third gate insulating layers is thicker than the second gate insulating layer.

Here, among the plurality of third gate electrodes, at least two gate electrodes are electrically connected to each other using a single piece of poly-silicon, and the thickness of the third gate insulating film formed under each of the at least two gate electrodes is equal to the remaining thickness. The thickness may be greater than the thickness of the third gate insulating film formed under one gate electrode.

Here, one of the plurality of third gate insulating layers may be formed to have the same thickness as the second gate insulating layer.

Here, the first or second semiconductor device is characterized as being one of an SRAM device, a standard cell device, a logic device, a digital device, or an analog device, and the memory device is an electrically programmable read only memory (EPROM). ), electrically erasable programmable read only memory (EEPROM), Flash memory, multiple time programmable (MTP) memory device, or one time programmable (OTP) memory device.

Here, the third semiconductor device is characterized in that it is a single poly multi-time programmable non-volatile memory device, the non-volatile memory device includes a sensing transistor, a selection transistor, and a control gate structure, and the gate electrode of the sensing transistor and the gate electrode of the control gate structure may be electrically connected to each other.

Here, the sensing transistor includes a sensing gate insulating film and a sensing gate electrode, the selection transistor includes a selection gate insulating film and a selection gate electrode, the control gate structure includes a control gate insulating film and a control gate electrode, and the sensing The thickness of the gate insulating layer and the control gate insulating layer may be the same or thicker than the selection gate insulating layer.

Meanwhile, the present invention provides a step of forming a logic device and a non-volatile memory device on a semiconductor substrate, including selectively forming an ion implantation layer to increase the thickness of the gate insulating film in a region where the non-volatile memory device is formed; simultaneously forming a gate insulating layer of the logic device and a gate insulating layer of the non-volatile memory device; and forming a gate electrode on the gate insulating layer of the logic element and the gate insulating layer of the non-volatile memory device, respectively, wherein the gate insulating layer of the non-volatile memory device is thicker than the gate insulating layer of the logic element. A semiconductor device manufacturing method is additionally provided.

Here, the ion implantation layer may use a dopant containing any one of fluorine, arsenic, boron, germanium, or argon.

Here, the non-volatile memory device is characterized as a single poly multi-time programmable non-volatile memory device, the non-volatile memory device includes a sensing transistor, a selection transistor, and a control gate structure, and the gate electrode of the sensing transistor and the gate electrode of the control gate structure may be electrically connected to each other.

Here, the thickness of the gate insulating film of the sensing transistor may be thicker than that of the logic element.

Here, after forming a gate electrode on the gate insulating film of the logic device and the gate insulating film of the non-volatile memory device, forming a well region of the logic device and a well region of the non-volatile memory device are further performed. It can be included.

The disclosed technology can have the following effects. However, since it does not mean that a specific embodiment must include all or only the following effects, the scope of rights of the disclosed technology should not be understood as being limited thereby.

According to the means for solving the problem of the present application described above, the non-volatile memory device manufacturing method according to the present application can control the thickness of the gate insulating film by controlling the ions of the ion implantation process without additionally performing a separate oxidation process. Simplification is possible. This solves the problem of requiring an additional oxidation process to adjust the thickness of some gate insulating films of conventional devices.

The non-volatile memory device using the manufacturing method of the present application can improve the durability of the device as well as the data preservation ability by improving the deterioration of the oxide as the device cycles by having separate program areas and erase areas.

Additionally, non-volatile memory devices can improve write and erase operation efficiency and reduce the area of the memory device.

1 is a cross-sectional view of a gate insulating film of a semiconductor device according to an embodiment of the present invention.
2A to 2E show a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Figure 3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
Figure 4 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
Figure 5 is a plan view of a non-volatile memory device according to an embodiment of the present invention.
6 and 7 are cross-sectional views of a non-volatile memory device according to an embodiment of the present invention.
8 and 9 are cross-sectional views of a non-volatile memory device according to another embodiment of the present invention.
10A to 10G show a method of manufacturing a non-volatile memory device according to an embodiment of the present invention.

Since the present invention can be subject to various changes and can have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all changes, equivalents, and substitutes included in the spirit and technical scope of the present invention.

While describing each drawing, similar reference signs are used for similar components. Terms such as first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

For example, a first component may be referred to as a second component, and similarly, the second component may be referred to as a first component without departing from the scope of the present invention. The term “and/or” may include any of a plurality of related stated items or a combination of a plurality of related stated items.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the technical field to which the present invention pertains.

Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and unless clearly defined in the present application, should not be interpreted as having an ideal or excessively formal meaning. It shouldn't be.

Throughout this specification, when a member is said to be located “on”, “above”, “at the top”, “below”, “at the bottom”, or “at the bottom” of another member, this means that a member is located on another member. This can include not only cases where they are in contact, but also cases where another member exists between two members.

Throughout the specification of the present application, when a part "includes" a certain element, this means that it may further include other elements rather than excluding other elements, unless specifically stated to the contrary.

As used herein, the terms “about,” “substantially,” and the like are used to mean at or close to a numerical value when manufacturing and material tolerances inherent in the stated meaning are presented, and to aid understanding of the present application. It is used to prevent unscrupulous infringers from unfairly exploiting disclosures in which precise or absolute figures are mentioned. Additionally, throughout the specification herein, “a step of” or “a step of” does not mean “a step for.”

Throughout this specification, the term "combination thereof" included in the Markushi format expression means a mixture or combination of one or more components selected from the group consisting of the components described in the Markushi format expression, It means including one or more selected from the group consisting of.

Hereinafter, a semiconductor device including a non-volatile memory device of the present application and a manufacturing method using the same will be described in detail with reference to implementation examples, examples, and drawings. However, the present application is not limited to these implementation examples, examples, and drawings.

1 is a cross-sectional view of a gate insulating film of a semiconductor device including a non-volatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor device has a low voltage (LV) region 11, a medium voltage (MV) region 12, and a non-volatile memory (NVM) region 13. may include. First to third gate insulating films ( 31, 35, 39) can be formed. Additionally, first to third semiconductor devices (not shown) may be formed in the LV region 11, MV region 12, and NVM region 13, respectively. The first to third semiconductor devices may be called low-voltage devices, mid-voltage devices, and non-volatile memory devices depending on the operating voltage.

Low voltage (LV) devices or medium voltage (MV) devices can be used to form SRAM, standard cells, logic devices, digital devices, or analog devices. The low voltage (LV) area 11 and the medium voltage (MV) area 12 may be called an SRAM area, standard cell area, logic area, digital area, or analog area.

Non-volatile memory devices refer to electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), Flash memory, multiple time programmable (MTP) memory devices, or one time programmable (OTP) memory devices. Here, the multiple time programmable (MTP) memory device may be a single poly multi-time programmable memory device.

So, broadly speaking, the low-voltage and mid-voltage device regions 11 and 12 can be viewed as areas where SRAM devices, standard cell devices, logic devices, digital devices, or analog devices are formed. On the other hand, the non-volatile memory (NVM) area 13 can be viewed as an area where memory elements are formed.

The operating voltage of the low voltage area 11 may be 1-3V, the operating voltage of the medium voltage area 12 may be 2-10V, and the non-volatile memory (NVM) area 13 may be 2-15V.

Meanwhile, the medium voltage (MV) area 12 and the non-volatile memory (NVM) area 13 have similar operating voltages. Therefore, the thickness of the gate insulating film may be similar in many cases in the medium voltage (MV) region 12 and the non-volatile memory (NVM) region 13. The NVM area 13 may be referred to as the memory area 13.

It can be seen that the first gate insulating film 31 has a thickness of 5 Å to 40 Å in the low voltage region 11 . The thickness of the second gate insulating film 35 in the medium voltage region 12 may be 30 Å to 150 Å, and the thickness of the third gate insulating film 39 in the non-volatile memory (NVM) region 13 may be 50 Å. It can be formed from Å to 200 Å. The thickness of the third gate insulating layer 39 in the NVM region 13 may be at least thicker than the thickness of the second gate insulating layer 35 in the medium voltage region 12.

The thickness difference between the third gate insulating film 39 in the memory area 13 and the second gate insulating film 35 in the mid-voltage area 12 is due to the manufacturing method. Although not shown, only the NVM area is opened to perform the fluorine ion implantation process. This is the result when the oxidation process was performed after performing the fluorine ion implantation process. Instead of fluorine ions, arsenic (As), argon (Ar), phosphorus (P), boron (B), or germanium (Ge) ions can be implanted. Here, fluorine ion is used as a representative example. In the medium voltage region 12 where the fluorine ion implantation process was not performed, the second gate insulating film 35 had a thickness of 30 Å to 150 Å, whereas in the memory region 13 where the fluorine ion implantation process was performed, the third gate insulating film 35 had a thickness of 30 Å to 150 Å. (39) can be formed thicker, with a thickness of 50 Å to 200 Å. This will be explained in detail in FIGS. 2A, 2B, 2C, 2D, and 3.

2A to 2E are diagrams of a method of manufacturing a semiconductor device including a non-volatile memory device according to an embodiment of the present invention.

Referring to FIG. 2A, a DNW area 13DN may be formed in the NMV area or memory area 13 of the substrate 21. A DNW region 13DN is formed to separate the substrate from the well region (not shown) formed below the memory device. And a mask pattern 25 is formed. The mask pattern 25 may cover the LV and MV regions 11 and 12. And the memory area 13 is open. Then, ion implantation (27) is performed on the substrate using fluorine ions (F). Ion implantation 27 may be performed while passing through the screen insulating film 29. The screen insulating film 29 is an insulating film to protect the substrate surface and can be removed after ion implantation. Alternatively, ion implantation can be performed without the screen insulating film 29. Instead of fluorine (F) atoms, arsenic, argon, phosphorus, boron, etc. can be used. Therefore, the fluorine ion (F) injection layer 30 can be formed only in the memory area 13. The fluorine ion (F) implantation region 30 may be referred to as an ion implantation layer 30 for increasing the thickness of the gate insulating film. Alternatively, a mask pattern 25 may be formed in a partial area of the memory area 13 to prevent fluorine ions from being implanted into the partial area of the memory area 13 (see FIG. 10A).

Referring to FIG. 2B, the process of forming gate insulating films 35, 37, and 39 is performed simultaneously in the mid-voltage region and the non-volatile memory region. Therefore, medium voltage gate insulating films 35 and 37 and non-volatile memory gate insulating films 39 having different thicknesses can be formed in the medium voltage region 12 and the non-volatile memory region 13, respectively. Since the second gate insulating films 35 and 37 and the NVM gate insulating film 39 are formed at the same time in the same step, process costs can be significantly reduced. The reason is that the number of masks is decreasing. If a separate mask is used to form the NVM gate insulating film 39, the cost increases significantly. In this way, if the operating voltages of the medium voltage (MV) area 12 and the non-volatile memory (NVM) area 13 are similar and different thicknesses are required, process costs can be reduced. For this purpose, it is advantageous to form a gate insulating film at the same time. The thickness of the NVM gate insulating layer 39 may be thicker than the thickness of the second gate insulating layers 35 and 37. This is because fluorine ions (F) were injected only into the memory area 13. After fluorine (F), arsenic (As), argon (Ar), phosphorus (P), boron (B), or germanium (Ge) ions are injected, the oxidation process speeds up by more than three times. A gate insulating film that is thicker than other areas may be formed.

Referring to FIG. 2C, a process of forming first gate insulating films 31 and 33 is performed in the low voltage region 11. When the first gate insulating films 31 and 33 are formed, the second gate insulating films 35 and 37 and the NVM gate insulating film 39 may slightly increase in thickness. So, finally, a plurality of gate insulating films are formed on the substrate 21. In the LV region 11, first gate insulating layers 31 and 33 may be formed on the P-type well regions (PW, 11P) and N-type well regions (NW, 11N), respectively. In the MV region 12, second gate insulating films 35 and 37 may be formed on the P-type well region (PW, 12P) and the N-type well region (NW, 12N), respectively. In the memory area 13, an NVM gate insulating layer 39 may be formed on an N-type deep well area (DNW, 13DN).

Referring to FIG. 2D, a gate electrode is formed on each gate insulating film. In the LV region 11, a first semiconductor device including first gate electrodes 41 and 43 may be formed on the first gate insulating films 31 and 33. In the MV region 12, a second semiconductor device including second gate electrodes 45 and 47 may be formed on the second gate insulating films 35 and 37. A plurality of gate insulating films and a plurality of gate electrodes may be formed in the memory area 13. First, first to third NVM gate insulating films 39a, 39b, and 39c are formed with a plurality of gate insulating films. And a plurality of first, second, and third NVM gate electrodes 49a, 49b, and 49c may be formed from the plurality of gate electrodes. Here, through an etching process for forming a plurality of first, second and third NVM gate electrodes 49a, 49b, and 49c, the NVM gate insulating film 39 described in FIG. 2B or 2C is formed into a plurality of NVM gate insulating films ( It can be separated into 39a, 39b, 39c). Therefore, the NVM gate insulating films 39a, 39b, and 39c may be formed below the first, second, and third NVM gate electrodes 49a, 49b, and 49c, respectively, spaced apart from each other.

FIG. 2D shows a case where the first, second, and third NVM gate insulating films 39a, 39b, and 39c are formed to have the same thickness under the first, second, and third NVM gate electrodes 49a, 49b, and 49c. And the first NVM gate electrode 49a and the third NVM gate electrode 49c may be electrically connected to each other through the floating gate electrode 49d. However, the second NVM gate electrode 49b may not be connected to the floating gate electrode 49d.

Figure 2e shows a process of forming a plurality of well regions after forming the gate electrode. A P-type well region (PW, 11P) and an N-type well region (NW, 11N) may be formed in the LV region 11, respectively. A P-type well region (PW, 12P) and an N-type well region (NW, 12N) may be formed in the MV region 12, respectively. In the memory area 13, a plurality of P-type well regions 13P1 and 13P2 may be additionally formed within the N-type deep well regions DNW and 13DN. An NW (13N) for isolation purposes may be formed between the P-type well regions (13P1 and 13P2). The depth of the DNW area (13DN) is deeper than that of the PW (11P), NW (11N), PW (12P), NW (12N), P-type well areas (13P1, 13P2), and NW (13N). PW (11P), NW (11N), PW (12P), NW (12N), P-type well region (13P1, 13P2), and NW (13N) are formed using the gate electrode as a mask, so the depth of the bottom surface is flat. If you don't do this, curves may appear. The depth of well regions such as PW (11P), NW (11N), PW (12P), NW (12N), P-type well regions (13P1, 13P2), and NW (13N) overlapping with the gate electrode is equal to that of the gate electrode. It may have a shallower depth than the depth of the non-overlapping well regions. The gate electrode acts as a mask, so the depth of the overlapping well area becomes small.

Meanwhile, as another method, well regions such as PW (11P), NW (11N), PW (12P), NW (12N), P-type well regions (13P1, 13P2), and NW (13N) are formed using gate insulating films 31 and 33. , 35, 37, 39) can be formed prior to the forming process. In that case, the depth of the bottom surface of the well regions such as PW (11P), NW (11N), PW (12P), NW (12N), P-type well region (13P1, 13P2), and NW (13N) is formed to be flat. It can be.

Figure 3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

Referring to Figure 3, the structure is similar to Figure 2e. The difference is that the first, second and third NVM gate insulating films 39a, 39b and 39c may be formed with different thicknesses under the first, second and third NVM gate electrodes 49a, 49b and 49c. there is. In this case, a mask pattern 25 may be formed in the memory area 13 to prevent fluorine ion implantation in some areas (not shown). The first NVM gate electrode 49a and the third NVM gate 49c may be electrically connected to each other through the floating gate electrode 49d. The second NVM gate electrode 49b may not be connected to the floating gate electrode 49d. The thickness of the second NVM gate insulating layer 39b formed below the second NVM gate electrode 49b may be smaller than the thickness of the first and second NVM gate insulating layers 39a. In other words, the thickness of the first and third NVM gate insulating films 39a and 39c formed below the first and third NVM gate electrodes 49a and 49c connected to the floating gate electrode 49d is equal to the thickness of the floating gate electrode 49d. It may be greater than the thickness of the second gate insulating film 39b formed under the second NVM gate electrode 49b that is not connected to the second NVM gate electrode 49b. The first to third NVM gate insulating films 39a, 39b, and 39c in FIG. 6 or 7 will be described in detail.

Figure 4 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

LV elements and MV elements may be formed in the LV region 11 and MV region 12, respectively. The LV element and MV element have been described previously and are therefore omitted. In addition, a high voltage (HV) driving element for driving the NVM element may be formed in the driving element region 15. The HV driving elements each drive HV on a P-type high voltage well region (HPW, 15HPW) or a high voltage N-type well region (HNW, 15HNW). A device may be formed. The thickness of the gate insulating films 50 and 54 of the HV driving element may be greater than the thickness of the MV gate insulating films 35 and 37. HV drive devices require thicker gate insulation films to operate at higher voltages than MV devices. In the present invention, in order to reduce process costs, an ion implantation layer 30 may be formed to increase the thickness of the gate insulating film. The ion implantation layer 30 for increasing the gate insulating film thickness is implanted into the substrate 21 using dopants such as fluorine (F), arsenic, argon, phosphorus, and boron. can be formed. Therefore, the MV gate insulating films 35 and 37 and the gate insulating films 50 and 54 of the HV driving element can be formed simultaneously. Even if they are formed simultaneously, the growth rate of the gate insulating films 50 and 54 of the HV driving device is faster than that of the MV gate insulating films 35 and 37 because the dopant is ion-implanted, so they can be formed thicker.

Referring to FIG. 4, the semiconductor device may further include an NVM device operating by an HV driving device in the NVM region 17. The HV driving element includes a tunneling gate insulating film 60, a floating gate 62, a dielectric film 64, a control gate 66, a selection gate insulating film 68, and a selection gate 70 in an N-type deep well region (17DNW). and may be formed on the P-type well region 17PW.

Figure 5 is a plan view of a non-volatile memory device according to an embodiment of the present invention.

Referring to FIG. 5 , the non-volatile memory device may include a sensing transistor 1301, a selection transistor 1302, and a control gate structure 1303. The sensing transistor 1301 and the selection transistor 1302 may be formed in the first P-type well region 110 .

The sensing transistor 1301 may include a sensing gate electrode 150 and a first contact plug 170. Additionally, a bit line (Bit line, BL) may be connected to the drain contact of the sensing transistor to apply a drain voltage or a bit line voltage (V _BL ) to the first contact plug 170. Here, the sensing gate electrode 150 can be viewed as a part of the floating gate (FG) 400. The floating gate 400 is also used in the control gate structure 1303. There is no contact plug connected on the floating gate (FG) 400.

The selection transistor 1302 may include a selection gate electrode 250, a second contact plug 270, and a third contact plug 290. A source line (SL for short) may be connected to the second contact plug 270. In order to apply a voltage to the selection gate electrode 250, a selection gate line (SG line for short, SG) may be connected to the third contact plug 290. Here, the SG line can be called a word line (WL for short).

The control gate structure 1303 may include a fourth contact plug 370 and a control gate electrode 350 formed in the second P-type well region 310 . The fourth contact plug 370 formed in the second P-type well region 310 may be formed on both sides of the control gate. A control gate line (CG line, CG for short) may be connected to the fourth contact plug 370.

The control gate electrode 350 can be viewed as a part of the floating gate (FG) 400. The sensing gate electrode 150 and the control gate electrode 350 are formed using a single piece of polysilicon to electrically connect them to each other. Since there is no contact plug directly connected to the sensing gate electrode 150 and the control gate electrode 350, it is also called a floating gate (FG) 400. Therefore, it can be seen that electrons are charged or discharged in the floating gate electrode 400.

Figure 5 shows one memory cell including two transistors (1301, 1302) and one control gate structure (1303). Here, the two transistors are a sensing transistor 1301 and a selection transistor 1302, respectively. It is programmable by charging or discharging electrons through the sensing transistor 1301. The sensing transistor 1301 may be called a program transistor. A bit line (BL) voltage (V _BL ) is applied to the drain terminal 170 of the sensing transistor 1301. The selection transistor 1302 functions to select or not select the one cell. Additionally, the selection transistor 1302 is required for a read function to determine whether electrons are charged or discharged in the sensing transistor 1301. A selection gate voltage (V _SG ) and a source voltage (V- _SL ) are applied to the gate terminal 290 and source terminal 270 of the selection transistor 1302, respectively. The selection transistor 1302 may be turned on or off through the selection gate voltage (V _SG ) applied to the selection gate electrode. The sensing transistor 1301 and the selection transistor 1302 may be formed in one first well region 110 . The selection transistor 1302 can block leakage current (leakage) from flowing in the erased state. One control gate structure 1303 has a control gate structure for controlling charging or discharging of electrons in the sensing gate of the sensing transistor 1301. A control gate voltage (V _CG ) is applied to the fourth contact plug 370 of the control gate structure. One control gate structure may be formed in the second well region 310.

Figures 6 and 7 are cross-sectional views of a non-volatile memory device according to an embodiment of the present invention, taken along line XX' in Figure 5.

Referring to FIG. 6 , the non-volatile memory device may include first, second, and third NVM gate insulating layers 130, 230, and 330, as previously mentioned. The first, second, and third NVM gate insulating layers 130, 230, and 330 may correspond to the NVM gate insulating layers 39a, 39b, and 39c of FIG. 2D shown above. And the non-volatile memory device may further include first, second, and third NVM gate electrodes 150, 250, and 350 formed on the first, second, and third NVM gate insulating films 130, 230, and 330, respectively. You can. The first, second, and third NVM gate electrodes 150, 250, and 350 may correspond to the first, second, and third NVM gate electrodes 49a, 49b, and 49c of FIG. 2D or 3.

Hereinafter, for convenience of explanation, the first, second, and third NVM gate insulating layers 130, 230, and 330 are respectively referred to as a sensing gate insulating layer 130, a selection gate insulating layer 230, and a control gate insulating layer 330. Let's do it. And for convenience of explanation, the first, second, and third NVM gate electrodes 150, 250, and 350 will be referred to as the sensing gate electrode 150, the selection gate electrode 250, and the control gate electrode 350, respectively. do. The sensing gate electrode 150 may also be called a program gate electrode.

A sensing gate insulating layer 130 and a selection gate insulating layer 230 may be formed on the first P-type well region 110 . And a control gate insulating layer 330 may be formed on the second P-type well region 310 . The control gate insulating layer 330 can be viewed as a dielectric layer of the control gate structure 1303. A sensing gate electrode 150, a selection gate electrode 250, and a control gate electrode 350 may be formed on the sensing gate insulating film 130, the selection gate insulating film 230, and the control gate insulating film 330, respectively. The sensing gate electrode 150 and the control gate electrode 350 are part of the floating gate 400 and are physically and electrically connected to each other. The sensing gate electrode 150 and the control gate electrode 350 are gate electrodes made of a single poly-silicon film.

The thicknesses of the sensing gate insulating layer 130, the selection gate insulating layer 230, and the control gate insulating layer 330 are the same. However, as previously described, it may be formed thicker than the thickness of the second gate insulating films 35 and 37. This is because the ion implantation layer 120 is formed to increase the thickness of the gate insulating film. The ion implantation layer may be formed under the gate insulating film whose thickness is to be increased using dopants such as fluorine, argon, phosphorus, boron, and germanium (Ge). Here, as the thickness of the sensing gate insulating film 130 increases, the data preservation ability and retention of the MTP Cell improves. As the thickness of the gate insulating film increases, it becomes difficult for electrons stored in the floating gate to escape after performing a program or erase operation, thereby improving data preservation ability. This is because the sensing gate insulating film 130 is thick, preventing electrons from being easily discharged.

The non-volatile memory device may include a plurality of trenches 106 formed between the first P-type well region 110 and the second P-type well region 310 . It may further include a plurality of N-type well regions (NW, 108). The N-type well region (NW, 108) formed below the trench 106 may serve as a channel stop between neighboring devices. It may further include a deep well region (DNW) 107 surrounding the first P-type well region 110, the second P-type well region 310, and the N-type well region 108.

During program operation, Positive VPP can be applied to the fourth contact plug 370. And negative VPP can be applied to the second contact plug 270. Then, electrons are injected from the first PW to the sensing gate electrode 150 to perform a program operation. The threshold voltage (Vt) of single poly NVM (100) is increased. Conversely, when a negative VPP is applied to the fourth contact plug 370 and a positive VPP is applied to the second contact plug 270 during an erase operation, electrons in the sensing gate electrode 150 are transferred to the first P-type well region 110. It exits and performs an erasing operation.

Referring to Figure 7, the structure of Figure 7 is similar to Figure 6. The difference is that the thickness of the sensing gate insulating layer 130 and the control gate insulating layer 330 is thicker than the thickness of the selection gate insulating layer 230. In order to increase the thickness of the sensing gate insulating film 130 and the control gate insulating film 330, an ion implantation layer 120 of fluorine, phosphorus, boron, germanium, etc. is placed under the sensing gate insulating film 130 and the control gate insulating film 330, respectively. This is formed. On the other hand, the ion implantation layer 120 is not formed under the selection gate insulating layer 230.

The MV gate insulating films 35 and 37, the sensing gate insulating film 130, the selection gate insulating film 230, and the control gate insulating film 330 are formed simultaneously in one process as described above. As described above, the thickness of the sensing gate insulating layer 130 and the control gate insulating layer 330 on which the ion implantation layer 120 is formed may be thicker than the thickness of the MV gate insulating layers 35 and 37. On the other hand, the thickness of the selection gate insulating layer 230 and the MV gate insulating layer 35 and 37 without the ion implantation layer 120 is formed to be thinner than the thickness of the sensing gate insulating layer 130 and the control gate insulating layer 330.

As the thickness of the sensing gate insulating film 130 and the control gate insulating film 330 increases, the data preservation ability and retention of the MTP Cell improves. The selection gate insulating layer 230 has a small effect on the data retention ability, so it may be formed to the same thickness as the MV gate insulating layer 35 and 37. 6 and 7 , the thickness of the sensing gate insulating layer 130 may be the same as or thicker than the thickness of the selection gate insulating layer 230. In the end, it can be seen that the thickness of the gate insulating films 130 and 330 formed below the sensing gate electrode 150 and the control gate electrode 350, which are electrically connected to each other, is thicker than the thickness of the selection gate insulating film 230. there is.

8 and 9 are cross-sectional views of a non-volatile memory device according to another embodiment of the present invention.

Referring to FIG. 8, the NVM gate insulating films 39a, 39b, and 39c shown in FIGS. 2d and 4b may include first, second, third, and fourth NVM gate insulating films 130, 230, 330, and 530. You can. And the NVM gate electrodes 49a, 49b, and 49c shown in FIGS. 2D and 4B are the first, second, third, and fourth NVM gate insulating films 130, 230, 330, and 530, respectively. It may include 2nd, 3rd, and 4th NVM gate electrodes 150, 250, 350, and 550. Hereinafter, for convenience of explanation, the first, second, third, and fourth NVM gate insulating films 130, 230, 330, and 530 are respectively referred to as a sensing gate insulating film 130, a selection gate insulating film 230, and a control gate insulating film. It will be referred to as 330 and erase gate insulating film 530. And for convenience of explanation, the first, second, third, and fourth NVM gate electrodes 150, 250, 350, and 550 are respectively referred to as a sensing gate electrode 150, a selection gate electrode 250, and a control gate electrode ( 350) and an erase gate electrode 550. The sensing gate electrode 150 may also be called a program gate electrode. Except for the select gate electrode 250, the sensing gate electrode 150, the control gate electrode 350, and the erase gate electrode 550 are electrically connected to each other. The sensing gate electrode 150, the control gate electrode 350, and the erase gate electrode 550 can be electrically connected to each other using one floating gate electrode 400.

The thickness of the sensing gate insulating film 130, the selection gate insulating film 230, the control gate insulating film 330, and the erase gate insulating film 530 may be the same, and may be thicker than the thickness of the MV gate insulating films 35 and 37. It can be.

Referring to FIG. 9 , the thickness of the sensing gate insulating film 130, control gate insulating film 330, or erase gate insulating film 530 is thicker than the thickness of the selection gate insulating film 230. As described above, the thickness of the sensing gate insulating film 130, control gate insulating film 330, or erase gate insulating film 530 may be thicker than the thickness of the MV gate insulating films 35 and 37. On the other hand, the thickness of the selection gate insulating layer 230 may be the same as that of the MV gate insulating layers 35 and 37. As the thickness of the sensing gate insulating film 130 and the control gate insulating film 330 increases, the data preservation ability and retention of the MTP Cell improves. The selection gate insulating layer 230 has a small effect on the data retention ability, so it may be formed to the same thickness as the MV gate insulating layer 35 and 37.

Ultimately, the thickness of the gate insulating films 130, 330, and 530 formed below the sensing gate electrode 150, control gate electrode 350, and erase gate electrode 550, which are electrically connected to each other, is equal to the selection gate insulating film 230. ) can be seen to be thicker than the thickness of.

10A to 10G show a method of manufacturing a non-volatile memory device according to an embodiment of the present invention.

Referring to FIG. 10A, fluorine ion implantation is performed to form gate insulating films having different thicknesses on the substrate. First, a plurality of device isolation films 106 may be formed on the semiconductor substrate 105. The device isolation layer 106 is formed using Shallow Trench Isolation (STI) or LOCal Oxidation of Silicon (LOCOS). The DNW 107 can be formed by performing ion implantation into the semiconductor substrate. To increase the coupling ratio, a control gate ion implantation region 320 can be additionally formed in the second P-type well region 310 using boron (B) and indium (In) ions. The control gate ion implantation region 320 can be formed by sequentially implanting boron (B) and indium (In) ions. Alternatively, it can be formed by ion implanting only one of boron (B) ions or indium (In) ions. Boron ion (11B+) implantation can be performed with an ion implantation energy of 10 - 40 KeV and a dose of 1.0E11 - 1.0 E13/cm ² . And indium ions (Indium, 115In+) can be implanted at a dose of 100 - 300 KeV, 1.0E11 - 1.0E 13/cm ² . A mask pattern 125 may be formed on the substrate 105 that opens a partial area of the first P-type well region 110 and the second P-type well region 310 . Then, a fluorine (F) ion implantation process may be performed on the open area using a mask pattern to form first and second fluorine (F) ion implantation regions 120a and 120b that are spaced apart from each other. The fluorine (F) ion implantation process can form fluorine (F) ion implantation regions 120a and 120b by injecting energy of 1E12 - 1E15 atoms/cm ² and 5-30 KeV using fluorine (F) ions. there is. Instead of fluorine (F) ions, arsenic (As), argon (Ar), or phosphorus (P) ions can be implanted. When fluorine (F), arsenic (As), argon (Ar), or phosphorus (P) ions are implanted, the oxidation rate increases by up to three times during the subsequent oxidation process, so other parts of the surface of the ion implantation layer may appear. A thicker gate insulating film can be formed. In the present invention, fluorine (F) ions are implanted into the area where the sensing gate insulating film 130 and the control gate insulating film 330 will be formed. Afterwards, the mask pattern 125 is removed.

Referring to FIG. 10b, an oxidation process is performed at a high temperature of 750 ^o C or higher to form the gate insulating film. The sensing gate insulating layer 130, the selection gate insulating layer 230, and the control gate insulating layer 330 may be formed simultaneously. The sensing gate insulating layer 130 and the control gate insulating layer 330 may be formed as thick as 5 to 20 nm. The selection gate insulating layer 230 may have a thickness of 3 to 15 nm. The thickness of the sensing gate insulating layer 130 and the control gate insulating layer 330 is formed to be thicker than the thickness of the selection gate insulating layer 230. The difference in thickness of the gate insulating film is due to fluorine ion implantation, as explained previously. Conventionally, an additional oxidation process was required to adjust the thickness of some of the gate insulating films of the device, but when the manufacturing method of the non-volatile memory device of the present invention is applied, the ions of the ion implantation process are not additionally performed. By adjusting , the thickness of the gate insulating film can be adjusted, making it possible to simplify the process.

Referring to FIG. 10C, a conductive layer 140 is formed to form a gate electrode. Poly-silicon material can be used as the conductive layer 140. The poly-silicon layer can be formed as an amorphous silicon film doped through a low pressure chemical vapor deposition (LPCVD) process, or as an undoped amorphous silicon film. For example, the doped amorphous silicon film is formed using SiH ₄ or Si ₂ H ₆ and PH ₃ gas. An undoped amorphous silicon film is formed using SiH ₄ or Si ₂ H ₆ gas.

Referring to FIG. 10D, the conductive layer 140 is patterned to form a gate electrode. A sensing gate electrode 150, a selection gate electrode 250, and a control gate electrode 350 may be formed simultaneously on the sensing gate insulating film 130, the selection gate insulating film 230, and the control gate insulating film 330, respectively. The sensing gate electrode 150 and the control gate electrode 350 are part of the floating gate 400 and are physically and electrically connected to each other. The sensing gate electrode 150 and the control gate electrode 350 are gate electrodes made of a single poly-silicon film.

Referring to FIG. 10E, after forming the gate electrode, a plurality of well regions 110 and 310 are formed. Since the well regions 110 and 310 are formed by performing ion implantation using the gate electrode as a mask, the depth of the well regions 110 and 310 may be curved. The well regions 110 and 310 overlapping the gate electrode may be formed to be relatively thin. However, the well regions 110 and 310 that do not overlap the gate electrode may be formed relatively deep. The well regions 110 and 310 may be P-type well regions. Although not shown, various N-type or P-type LDD regions may be formed.

Although not shown, the well regions 110 and 310 may be formed in advance before the gate electrode. It can be preformed before fluorine ion implantation. A well region can be formed, fluorine ions can be implanted, and a gate insulating film and gate electrode can be formed.

Referring to FIG. 10F, spacers 411, 412, and 413 may be formed on both sides of the sensing gate electrode 150, the selection gate electrode 250, and the control gate electrode 350, respectively. And through high-concentration ion implantation, high-concentration doping regions, N+ regions (401, 402, 403, 404) and P+ regions (405, 406, 407), are formed on the substrate, respectively. To form N+ regions (401, 402, 403, 404), arsenic ions (75As+) are used to implant ions at 50-70 KeV ion implantation energy and 1E15-1E16/cm2 dose. Then, phosphorous ions (31P+) are used to implant ions at 30-50 KeV ion implantation energy and 1E12-1E14/cm2 dose. To form P+ regions (405, 406, 407), boron fluoride ions (49BF2) are used for ion implantation with 20-50 KeV ion implantation energy and 1E15-1E16/cm2 dose. Next, using boron ions (11B+), ion implantation is performed at 20-40KEV ion implantation energy and 1E12-1E14/cm2 dose. Because the N+ and P+ ion implantation energies are greater than the F ion implantation energies described above, the depth of the N+ and P+ ion implantation regions is smaller than the depth of the F ion implantation regions 120a and 120b. The N+ region 402 formed in the first P-type well region and on one side of the sensing gate electrode 150 is a drain region. And the N+ region 403 formed between the other side of the sensing gate electrode 150 and one side of the selection gate electrode 250 is both a source region and a drain region. The N+ region 404 formed on the other side of the selection gate electrode 250 is a source region. And the P+ region 405 formed in contact with the source region 404 is a pickup region of the first P-type well region. Additionally, the P+ regions 406 and 407 formed on both sides of the control gate electrode 350 and in the second PW 310 may be referred to as a pick up region. The second PW (310) and P+ regions (406, 407) are of the same conductivity type. Meanwhile, the drain region, source region, and pickup region described above are formed in the first P-type well region 110 and/or the second P-type well region 310.

Referring to FIG. 10G, contact plugs 170, 270, 290, 370, and 470 respectively connected to the N+ regions 401, 402, 403, and 404 or the P+ regions 405, 406, and 407 may be formed. And metal wires 601-606 connected to the contact plugs may be formed. The bit line BL may be electrically connected to the drain region 402 through the first contact plug 170. The source line SL may be electrically connected to the source area 404 and the pickup area 405 through the second contact plug 270 at the same time. The selection gate line SG may be connected to the selection gate electrode 250 through the third contact plug 290. The control gate line CG may be connected to the pickup areas 406 and 407 through the fourth contact plug 370. The sensing gate electrode 150 and the control gate electrode 350 may be connected to each other through a single piece of poly-silicon 701.

The method for manufacturing a non-volatile memory device according to the present application can control the thickness of the gate insulating film by controlling the ions of the ion implantation process without performing an additional separate oxidation process, making it possible to simplify the process. This solves the problem of requiring an additional oxidation process to adjust the thickness of some gate insulating films of conventional devices.

The non-volatile memory device using the manufacturing method of the present application can improve the durability of the device as well as the data preservation ability by improving the deterioration of the oxide as the device cycles by having separate program areas and erase areas.

Additionally, non-volatile memory devices can improve write and erase operation efficiency and reduce the area of the memory device.

The description of the present application described above is for illustrative purposes, and those skilled in the art will understand that the present application can be easily modified into other specific forms without changing its technical idea or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. For example, each component described as a single type may be implemented in a distributed form, and similarly, components described as distributed may also be implemented in a combined form.

The scope of the present application is indicated by the claims described below rather than the detailed description above, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present application.

11: Low voltage (LV) area
12: Medium voltage (MV) area
13: Non-Volatile Memory (NVM) area
25: Mask pattern
31, 33: LV gate insulation film
35, 37: MV gate insulating film
39: NVM gate insulation film
49: NVM gate electrode
105: semiconductor substrate
106: Trench area, device isolation membrane
107: Deep deep well region, DNW
108: N-type well region, NW
110, 310: first and second P-type well regions
120, 120a, 120b: first and second fluorine (F) ion implantation areas
130: Sensing gate insulating film
140: conductive layer
150: sensing gate
170, 270, 290: first, second and third contact plugs
230: Select gate insulating film
250: selection gate
320: Control gate ion implantation area
330: control gate insulating film
350: control gate
370: fourth contact plug
400: floating gate
401, 402, 403, 404: N+ area
405, 406, 407: P+ area
411, 412, 413: Spacer
530: erase gate insulating film
550: erase gate electrode
1301: Sensing transistor
1302: Select transistor
1303: Control gate structure

Claims (11)

first, second and third regions on a semiconductor substrate; and
Comprising first, second, and third semiconductor elements formed in the first, second, and third regions, respectively,
The first semiconductor device is
a first gate insulating film; and
It includes a first gate electrode formed on the first gate insulating film,
The second semiconductor device is
a second gate insulating layer thicker than the thickness of the first gate insulating layer; and
It includes a second gate electrode formed on the second gate insulating film,
The third semiconductor device is a non-volatile memory device,
a plurality of third gate insulating films;
a plurality of third gate electrodes each formed on the plurality of third gate insulating films;
an ion implantation layer for increasing the thickness of the plurality of third gate insulating layers;
A sensing transistor including a sensing gate insulating film and a sensing gate electrode;
A selection transistor including a selection gate insulating film and a selection gate electrode; and
A control gate structure including a control gate insulating film and a control gate electrode,
One of the plurality of third gate insulating films is formed thicker than the second gate insulating film,
A semiconductor device wherein the sensing gate insulating layer and the control gate insulating layer are formed to be thicker than the selection gate insulating layer.
According to claim 1,
Among the plurality of third gate electrodes, at least two gate electrodes are electrically connected to each other using a single piece of poly-silicon,
A semiconductor device in which the thickness of the third gate insulating film formed under each of the at least two gate electrodes is greater than the thickness of the third gate insulating film formed under the remaining one gate electrode.
According to claim 1,
A semiconductor device wherein one of the plurality of third gate insulating films is formed to have the same thickness as the second gate insulating film.
According to claim 1,
The first or second semiconductor device is characterized in that it is one of an SRAM device, a standard cell device, a logic device, a digital device, or an analog device,
The non-volatile memory device is one of electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), Flash memory, multiple time programmable (MTP) memory device, or one time programmable (OTP) memory device. Characterized semiconductor device.
According to claim 1,
The third semiconductor device is a single poly multi-time programmable non-volatile memory device,
A semiconductor device in which the sensing gate electrode of the sensing transistor and the control gate electrode of the control gate structure are electrically connected to each other.
In the step of forming a logic element and a non-volatile memory element on a semiconductor substrate,
selectively forming an ion implantation layer in an area where the non-volatile memory device is formed to increase the thickness of the gate insulating layer;
simultaneously forming a gate insulating layer of the logic device and a gate insulating layer of the non-volatile memory device; and
Forming gate electrodes on the gate insulating film of the logic device and the gate insulating film of the non-volatile memory device, respectively,
The thickness of the gate insulating film of the non-volatile memory device is thicker than the gate insulating film of the logic device,
The non-volatile memory element includes a sensing transistor, a selection transistor, and a control gate structure,
A semiconductor device manufacturing method, wherein the sensing gate insulating film of the sensing transistor and the control gate insulating film of the control gate structure are formed thicker than the selection gate insulating film of the selection transistor.
According to claim 6,
A method of manufacturing a semiconductor device in which the ion implantation layer uses a dopant containing any one of fluorine, arsenic, boron, germanium, or argon.
According to claim 6,
The non-volatile memory device is characterized in that it is a single poly multi-time programmable non-volatile memory device,
A semiconductor device manufacturing method in which the sensing gate electrode of the sensing transistor and the control gate electrode of the control gate structure are electrically connected to each other.
According to claim 6,
A semiconductor device manufacturing method wherein the sensing gate insulating film of the sensing transistor is formed to be thicker than the gate insulating film of the logic device.
According to claim 6,
After forming a gate electrode on the gate insulating film of the logic device and the gate insulating film of the non-volatile memory device, forming a well region of the logic device and a well region of the non-volatile memory device. Semiconductor device manufacturing method.
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