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KR100602120B1 - Semiconductor device and manufacturing method - Google Patents

Semiconductor device and manufacturing method Download PDF

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KR100602120B1
KR100602120B1 KR1020040074503A KR20040074503A KR100602120B1 KR 100602120 B1 KR100602120 B1 KR 100602120B1 KR 1020040074503 A KR1020040074503 A KR 1020040074503A KR 20040074503 A KR20040074503 A KR 20040074503A KR 100602120 B1 KR100602120 B1 KR 100602120B1
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copper
layer
gas
wiring
seed layer
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KR20060025718A (en
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정병현
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명의 목적은 반도체 소자의 구리 배선에서 확산배리어층에 의한 RC 지연 및 EM 특성 저하를 효과적으로 방지하는 것이다.An object of the present invention is to effectively prevent the RC delay and the EM characteristic degradation caused by the diffusion barrier layer in the copper wiring of the semiconductor device.

본 발명의 목적은 반도체 기판; 기판 상에 형성되고 기판을 일부 노출시키는 콘택홀 및 배선홀로 이루어진 다마신 구조가 구비된 층간절연막; 다마신 구조 표면에 순차적으로 형성된 배리어금속막 및 구리 시드층; 다마신 구조를 매립하면서 구리 시드층 상에 형성된 구리 배선; 및 구리 시드층과 구리 배선 표면에만 선택적으로 형성된 구리실리콘질화막의 확산배리어층을 포함하는 반도체 소자에 의해 달성될 수 있다.An object of the present invention is a semiconductor substrate; An interlayer insulating film formed on the substrate and having a damascene structure formed of a contact hole and a wiring hole to partially expose the substrate; A barrier metal film and a copper seed layer sequentially formed on the damascene structure surface; Copper wiring formed on the copper seed layer while embedding the damascene structure; And a diffusion barrier layer of a copper silicon nitride film selectively formed only on the copper seed layer and the copper wiring surface.

구리 배선, EM, 확산배리어층, 구실리콘질화막, 다마신 구조Copper wiring, EM, Diffusion barrier layer, old silicon nitride film, damascene structure

Description

반도체 소자 및 그 제조방법{Semiconductor device and method of manufacturing the same}Semiconductor device and method of manufacturing the same

도 1a 및 도 1b는 종래 반도체 소자의 구리 배선 형성방법을 설명하기 위한 단면도.1A and 1B are cross-sectional views for explaining a method of forming a copper wiring of a conventional semiconductor device.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 구리 배선 형성방법을 설명하기 위한 순차적 공정 단면도.2A to 2D are sequential process cross-sectional views for explaining a method of forming a copper wiring of a semiconductor device according to an embodiment of the present invention.

본 발명은 반도체 소자 및 그 제조방법에 관한 것으로, 특히 반도체 소자의 구리 배선 및 그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a copper wiring of a semiconductor device and a method of forming the same.

일반적으로, 배선 기술은 집적회로(Integrated Circuit; IC)에서 트랜지스터의 상호 연결회로, 전원공급 및 신호전달의 통로를 구현하는 기술을 말한다.In general, the wiring technology refers to a technology that implements the interconnection circuit of the transistor, the power supply and the signal transmission path in an integrated circuit (IC).

이러한 배선 재료로 주로 알루미늄(Al)을 사용하였지만, 반도체 소자의 고집적화 및 고속화 추세에 따른 선폭 감소로 인해 배선 및 콘택 저항이 증가하고 일렉트로마이크레이션(ElectroMigration; EM) 등의 문제가 야기되면서, 구리(Cu) 배선에 대한 연구가 활발히 진행되고 있다.Although aluminum (Al) is mainly used as such a wiring material, wire and contact resistance increase due to the high integration and high speed of semiconductor devices, and wiring and contact resistance increase, causing problems such as electromigration (EM). Research on Cu) wiring is being actively conducted.

구리는 알루미늄에 비해 약 62%의 낮은 저항을 가질 뿐만 아니라 EM에 대한 저항성이 커서 고집적 및 고속 소자에서 우수한 배선 신뢰성을 얻을 수 있다.Copper not only has a resistance of about 62% lower than that of aluminum, but also has high resistance to EM, which provides excellent wiring reliability in high-density and high-speed devices.

반면, 알루미늄과는 달리 건식식각이 불가능하기 때문에, 층간절연막에 콘택홀 및 배선홀을 포함하는 다마신 구조를 형성하는 듀얼 다마신(dual damascene) 공정에 의해 배선을 형성하여야 한다.On the other hand, unlike aluminum, dry etching is impossible, and thus wiring must be formed by a dual damascene process of forming a damascene structure including a contact hole and a wiring hole in the interlayer insulating layer.

이러한 종래 구리 배선 형성방법을 도 1a 및 도 1b를 참조하여 설명한다.This conventional copper wiring formation method will be described with reference to FIGS. 1A and 1B.

도 1a를 참조하면, 반도체 기판(10) 상에 층간절연막(11)을 형성하고, 공지된 듀얼 다마신 공정에 의해 층간절연막(11)을 패터닝하여, 기판(10)의 일부를 노출시키는 콘택홀(12a) 및 배선홀(12b)을 포함하는 다마신 구조(12)을 형성한다.Referring to FIG. 1A, a contact hole for forming an interlayer insulating film 11 on a semiconductor substrate 10 and patterning the interlayer insulating film 11 by a known dual damascene process to expose a portion of the substrate 10. A damascene structure 12 including a 12a and a wiring hole 12b is formed.

도 1b를 참조하면, 다마신 구조(12) 및 층간절연막(11) 표면 상에 탄탈륨질화막(TaN)의 배리어금속막(13)을 형성한다. 여기서, 배리어금속막(13)은 후속 구리 시드층(14) 및 구리 배선으로부터 층간절연막(11)으로 구리가 확산하는 것을 방지한다. 그 다음, 배리어금속막(13) 상부에 구리 시드층(14)을 형성하고, 구리 시드층(14) 상에 다마신 구조(12)를 매립하도록 구리층을 형성한다.Referring to FIG. 1B, a barrier metal film 13 of a tantalum nitride film TaN is formed on the surface of the damascene structure 12 and the interlayer insulating film 11. Here, the barrier metal film 13 prevents the diffusion of copper from the subsequent copper seed layer 14 and the copper wiring to the interlayer insulating film 11. Next, a copper seed layer 14 is formed on the barrier metal film 13, and a copper layer is formed to bury the damascene structure 12 on the copper seed layer 14.

그 후, 화학기계연마(Chemical Mechanical Polishing; CMP)에 의해 층간절연막(11)이 노출되도록 구리층, 구리 시드층(14) 및 배리어금속막(13)을 제거하여 구리 배선(15)을 형성함과 동시에 표면을 평탄화한다. 그 다음, 기판 전면 상에 실리콘질화막(SiN)의 확산배리어층(16)을 형성한다. 여기서, 확산배리어층(16)은 구리 배선(14)으로부터 후속 형성되는 상부 층간절연막으로 구리가 확산하는 것을 방지한다.Thereafter, the copper layer 15 is removed by removing the copper layer, the copper seed layer 14 and the barrier metal layer 13 so that the interlayer insulating layer 11 is exposed by chemical mechanical polishing (CMP). And at the same time planarize the surface. Then, the diffusion barrier layer 16 of the silicon nitride film (SiN) is formed on the entire substrate. Here, the diffusion barrier layer 16 prevents the diffusion of copper from the copper wiring 14 to the upper interlayer insulating film subsequently formed.

그런데, 실리콘질화막의 확산배리어층(16)은 유전상수(k)가 7 정도로 매우 큰 값을 갖기 때문에 배선의 RC 지연(delay)을 야기시킬 뿐만 아니라, 구리 배선(14)과의 접착력(adheseion)이 매우 열악하기 때문에 후속 공정 시 박리될 가능성이 높아 EM 특성을 악화시킴으로써, 결국 배선의 신뢰성을 저하시키게 된다.However, since the diffusion barrier layer 16 of the silicon nitride film has a very large dielectric constant k of about 7, it causes not only the RC delay of the wiring but also the adhesion with the copper wiring 14. Since this is very poor, there is a high possibility of peeling in a subsequent process, which deteriorates EM characteristics, which in turn lowers the reliability of the wiring.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위한 것으로, 반도체 소자의 구리 배선에서 확산배리어층에 의한 RC 지연 및 EM 특성 저하를 효과적으로 방지하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object thereof is to effectively prevent RC delay and EM characteristic degradation caused by a diffusion barrier layer in a copper wiring of a semiconductor device.

상기한 바와 같은 본 발명의 목적은 반도체 기판; 기판 상에 형성되고 기판을 일부 노출시키는 콘택홀 및 배선홀로 이루어진 다마신 구조가 구비된 층간절연막; 다마신 구조 표면에 순차적으로 형성된 배리어금속막 및 구리 시드층; 다마신 구조를 매립하면서 구리 시드층 상에 형성된 구리 배선; 및 구리 시드층과 구리 배선 표면에만 선택적으로 형성된 구리실리콘질화막의 확산배리어층을 포함하는 반도체 소자에 의해 달성될 수 있다.An object of the present invention as described above is a semiconductor substrate; An interlayer insulating film formed on the substrate and having a damascene structure formed of a contact hole and a wiring hole to partially expose the substrate; A barrier metal film and a copper seed layer sequentially formed on the damascene structure surface; Copper wiring formed on the copper seed layer while embedding the damascene structure; And a diffusion barrier layer of a copper silicon nitride film selectively formed only on the copper seed layer and the copper wiring surface.

또한, 본 발명의 목적은 반도체 기판 상에 기판의 일부를 노출시키는 콘택홀 및 배선홀로 이루어진 다마신 구조를 구비한 층간절연막을 형성하는 단계; 다마신 구조 및 층간절연막 표면 상에 배리어금속막과 구리 시드층을 순차적으로 형성하는 단계; 다마신 구조를 매립하도록 구리 시드층 상에 구리층을 형성하는 단계; 층간절연막이 노출되도록 구리층, 구리 시드층 및 배리어금속막을 제거하여 구리층으로 이루어진 구리 배선을 형성함과 동시에 표면을 평탄화하는 단계; 및 구리 시드층 및 구리 배선 표면에만 구리실리콘질화막의 확산배리어층을 선택적으로 형성하는 단계를 포함하는 반도체 소자의 제조방법에 의해 달성될 수 있다.In addition, an object of the present invention is to form an interlayer insulating film having a damascene structure consisting of a contact hole and a wiring hole to expose a portion of the substrate on the semiconductor substrate; Sequentially forming a barrier metal film and a copper seed layer on the damascene structure and the interlayer insulating film surface; Forming a copper layer on the copper seed layer to bury the damascene structure; Removing the copper layer, the copper seed layer and the barrier metal film so as to expose the interlayer insulating film, thereby forming a copper wiring made of the copper layer and simultaneously planarizing the surface; And selectively forming a diffusion barrier layer of a copper silicon nitride film only on the copper seed layer and the copper wiring surface.

여기서, 확산배리어층은 SiH4 가스와 NH3/N2 가스를 이용하여 플라즈마 처리에 의해 형성하는데, 이때 챔버의 온도는 300 내지 400℃로 조절하고, RF 파워는 50 내지 300W로 조절한다.Here, the diffusion barrier layer is formed by plasma treatment using SiH 4 gas and NH 3 / N 2 gas, wherein the temperature of the chamber is adjusted to 300 to 400 ° C., and the RF power is adjusted to 50 to 300W.

또한, 플라즈마 처리는 10 내지 40 초 동안 상기 SiH4 가스를 100 내지 300sccm의 유량으로 주입한 후, NH3/N2의 혼합가스를 1 : 5의 비율로 주입하여 수행하거나, 20 내지 50초 동안 SiH4/N2/NH3의 혼합가스를 동시에 5 : 5 : 1의 비율로 주입하여 수행한다.In addition, the plasma treatment may be performed by injecting the SiH 4 gas at a flow rate of 100 to 300 sccm for 10 to 40 seconds, and then injecting a mixed gas of NH 3 / N 2 at a ratio of 1: 5 or for 20 to 50 seconds. The mixture gas of SiH 4 / N 2 / NH 3 is simultaneously injected at a ratio of 5: 5: 1.

이하, 본 발명이 속한 기술 분야에서 통상의 지식을 가진 자가 본 발명을 보다 더 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily implement the present invention.

도 2a 내지 도 2d를 참조하여 본 발명의 실시예에 따른 반도체 소자의 구리 배선 형성방법을 설명한다.A method of forming copper wirings of a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2A to 2D.

도 2a를 참조하면, 반도체 기판(20) 상에 제 1 층간절연막(21)을 형성하고, 공지된 듀얼 다마신 공정에 의해 제 1 층간절연막(21)을 패터닝하여, 기판(20)의 일부를 노출시키는 콘택홀(22a) 및 배선홀(22b)을 포함하는 다마신 구조(22)을 형성한다.Referring to FIG. 2A, the first interlayer insulating film 21 is formed on the semiconductor substrate 20, and the first interlayer insulating film 21 is patterned by a known dual damascene process to partially remove the substrate 20. A damascene structure 22 including a contact hole 22a and a wiring hole 22b to be exposed is formed.

도 2b를 참조하면, 다마신 구조(22) 및 제 1 층간절연막(21) 표면 상에 탄탈륨질화막(TaN)의 배리어금속막(23)을 형성한다. 여기서, 배리어금속막(23)은 이후 형성될 구리 시드층 및 구리 배선으로부터 층간절연막(21) 내로 구리가 확산하는 것을 방지한다. 그 다음, 배리어금속막(23) 상부에 구리 시드층(24)을 형성하고, 구리 시드층(24) 상에 다마신 구조(22)를 매립하도록 구리층을 형성한다. 그 후, CMP에 의해 제 1 층간절연막(21)이 노출되도록 구리층, 구리 시드층(24) 및 배리어금속막(23)을 제거하여 하부 구리 배선(25)을 형성함과 동시에 표면을 평탄화한다. Referring to FIG. 2B, a barrier metal film 23 of a tantalum nitride film TaN is formed on the surfaces of the damascene structure 22 and the first interlayer insulating film 21. Here, the barrier metal film 23 prevents copper from diffusing into the interlayer insulating film 21 from the copper seed layer and the copper wiring to be formed later. Next, a copper seed layer 24 is formed on the barrier metal film 23, and a copper layer is formed to bury the damascene structure 22 on the copper seed layer 24. Thereafter, the copper layer, the copper seed layer 24, and the barrier metal film 23 are removed to expose the first interlayer insulating film 21 by CMP, thereby forming the lower copper wiring 25 and planarizing the surface thereof. .

그 다음, 하부 구리 배선(25)이 형성된 기판을 SiH4, NH3/N2 가스를 이용하여 플라즈마 처리(26)하여, 도 2c에 도시된 바와 같이, 구리 시드층(24) 및 하부 구리 배선(25) 표면에만 선택적으로 100 내지 500Å 두께로 구리실리콘질화막(CuSiN)의 확산배리어층(27)을 형성한다. Subsequently, the substrate on which the lower copper wiring 25 is formed is plasma-treated 26 using SiH 4 , NH 3 / N 2 gas, and as shown in FIG. 2C, the copper seed layer 24 and the lower copper wiring. (25) A diffusion barrier layer 27 of a copper silicon nitride film (CuSiN) is formed to a thickness of only 100 to 500 GPa selectively.

여기서, 플라즈마 처리(26)는 챔버의 온도를 300 내지 400℃로 조절하고, 구리실리콘질화막(CuSiN)이 구리 시드층(24) 및 하부 구리 배선(25) 표면에만 형성되도록 RF 파워를 50 내지 300W로 조절하여 수행한다.Here, the plasma treatment 26 controls the temperature of the chamber to 300 to 400 ° C., and the RF power is 50 to 300 W so that the copper silicon nitride film (CuSiN) is formed only on the surface of the copper seed layer 24 and the lower copper wiring 25. Adjust to.

또한, 플라즈마 처리(26)는 SiH4 가스와 NH3/N2 가스를 순차적으로 또는 동시에 주입하여 구리 시드층(24) 및 하부 구리 배선(25) 표면에 구리실리콘질화막(CuSiN)을 형성하는 과정으로 수행하는데, SiH4 가스와 NH3/N2 가스를 순차적으로 주입하는 경우에는, 10 내지 40 초 동안 SiH4 가스를 100 내지 300sccm의 유량으로 주 입한 후, NH3/N2의 혼합가스를 1 : 5의 비율, 바람직하게는 NH3 가스는 20 내지 60sccm의 유량으로 N2 가스는 100 내지 300sccm의 유량으로 주입하고, SiH4 가스와 NH3/N2 가스를 순차적으로 주입하는 경우에는, 20 내지 50초 동안 SiH4/N 2/NH3의 혼합가스를 5 : 5 : 1의 비율, 바람직하게는 SiH4 가스와 N2 가스는 각각 100 내지 300sccm의 유량으로 NH3 가스는 20 내지 60sccm의 유량으로 주입한다.In addition, the plasma treatment 26 injects SiH 4 gas and NH 3 / N 2 gas sequentially or simultaneously to form a copper silicon nitride film (CuSiN) on the surface of the copper seed layer 24 and the lower copper wiring 25. when injecting, SiH 4 gas and NH 3 / N 2 gas for carrying out in sequence, the 10 to then imported state the SiH 4 gas at a flow rate of 100 to 300sccm for 40 seconds, a mixed gas of NH 3 / N 2 When a ratio of 1: 5, preferably NH 3 gas is injected at a flow rate of 20 to 60 sccm, N 2 gas is injected at a flow rate of 100 to 300 sccm, and SiH 4 gas and NH 3 / N 2 gas are sequentially injected, For 20 to 50 seconds, the mixed gas of SiH 4 / N 2 / NH 3 is in a ratio of 5: 5: 1, preferably, the SiH 4 gas and the N 2 gas are 100 to 300 sccm, respectively, and the NH 3 gas is 20 to 60 sccm. Inject at a flow rate of.

또한, 상술한 플라즈마 처리(26)에 의해 구리실리콘질화막의 확산배리어층(27)을 형성하기 전에, 챔버 내부로 NH3 가스를 5 내지 20초 동안 50 내지 100sccm의 유량으로 주입하여 구리 시드층(24) 및 하부 구리 배선(25) 표면의 구리산화막(CuO)을 제거할 수도 있다.In addition, before forming the diffusion barrier layer 27 of the copper silicon nitride film by the above-described plasma treatment 26, NH 3 gas is injected into the chamber at a flow rate of 50 to 100 sccm for 5 to 20 seconds to form a copper seed layer ( 24 and the copper oxide film CuO on the surface of the lower copper wiring 25 may be removed.

도 2d를 참조하면, 기판 전면 상에 제 2 층간절연막(28)을 형성하고, 듀얼 다마신 공정에 의해 제 2 층간절연막(28)과 확산배리어층(27)을 패터닝하여, 하부 구리 배선(25)의 일부를 노출시키는 콘택홀 및 배선홀을 포함하는 다마신 구조를 혀성한다. 그 다음, 다마신 구조 및 제 2 층간절연막(28) 표면 상에 탄탈륨질화막(TaN)의 배리어금속막(29)과 구리 시드층(30)을 순차적으로 형성하고, 다마신 구조를 매립하도록 구리 시드층(30) 상에 구리층을 형성한다. 그 후, CMP에 의해 제 2 층간절연막(28)이 노출되도록 구리층, 구리 시드층(30) 및 배리어금속막(29)을 제거하여 하부 구리 배선(25)과 콘택하는 상부 구리 배선(31)을 형성함과 동시에 표면을 평탄화한다. Referring to FIG. 2D, a second interlayer insulating film 28 is formed on the entire surface of the substrate, and the second interlayer insulating film 28 and the diffusion barrier layer 27 are patterned by a dual damascene process to form a lower copper wiring 25. A damascene structure including a contact hole and a wiring hole exposing a portion of the top face is formed. Next, the barrier metal film 29 of the tantalum nitride film TaN and the copper seed layer 30 are sequentially formed on the surface of the damascene structure and the second interlayer insulating film 28, and the copper seed is embedded to fill the damascene structure. A copper layer is formed on layer 30. Thereafter, the copper layer, the copper seed layer 30, and the barrier metal film 29 are removed to expose the second interlayer insulating film 28 by CMP, and the upper copper wiring 31 in contact with the lower copper wiring 25 is formed. While forming a planarization of the surface.

상술한 바와 같이, 본 발명에서는 플라즈마 처리에 의해 구리 시드층 및 구리 배선 표면에만 구리실리콘질화막의 확산배리어층을 형성한다.As described above, in the present invention, the diffusion barrier layer of the copper silicon nitride film is formed only on the copper seed layer and the copper wiring surface by plasma treatment.

이에 따라, 확산배리어층에 의한 RC 지연을 방지할 수 있을 뿐만 아니라 구리 배선과 확산배리어층 사이의 접착력을 개선할 수 있으므로 EM 특성 저하를 방지할 수 있다.As a result, not only the RC delay caused by the diffusion barrier layer can be prevented, but also the adhesion between the copper wiring and the diffusion barrier layer can be improved, so that the EM characteristic degradation can be prevented.

그 결과, 배선의 신뢰성을 향상시킬 수 있다.As a result, the reliability of the wiring can be improved.

이상에서 설명한 본 발명은 전술한 실시예 및 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those who have knowledge.

Claims (11)

반도체 기판;Semiconductor substrates; 상기 기판 상에 형성되고 상기 기판을 일부 노출시키는 콘택홀 및 배선홀로 이루어진 다마신 구조가 구비된 층간절연막;An interlayer insulating film formed on the substrate and having a damascene structure formed of a contact hole and a wiring hole to partially expose the substrate; 상기 다마신 구조 표면에 순차적으로 형성된 배리어금속막 및 구리 시드층;A barrier metal layer and a copper seed layer sequentially formed on the damascene structure surface; 상기 다마신 구조를 매립하면서 상기 구리 시드층 상에 형성된 구리 배선; 및 A copper wiring formed on the copper seed layer while filling the damascene structure; And 상기 구리 시드층과 구리 배선 표면에만 선택적으로 형성된 확산배리어층Diffusion barrier layer selectively formed only on the copper seed layer and the copper wiring surface 을 포함하며,Including; 상기 확산배리어층은 구리실리콘질화막(CuSiN)으로 이루어진 반도체 소자.The diffusion barrier layer is a semiconductor device consisting of a copper silicon nitride film (CuSiN). 삭제delete 반도체 기판 상에 상기 기판의 일부를 노출시키는 콘택홀 및 배선홀로 이루어진 다마신 구조를 구비한 층간절연막을 형성하는 단계;Forming an interlayer insulating film having a damascene structure comprising a contact hole and a wiring hole exposing a portion of the substrate on a semiconductor substrate; 상기 다마신 구조 및 층간절연막 표면 상에 배리어금속막과 구리 시드층을 순차적으로 형성하는 단계;Sequentially forming a barrier metal layer and a copper seed layer on the damascene structure and the interlayer dielectric layer; 상기 다마신 구조를 매립하도록 상기 구리 시드층 상에 구리층을 형성하는 단계; Forming a copper layer on the copper seed layer to bury the damascene structure; 상기 층간절연막이 노출되도록 상기 구리층, 구리 시드층 및 배리어금속막을 제거하여 상기 구리층으로 이루어진 구리 배선을 형성함과 동시에 표면을 평탄화하는 단계; 및 Removing the copper layer, the copper seed layer, and the barrier metal film to expose the interlayer insulating film to form a copper wiring made of the copper layer and planarize the surface thereof; And 상기 구리 시드층 및 구리 배선 표면에만 구리실리콘질화막의 확산배리어층을 선택적으로 형성하는 단계를 포함하는 반도체 소자의 제조방법.Selectively forming a diffusion barrier layer of a copper silicon nitride film only on the copper seed layer and the copper wiring surface. 제 3 항에 있어서, The method of claim 3, wherein 상기 확산배리어층은 SiH4 가스와 NH3/N2 가스를 이용한 플라즈마 처리에 의해 형성하는 반도체 소자의 제조방법.The diffusion barrier layer is formed by a plasma treatment using a SiH 4 gas and NH 3 / N 2 gas. 제 4 항에 있어서, The method of claim 4, wherein 상기 플라즈마 처리는 챔버의 온도를 300 내지 400℃로 조절하고, RF 파워를 50 내지 300W로 조절하여 수행하는 반도체 소자의 제조방법.The plasma treatment is performed by adjusting the temperature of the chamber to 300 to 400 ℃, RF power to 50 to 300W. 제 4 항 또는 제 5 항에 있어서, The method according to claim 4 or 5, 상기 플라즈마 처리는 10 내지 40 초 동안 상기 SiH4 가스를 100 내지 300sccm의 유량으로 주입한 후, NH3/N2의 혼합가스를 1 : 5의 비율로 주입하여 수행하는 반도체 소자의 제조방법.The plasma treatment is performed by injecting the SiH 4 gas at a flow rate of 100 to 300sccm for 10 to 40 seconds, and then injecting a mixed gas of NH 3 / N 2 in a ratio of 1: 5. 제 6 항에 있어서, The method of claim 6, 상기 NH3 가스는 20 내지 60sccm의 유량으로 주입하고 상기 N2 가스는 100 내지 300sccm의 유량으로 주입하는 반도체 소자의 제조방법.The NH 3 gas is injected at a flow rate of 20 to 60sccm and the N 2 gas is injected into a flow rate of 100 to 300sccm. 제 4 항 또는 제 5 항에 있어서, The method according to claim 4 or 5, 상기 플라즈마 처리는 20 내지 50초 동안 SiH4/N2/NH3의 혼합가스를 5 : 5 : 1의 비율로 동시에 주입하여 수행하는 반도체 소자의 제조방법.The plasma treatment method is performed by simultaneously injecting a mixed gas of SiH 4 / N 2 / NH 3 in a ratio of 5: 5: 1 for 20 to 50 seconds. 제 8 항에 있어서, The method of claim 8, 상기 SiH4 가스와 N2 가스는 각각 100 내지 300sccm의 유량으로 주입하고 상기 NH3 가스는 20 내지 60sccm의 유량으로 주입하는 반도체 소자의 제조방법.The SiH 4 gas and N 2 gas are injected at a flow rate of 100 to 300 sccm, respectively, and the NH 3 gas is injected into a flow rate of 20 to 60 sccm. 제 3 항에 있어서, The method of claim 3, wherein 상기 확산배리어층은 100 내지 500Å 두께로 형성하는 반도체 소자의 제조방법.The diffusion barrier layer is a manufacturing method of a semiconductor device to form a thickness of 100 to 500Å. 제 5 항에 있어서, The method of claim 5, 상기 확산배리어층을 형성하기 전에, 상기 챔버 내부로 NH3 가스를 5 내지 20초 동안 50 내지 100sccm의 유량으로 주입하여 상기 구리 시드층 및 구리 배선 표면에 발생된 구리산화막을 제거하는 반도체 소자의 제조방법.Before forming the diffusion barrier layer, manufacturing a semiconductor device to remove the copper oxide film generated on the surface of the copper seed layer and the copper wiring by injecting NH 3 gas at a flow rate of 50 to 100 sccm for 5 to 20 seconds into the chamber. Way.
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