KR100924555B1 - Metal wiring of semiconductor device and method of forming the same - Google Patents

Abstract

The present invention discloses a metal interconnection of a semiconductor device and a method of forming the same, which can improve contact resistance by preventing diffusion between upper and lower interconnections. Metal wiring of the semiconductor device according to the present invention, the lower metal wiring formed on the semiconductor substrate; An insulating film formed on the semiconductor substrate and having a wiring formation region exposing at least a portion of the lower metal wiring; A diffusion barrier film formed on a surface of a wiring formation region of the insulating film and including a multilayer structure of a Ta _x N _y film, a Ta _x B _y N _z film, a Ti _x B _y N _z film, and a Ti _x N _y film; And an upper metal wiring formed on the diffusion barrier to fill the wiring forming region of the insulating film.

Description

Metal Wiring of Semiconductor Devices and Forming Method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to metal wiring of semiconductor devices and methods of forming the same, and more particularly, to metal wiring of semiconductor devices and a method of forming the same, which can improve contact resistance by preventing diffusion between upper and lower wirings.

In general, a metal wiring is formed in the semiconductor device to electrically connect the device and the device, or the wiring and the wiring, and a damascene process has been proposed as a process for forming the metal wiring. In the damascene process, a trench is formed by etching an insulating layer, and then the trench is embedded with a conductive material such as tungsten (W), aluminum (Al), copper (Cu), and the like to form a metal wiring. When aluminum is applied as the conductive material, a film having a Ti / TiN laminated structure is formed as a diffusion barrier film and a wetting film.

Meanwhile, as the trend toward higher integration of semiconductor devices is intensified, copper, which is capable of solving the RC signal delay problem in high-density high-speed operation devices, has much higher electrical conductivity and lower resistance than the aluminum and tungsten in the fabrication of semiconductor devices that have become finer. Research into using as a wiring material is in progress.

When copper is applied as the conductive material, diffusion of the copper component into the semiconductor substrate is caused through the insulating film. Since the diffused copper component acts as a deep level impurity in a semiconductor substrate made of silicon to cause a leakage current, a diffusion barrier must be formed at the contact interface between the copper and the insulating layer. The diffusion barrier is usually formed of a single film or a double film structure of a Ta film and a TaN film.

However, the application of copper as the conductive material to all the wiring formation regions of the semiconductor device is not appropriate in terms of device characteristics and manufacturing cost increase. Therefore, when manufacturing a semiconductor device having a multi-layered metal wiring structure, the wiring layer that plays a role of signal transmission uses copper because speed is important, and a wiring layer whose main role is to supply power, which is relatively less important, is used. A method of using aluminum is being developed.

For example, a method has been proposed in which the lower metal interconnection is formed of a copper film, and the contact between the upper and lower metal interconnections and the upper metal interconnection are formed of an aluminum film. In this case, a diffusion barrier layer having a Ta / TaN layer structure is formed at an interface between the copper layer and the insulating layer when the lower metal line is formed, and an interface between the aluminum layer and the insulating layer and between the aluminum layer and the copper layer when the upper metal line is formed. A diffusion barrier film having a Ti / TiN laminated structure is formed on the substrate.

However, the above-described prior art has poor diffusion preventing properties of the Ti / TiN laminated structure applied during the formation of the upper metal wiring, causing mutual diffusion between the copper film and the aluminum film. As a result, a compound of two metal films is formed at the interface between the copper film and the aluminum film. Therefore, the contact resistance between the upper and lower metal wirings is lowered, resulting in deterioration of device characteristics.

The present invention provides a metal wiring of a semiconductor device and a method of forming the same that can prevent diffusion between upper and lower wirings.

In addition, the present invention provides a metal wiring and a method of forming the semiconductor device capable of improving the contact resistance.

Metal wiring of the semiconductor device according to an embodiment of the present invention, the lower metal wiring formed on the semiconductor substrate; An insulating film formed on the semiconductor substrate and having a wiring formation region exposing at least a portion of the lower metal wiring; A diffusion barrier film formed on a surface of a wiring formation region of the insulating film and including a multilayer structure of a Ta _x N _y film, a Ta _x B _y N _z film, a Ti _x B _y N _z film, and a Ti _x N _y film; And an upper metal wiring formed on the diffusion barrier to fill the wiring forming region of the insulating film.

The lower metal wiring includes a copper film.

The Ta _x B _y N _z film has an amorphous phase.

The _{x of} the Ta _x N _y film has a range of 0.4 to 0.7, and y has a range of 0.3 to 0.6.

_{X of} the Ta _x B _y N _z film has a range of 0.3 to 0.7, y has a range of 0.1 to 0.3, and z has a range of 0.2 to 0.4.

_{X of} the Ti _x B _y N _z film has a range of 0.3 to 0.7, y has a range of 0.1 to 0.3, and z has a range of 0.2 to 0.4.

The _{x of} the Ti _x N _y film has a range of 0.4 to 0.7, and y has a range of 0.3 to 0.6.

The upper metal wiring includes an aluminum film.

Method of forming a metal wiring of the semiconductor device according to an embodiment of the present invention, forming a lower metal wiring on the semiconductor substrate; Forming an insulating film having a wiring formation region exposing at least a portion of the lower metal wiring on the semiconductor substrate; Forming a diffusion barrier film including a multilayer structure of a Ta _x N _y film, a Ta _x B _y N _z film, a Ti _x B _y N _z film, and a Ti _x N _y film on the insulating film including the surface of the wiring forming region; And forming an upper metal wiring on the diffusion barrier to fill the wiring formation region.

The lower metal wiring includes a copper film.

The Ta _x B _y N _z film is formed of a film having an amorphous phase.

The Ta _x N _y film is formed of a film having x in the range of 0.4 to 0.7 and y in the range of 0.3 to 0.6.

The Ta _x B _y N _z film is formed of a film in which x has a range of 0.3 to 0.7, y has a range of 0.1 to 0.3, and z has a range of 0.2 to 0.4.

The Ti _x B _y N _z film is formed of a film in which x has a range of 0.3 to 0.7, y has a range of 0.1 to 0.3, and z has a range of 0.2 to 0.4.

The Ti _x N _y film is formed of a film having x in the range of 0.4 to 0.7 and y in the range of 0.3 to 0.6.

The forming of the diffusion barrier layer may include forming a Ta _x N _y film on an insulating film including a surface of the wiring forming region; Penetrating boron on the surface of the Ta _x N _y film to form a Ta _x B _y N _z film; Forming a Ti _x N _y film on the Ta _x B _y N _z film; And forming an interface layer on Ti _x B _y N _z between the Ta _x B _y N _z of boron in the film and the Ti _x N _y by reacting a film the Ta _x B _y N _z layer and the Ti _x N _y film; It includes.

The Ta _x N _y film is formed by a sputtering method.

The Ta _x N _y film is formed to have a crystalline phase.

The boron infiltration is performed by heat treatment or plasma treatment using boron-based gas.

The heat treatment is carried out under a temperature condition of 300 to 600 ℃.

The boron-based gas uses B ₂ H ₆ , or BCl ₃ .

The Ta _x B _y N _z film is formed to have an amorphous phase.

The Ti _x N _y film is a Ti-rich TiN film.

The reaction of boron in the Ta _x B _y N _z film and the Ti _x N _y film is performed by heat treatment.

The upper metal wiring includes an aluminum film.

According to the present invention, a diffusion barrier layer including a multilayer structure of TaN / TaBN / TiBN / TiN is formed at an interface between the lower metal interconnection and the upper metal interconnection when the copper and aluminum layers are applied as the lower metal interconnection and the upper metal interconnection, respectively. By doing so, the characteristics of the diffusion barrier can be improved.

In addition, the present invention by forming a diffusion barrier film having a multi-layer structure of TaN / TaBN / TiBN / TiN as described above, it is possible to prevent the generation of the compound due to the diffusion between the upper and lower metal wiring, thereby preventing the increase in contact resistance The contact resistance can be improved.

In addition, the present invention forms a wetting film on the diffusion barrier film including the multilayer structure of TaN / TaBN / TiBN / TiN, thereby forming the upper metal wiring stably and easily at the time of forming the upper metal wiring made of the aluminum film. Can be done.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a cross-sectional view illustrating a metal wiring of a semiconductor device according to an embodiment of the present invention.

As illustrated, an interlayer insulating film 102 and an abrasive stop film 104 are sequentially formed on the semiconductor substrate 100, and a lower metal wiring is formed in the interlayer insulating film 102 including the abrasive stop film 104. A first wiring formation region D1 to be formed is formed, and a lower metal wiring 108 is formed in the first wiring formation region D1. In this case, the lower metal wiring 108 is formed of a copper film. A TaN / Ta film 106 is formed on the surface of the first wiring region D1 of the interlayer insulating film 102 on which the lower metal wiring 108 is formed.

In addition, the capping film 110 and the insulating film 112 are sequentially formed on the polishing stop film 104 including the lower metal wiring 108, and the lower metal wiring in the insulating film 112 including the capping film 110. A second wiring formation region D2 exposing the 108 is formed, and an upper metal wiring 124 is formed on the insulating film 112 including the second wiring formation region D2. In this case, the upper metal wiring 124 is formed of an aluminum film.

Here, the TaN film 114, the TaBN film 116, the TiBN film 120, and the TiN film 118 are formed on the surface of the second wiring formation region D2 of the insulating film 112 on which the upper metal wiring 124 is formed. A diffusion barrier film 122 is formed that includes the sequentially stacked multilayer structure. The TaN film 114 and the TaBN film 116 of the diffusion barrier 122 serve as a diffusion barrier of the lower metal wiring 108, and the TiBN film 120 and the TiN film 118 are the upper metal wiring. It serves as a diffusion barrier of 124, the TiN film 118 may serve as a wetting film of the aluminum film.

The TaBN film 116 has an amorphous phase. The TaN film 114 is preferably a Ta _x N _y film (0.4 ≦ _x ≦ 0.7, 0.3 ≦ _y ≦ 0.6), and the TaBN film 116 is preferably a Ta _x B _y N _z film. (0.3 ≦ _x ≦ 0.7, 0.1 ≦ _y ≦ 0.3, 0.2 ≦ _z ≦ 0.4), and the TiBN film 120 is preferably a Ti _x B _y N _z film (0.3 ≦ _x ≦ 0.7, 0.1 ≦ _y ≦ 0.3, 0.2 ≦ z ≦ 0.4, and the TiN film 118 is preferably a Ti _x N _y film (0.4 ≦ _x ≦ 0.7, 0.3 ≦ _y ≦ 0.6).

In addition, the first wiring formation region D1 in which the lower metal wiring 108 is formed may include a trench structure according to a single damascene process or a dual damascene process, or a trench and at least one via hole connected to the trench. The trench and via hole structures may be formed. In this case, the second wiring formation region D2 in which the upper metal wiring 124 is formed may be formed in a via hole structure.

In the metal wiring of the present invention, the TaN film 114, the TaBN film 116, the TiBN film 120, and the TiN film 118 are sequentially stacked on the contact interface between the lower metal wiring 108 and the upper metal wiring 124. Since the diffusion barrier 122 including the multilayered structure is formed, the characteristics of the diffusion barrier 122 itself is improved. Therefore, the present invention can effectively prevent the formation of a high resistance compound at the contact interface between the lower metal wiring 108 and the upper metal wiring 124 due to the diffusion of aluminum, which is the upper metal wiring 124 material. As a result, the present invention can prevent the increase in contact resistance between the lower metal wiring 108 and the upper metal wiring 124, thereby improving the contact resistance.

In addition, according to the present invention, the TiN film 118 of the diffusion barrier film 122 serves as a wetting film of an aluminum film, thereby forming a process of forming the upper metal wiring 124 when the upper metal wiring 124 is formed. It can be performed easily.

2A to 2G are cross-sectional views illustrating processes for forming a metal wiring of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, an interlayer insulating layer 102 is formed on an upper portion of a semiconductor substrate 100 including lower structures such as gates and bit lines to cover the lower structure, and the interlayer insulating layer 102 is formed. An abrasive stop film 104 is formed on the substrate.

Then, the interlayer insulating film 102 and the polishing stop film 104 are etched to form a first wiring forming region D1 in which a lower metal wiring is to be formed. The first wiring formation region D1 may be formed in a single structure made of a trench or a dual structure including a trench and a via hole.

Referring to FIG. 2B, a TaN / Ta film 106 is formed on the surface of the first wiring forming region D1 including the polishing stop film 104 to serve as a diffusion barrier film of copper, and the TaN / A seed film (not shown) for embedding the metal film is formed on the Ta film 106. Subsequently, a lower metal wiring metal film 108a is formed on the seed film to fill the first wiring formation region D1. The upper metal wiring metal film 108a is formed of a copper film, and is formed using an electroplating method.

Referring to FIG. 2C, the lower metal wiring metal film and the TaN / Ta film 106 are removed by CMP until the polishing stop film 104 is exposed to form the lower metal wiring 108. The capping film 110 is formed on the lower metal wiring 108 including the / Ta film 106 and the polishing stop film 104. The capping film 110 is formed of, for example, a nitride film.

Referring to FIG. 2D, an insulating film 112 is formed on the capping film 110, and the insulating film 112 and the capping film 110 are etched until the lower metal wiring 108 is exposed to form a second insulating film 112. The wiring formation region D2 is formed. At this time, the second wiring formation region D2 is preferably a via hole structure.

Referring to FIG. 2E, a TaN film 114 is formed on the insulating film 112 including the surface of the second wiring formation region D2. The TaN film 114 is preferably formed of a Ta _x N _y film (0.4 ≦ _x ≦ 0.7, 0.3 ≦ _y ≦ 0.6) and formed by a sputtering method. The TaN film 114 formed by the sputtering method has a crystalline phase of a nano size.

Then, boron is penetrated to the surface of the TaN film 114 to form an amorphous TaBN film 116, preferably, a Ta _x B _y N _z film (0.3 ≦ _x ≦ 0.7, 0.1 ≦ y ≦ 0.3, 0.2 ≦ _z). ≤0.4). Infiltration of boron to form the amorphous TaBN film 116 is performed by heat treatment or plasma treatment using a boron-based gas such as B ₂ H ₆ , or BCl ₃ , and the heat treatment is performed at 300 to 600 ° C. It is carried out at the temperature conditions of.

Here, the crystal structure of the TaN film 114 having the crystalline phase is broken and amorphous through the boron infiltration, thereby forming the TaBN film 116 having the amorphous phase.

Referring to FIG. 2F, a Ti-rich (Rich) TiN film is formed on the TaBN film 116, preferably, a TiN film having a Ti content of 1.5 times or more of N content. The boron in the TaBN film 116 reacts with the TiN film to form a TiBN film 120 at an interface between the TaBN film 116 and the TiN film. The TiBN film 120 is preferably a Ti _x B _y N _z film (0.3 ≦ _x ≦ 0.7, 0.1 ≦ y ≦ 0.3, 0.2 ≦ _z ≦ 0.4).

As a result, a diffusion barrier film 122 including a multilayer structure in which the TaN film 114, the TaBN film 116, the TiBN film 120, and the TiN film 118 are sequentially stacked is formed. At this time, the TiN film 118 is preferably a Ti _x N _y film (0.4≤x≤0.7, 0.3≤y≤0.6). The TaN film 114 and the TaBN film 116 of the diffusion barrier 122 serve as a diffusion barrier of the lower metal wiring 108, and the TiBN film 120 and the TiN film 118 are the upper metal wiring. It serves as a diffusion barrier of (124).

Here, the reaction between the boron in the TaBN film 116 and the TiN film is performed by heat treatment. The TiBN film 120 is formed at the interface between the Ti-rich TiN film and the TaBN film 116 during the heat treatment, and the surface portion of the remaining TiN film that does not react with boron in the TaBN film 116 is stoichiometric. The TiN film 118 is converted into. The stoichiometric TiN film 118 serves as a wetting film in the deposition of subsequent aluminum films.

Referring to FIG. 2G, the TaN film 114, the TaBN film 116, the TiBN film 120, and the TiN film 118 may have a diffusion barrier film 122 including a multilayer structure in which a multilayer structure is sequentially stacked. An upper metal wiring metal film is embedded on the semiconductor substrate 100 including the wiring forming region D2 to fill the second wiring forming region D2. In this case, the upper metal wiring metal film is formed of an aluminum film. Next, the upper metal wiring 124 and the diffusion barrier layer 122 are etched to form the upper metal wiring 124.

Subsequently, although not shown, a series of subsequent known processes are sequentially performed to form the metal wiring of the semiconductor device according to the embodiment of the present invention.

As described above, in the present invention, by forming a diffusion barrier including a multilayer structure of TaN / TaBN / TiBN / TiN, the characteristics of the diffusion barrier can be improved without increasing the thickness of the diffusion barrier. In addition, the present invention can improve the contact resistance by preventing the diffusion between the upper and lower metal wirings through the diffusion barrier layer including the multilayer structure of TaN / TaBN / TiBN / TiN.

In addition, by forming a wetting film on the diffusion barrier layer, when forming the upper metal wiring, the formation of the metal wiring can be performed stably and easily, thus improving the characteristics and reliability of the semiconductor device.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1 is a cross-sectional view for explaining a metal wiring of a semiconductor device according to an embodiment of the present invention.

2A to 2G are cross-sectional views illustrating processes for forming metal wirings of a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 interlayer insulating film

104: polishing stop film D1: first wiring formation region

106: TaN / Ta film 108: lower metal wiring

110 capping film 112 insulating film

D2: Second Wiring Formation Area 114: TaN Film

116: TaBN film 118: TiBN film

120: TiN film 122: diffusion barrier film

124: upper metal wiring

Claims (25)

A lower metal interconnection formed on the semiconductor substrate; An insulating film formed on the semiconductor substrate and having a wiring formation region exposing at least a portion of the lower metal wiring; It is formed on the wiring forming area surface of the insulating film, Ta _x N _y film _{(0.4≤x≤0.7, 0.3≤y≤0.6), Ta x} B y N z film (0.3≤x≤0.7, 0.1≤y≤0.3 , 0.2 ≦ _z ≦ 0.4), Ti _x B _y N _z film (0.3 ≦ _x ≦ 0.7, 0.1 ≦ y ≦ 0.3, 0.2 ≦ _z ≦ 0.4) and Ti _x N _y film (0.4 ≦ _x ≦ 0.7, 0.3 ≦ _y A diffusion barrier layer including a multilayer structure in which ≦ 0.6) is sequentially stacked; And An upper metal wiring formed on the diffusion barrier to fill the wiring forming region of the insulating film; Metal wiring of a semiconductor device comprising a. The method of claim 1, The lower metal wiring may include a copper film. The method of claim 1, The Ta _x B _y N _z film has an amorphous phase, the metal wiring of the semiconductor device. delete delete delete delete The method of claim 1, The metal wiring of the semiconductor device, characterized in that the upper metal wiring comprises an aluminum film. Forming a lower metal wiring on the semiconductor substrate; Forming an insulating film having a wiring formation region exposing at least a portion of the lower metal wiring on the semiconductor substrate; On the insulating film including the surface of the wire formation area Ta _x N _y film _{(0.4≤x≤0.7, 0.3≤y≤0.6), Ta x} B y N z film (0.3≤x≤0.7, 0.1≤y≤0.3, 0.2 ≦ _z ≦ 0.4), Ti _x B _y N _z films (0.3 ≦ _x ≦ 0.7, 0.1 ≦ y ≦ 0.3, 0.2 ≦ _z ≦ 0.4) and Ti _x N _y films (0.4 ≦ _x ≦ 0.7, 0.3 ≦ _y ≦ Forming a diffusion barrier film including a multilayer structure in which 0.6) is sequentially stacked; And Forming an upper metal wiring on the diffusion barrier to fill the wiring formation region; Metal wiring forming method of a semiconductor device comprising a. The method of claim 9, The metal wiring forming method of the semiconductor device, characterized in that the lower metal wiring comprises a copper film. The method of claim 9, The Ta _x B _y N _z film is a metal wiring forming method of the semiconductor device, characterized in that formed in a film having an amorphous phase. delete delete delete delete The method of claim 9, Forming the diffusion barrier film, Forming a Ta _x N _y film on the insulating film including the surface of the wiring forming region; Penetrating boron on the surface of the Ta _x N _y film to form a Ta _x B _y N _z film; Forming a Ti _x N _y film on the Ta _x B _y N _z film; And To form by reacting the boron in the Ta _x B _y N _z layer and the Ti _x N _y film is a film at the interface between the Ta _x N _y B _z layer and the Ti _x N _y film Ti _x B _y N _z; Metal wiring forming method of a semiconductor device comprising a. The method of claim 16, The Ta _x N _y film is formed by a sputtering method (sputtering) metal wiring forming method of a semiconductor device. The method of claim 16, The Ta _x N _y film is formed to have a crystalline phase metal wiring forming method of the semiconductor device, characterized in that The method of claim 16, The penetration of the boron is a metal wiring forming method of a semiconductor device, characterized in that performed by heat treatment or plasma treatment using a boron-based gas. The method of claim 19, The heat treatment is a metal wiring forming method of a semiconductor device, characterized in that performed at a temperature condition of 300 ~ 600 ℃. The method of claim 19, The boron-based gas is B ₂ H ₆ , or BCl ₃ The metal wiring forming method of a semiconductor device, characterized in that using. The method of claim 16, The Ta _x B _y N _z film is formed to have an amorphous phase metal wiring formation method of a semiconductor device. The method of claim 16, The Ti _x N _y film is a metal wiring forming method of a semiconductor device, characterized in that using a Ti-rich (Rich) TiN film. The method of claim 16, The reaction between the boron in the Ta _x B _y N _z film and the Ti _x N _y film is performed by heat treatment. The method of claim 9, The metal wiring forming method of the semiconductor device, characterized in that the upper metal wiring comprises an aluminum film.

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