KR20040039591A - Method for forming a copper anti-diffusion film and Method for manufacturing a copper metal line using the same - Google Patents

Abstract

PURPOSE: A method for forming a copper anti-diffusion layer is provided to prevent a copper silicide layer from being formed between a copper interconnection and an anti-diffusion layer by forming an anti-diffusion layer made of a CoW thin film on the copper interconnection. CONSTITUTION: A lower structure includes a lower interconnection whose uppermost layer is made of a copper metal layer(104). An upper structure includes an upper interconnection made of a metal layer. A copper anti-diffusion layer(106) made of a CoW thin film is formed on the lower interconnection by selectively using a cobalt source precursor, a tungsten source precursor and hydrogen reduction gas.

Description

Method for forming a copper anti-diffusion film and Method for manufacturing a copper metal line using the same}

The present invention relates to a method for forming a copper diffusion barrier and a method for manufacturing a copper wiring using the same, and in particular, to improve the reliability of the semiconductor device by improving the interfacial properties between the copper wiring and the diffusion barrier, and a copper diffusion barrier formation method It relates to a wiring manufacturing method.

In a semiconductor device or an electronic device, a metal film such as aluminum (Al) or tungsten (W) is deposited on an insulating film, and then metal wiring is formed by using a photolithography process and a dry or wet etching process. To form. In particular, recently, a method of using a low-resistance metal such as copper (Cu) instead of aluminum or tungsten as a wiring to reduce the RC delay time centering on a logic device requiring high speed among semiconductor devices has recently been used. Is being studied.

In the wiring forming process using copper, a patterning process of copper metal is more difficult than aluminum or tungsten, and so-called 'line damascene' which forms a wiring by filling a trench (for example, a region where wiring is to be formed). In particular, during the line damascene process, a via hole is formed in the interlayer insulating film together with a trench to be connected to the lower wiring, and a copper metal is embedded in the via hole and the trench to simultaneously form a wiring. Dual damascene processes are commonly used.

In general, in the copper wiring forming process using the dual damascene process, copper atoms are easily diffused between interlayer insulating films as compared with other metals such as aluminum or tungsten. Because of this property, a diffusion barrier (or capping film) is formed on the surface of the main conductive layer made of copper. In particular, a diffusion barrier is deposited on a silicon nitride film (SiN film) so as to cover the upper surface of the copper wiring on the upper surface of the interlayer insulating film in which the trench and the via hole are formed. In this case, the diffusion barrier layer is conventionally formed by chemical vapor deposition (hereinafter referred to as 'CVD') at a relatively high temperature (eg, 400 ° C. or more) using SiH ₄ and NH ₃ gas.

However, during the formation of the diffusion barrier layer, for example, in the CVD process, a hillock phenomenon occurs due to thermal stress due to high temperature, and SiH ₄ reacts with the copper atom to react the copper silicide layer (Cu) between the copper metal wiring and the diffusion barrier layer. Silicide film or copper oxide is formed, which causes sheet resistance of copper metal wiring to increase. These defects of the copper silicide layer affect the subsequent exposure and etching processes, causing some via holes to become smaller and some via holes to become larger.

Meanwhile, the 'K. Takeda, Jpn. J. Appl. Phys. According to Vol. 40 ', "Time Dependent Dielectric Breakdown (TDDB) phenomenon in copper damascene structure is mainly generated at the interface between the silicon nitride film and the copper metal wiring." These results suggest that the defects remaining at the interface between the silicon nitride film and the copper metal wiring should be reduced and the bonding strength should be enhanced. In addition, the silicon nitride film used as the diffusion barrier film has a large amount of pinholes in the thin film, and when deposited using a PECVD (Plasma Enhanced Chemical Vapor Deposition) process, the surface roughness of the thin film is rough, so that the copper It will not be sufficient to prevent diffusion. As a result, leakage current between the lower wiring and the upper wiring increases, which causes deterioration of the reliability of the device.

Accordingly, the present invention has been made to solve the above problems of the prior art, and an object thereof is to prevent the formation of a copper silicide film between a copper metal wiring and a diffusion barrier film.

In addition, the present invention has another object to suppress the occurrence of hillock phenomenon due to thermal stress during the deposition process of the diffusion barrier.

In addition, the present invention has another object to improve the interface characteristics between the copper wiring and the diffusion barrier by reducing the defects occurring at the interface between the copper wiring and the diffusion barrier as possible.

In addition, the present invention has another object to improve the reliability of the semiconductor device.

1 is a cross-sectional view for explaining a method for forming a copper diffusion barrier according to a first embodiment of the present invention.

2 is a cross-sectional view for explaining a method of forming a copper diffusion barrier according to a second embodiment of the present invention.

3 to 8 are cross-sectional views illustrating a method for manufacturing a copper wiring according to a third embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

102, 202, and 302: semiconductor substrates 104 and 204: copper metal layers

106,206: copper diffusion barrier 304: first etch stop layer

306: first interlayer insulating film 308: first diffusion barrier film

310: lower wiring 312: first selective diffusion barrier

314: second interlayer insulating film 316: second etch stop layer

318: third interlayer insulating film 320: via hole

322 trench 324 second diffusion barrier

326: copper wiring 328: second selective diffusion barrier

330: third etch stop layer 332: fourth interlayer insulating film

334: third diffusion barrier 336: upper wiring

According to an aspect of the present invention, the lower wiring to prevent the diffusion of the copper atoms of the lower wiring between the lower structure including the lower structure of the upper layer is made of a copper metal layer, and the upper structure comprising an upper wiring made of a metal layer, Provided is a method for forming a copper diffusion barrier of a CoW thin film using a cobalt source precursor, a tungsten source precursor, and a hydrogen reducing gas.

According to another aspect of the invention, in order to prevent the diffusion of the copper atoms of the lower wiring between the lower structure including the lower structure of the uppermost layer is made of copper metal, and the upper structure comprising the upper wiring is made of a metal layer, Provided is a method of forming a copper diffusion barrier film having a laminated structure of a cobalt film or a laminated structure of a cobalt film and a tungsten film.

According to another aspect of the invention, forming a first interlayer insulating film on a semiconductor substrate having a lower structure, and etching a portion of the first interlayer insulating film, and forming a lower wiring made of copper metal on the portion to be etched And forming a selective diffusion barrier on the lower interconnection, wherein the selective diffusion barrier is formed of a CoW thin film using a cobalt source precursor, a tungsten source precursor, and a hydrogen reducing gas, or a laminated structure of a tungsten film and a cobalt film Forming a layered structure of a cobalt film and a tungsten film, forming a second interlayer insulating film on the entire structure, etching a portion of the second interlayer insulating film to expose a part of the selective diffusion barrier film, and Copper wire manufacturing method comprising the step of forming an upper wiring made of a metal material on the portion to be etched to provide.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1 is a cross-sectional view for explaining a method of forming a copper diffusion barrier according to a first embodiment of the present invention.

Referring to FIG. 1, a copper metal layer 104 is formed on a semiconductor substrate 102 on which a predetermined substructure (not shown) is formed. Then, the copper diffusion barrier 106 is formed on the copper metal layer 104 by using a CoW film capable of low temperature deposition and excellent in the ability to prevent diffusion of copper atoms.

The copper diffusion barrier layer 106 is deposited using a low pressure CVD (LPCVD) method, but is deposited using a cobalt (Co) source precursor, a tungsten (W) source precursor, and a hydrogen (H ₂ ) reducing gas. Co ₂ (CO) ₈ , HCo (CO) ₄ or (CF ₃ ) Co (CO) ₄ is used as the cobalt source precursor, and WF ₆ is used as the tungsten source precursor. In addition, the copper diffusion barrier 106 may use all of the precursors containing cobalt or tungsten as a source.

For example, the LPCVD deposition conditions for forming the diffusion barrier film 106 is performed by setting the deposition target to a thickness of 100 mW to 1000 mW. Specifically, the deposition conditions are a cobalt source precursor and a tungsten source precursor to the deposition reactor at a flow rate of 10sccm to 500sccm, hydrogen is supplied at a flow rate of 200sccm to 5000sccm, and the pressure of the deposition reactor is about 0.001Torr to 100Torr, The temperature of the deposition reactor is set to about 200 to 400 ℃.

Meanwhile, the CoW film formed through the LPCVD deposition process is formed as in Scheme 1 below. Here, only the reaction scheme of the CoW thin film formed when Co ₂ (CO) ₈ is used as the cobalt source precursor and WF ₆ is used as the tungsten source precursor will be described.

Co ₂ (CO) ₈ + 2WF ₆ + 14H ₂ → 2CoW + 12HF + 4CO ₂ + 4CH ₄

The CoW thin film of the copper diffusion barrier layer 106 described above is excellent in the diffusion preventing ability of the copper atoms can effectively reduce the sheet resistance of the device. In particular, the CoW thin film not only has excellent contact force with the copper metal layer 104, but also has excellent contact force with other oxide films. Accordingly, the formation and defects of the copper silicide film generated at the interface between the copper metal layer 104 and the copper diffusion barrier film 106 can be suppressed to the maximum.

2 is a cross-sectional view illustrating a method of forming a copper diffusion barrier according to a second embodiment of the present invention.

Referring to FIG. 2, a copper metal layer 204 is formed on a semiconductor substrate 202 on which a predetermined substructure (not shown) is formed. Then, a copper diffusion barrier 206 is formed on the copper metal layer 204. At this time, the copper diffusion barrier 206 is formed in a laminated structure, the tungsten film 206a is formed as a lower layer, and the cobalt film 206b is formed as an upper layer. However, the copper diffusion barrier 206 may form a cobalt film as a lower layer and a tungsten film as an upper layer. Here, the tungsten film 206a and the cobalt film 206b are sequentially formed in the same deposition reactor by performing an LPCVD deposition process in an in-situ manner.

For example, the LPCVD deposition conditions for forming the tungsten film 206a are performed by setting the deposition target to a thickness of 50 mW to 500 mW. Specifically, the deposition conditions are WF ₆ to 5sccm to 500sccm to the deposition reactor, hydrogen is supplied to 50sccm to 5000sccm, the pressure of the deposition reactor is about 0.001 Torr to 100 Torr, the temperature of the deposition reactor is 300 ℃ to 450 ℃ Set to about.

On the other hand, the reaction formula of the tungsten film 206a formed through the LPCVD deposition process is shown in the following reaction formula 2.

WF ₆ + 3H ₂ → W + 6HF

On the other hand, LPCVD deposition conditions for forming the cobalt film 206b is carried out by setting the deposition target to a thickness of 50 kPa to 500 kPa. Specifically, the deposition conditions are Co ₂ (CO) ₈ , HCo (CO) ₄ or (CF ₃ ) Co (CO) ₄ to supply a 5sccm to 500sccm to the deposition reactor, hydrogen to 500sccm to 5000sccm to the deposition reactor and The pressure of the deposition reactor is set to about 0.001 Torr to 100 Torr, and the temperature of the deposition reactor is set to about 200 ° C to 450 ° C.

On the other hand, the reaction formula of the cobalt film 206b formed through the LPCVD deposition process is shown in the following reaction formula 3. For convenience of explanation, only the reaction scheme of Co ₂ (CO) ₈ will be described here.

Co ₂ (CO) ₈ + 8H ₂ → 2Co + 4CO ₂ + 4CH ₄

In the above, in the first and second embodiments of the present invention described with reference to FIGS. 1 and 2, after depositing the copper diffusion barrier films 106 and 206, a predetermined superstructure (not shown) is formed thereon. It may be.

Hereinafter, a method of manufacturing a copper wiring by using the copper diffusion barrier film forming method according to the first and second embodiments of the present invention will be described in detail through the third embodiment. As an example, a back end of line damascene wiring process will be described.

3 to 8 are cross-sectional views illustrating a method for manufacturing a copper wiring according to a third embodiment of the present invention.

Referring to FIG. 3, a trench etch stop layer serving as an etch stop layer during an etching process for forming a subsequent trench (not shown) on a semiconductor substrate 302 having a predetermined substructure (not shown) is formed. layer 304 (hereinafter referred to as a 'first etch stop layer') is deposited.

Subsequently, an insulating film (hereinafter referred to as a 'first interlayer insulating film') 306 is deposited on the entire structure using a low dielectric material, for example, silicon oxide, fluorine-containing silicon oxide, or fluorine-containing oxide. In general, fluorine-containing silicon oxide has a lower dielectric constant than silicon oxide, and the dielectric constant can be controlled by adjusting the fluorine content.

Subsequently, after the photoresist film is entirely coated on the entire structure, the photoresist pattern exposing a part of the first interlayer insulating film 306 by sequentially performing exposure and development processes using a photomask ( form a photoresist pattern (not shown).

Subsequently, the first interlayer insulating layer 306 and the first etch stop layer 304 are etched by performing an etching process using a photoresist pattern as an etching mask in a dry or wet manner. As a result, a trench in which a part of the semiconductor substrate 302 is exposed is formed. Then, a strip process is performed to remove the photoresist pattern.

Subsequently, a diffusion barrier (hereinafter, referred to as a first diffusion barrier) 308 is formed on the trench inner surfaces (ie, inner and bottom surfaces). For example, the first diffusion barrier 308 is formed of Ta, TaN, TaAlN, TaSiN, TaSi ₂ , Ti, TiN, TiSiN to prevent subsequent atoms of the first copper metal layer 310 from diffusing into the first interlayer insulating layer 306. , WN, Co and CoSi ₂ .

Subsequently, a copper metal layer 310 (hereinafter referred to as 'lower wiring') 310 is formed to fill the trench. The lower wiring 310 may be formed of a metal layer made of any one of Al, Pt (Platinum), Pd (Palladium), Ru (Rubidium), St (Strontium), Rh (Rhadium), and Co instead of copper metal. In this case, the lower wiring 310 may be formed using an electroplating method. For example, in the case of depositing a copper metal using an electroplating method, the copper metal is first deposited, and then annealing is performed to crystallize the copper metal.

Referring to FIG. 4, a diffusion barrier layer (hereinafter, referred to as a first selective diffusion barrier layer) 312 is selectively formed on the lower wiring 310. The first selective diffusion barrier 312 is formed of a single film of a CoW film as in the first embodiment described in FIG. 1, or a layered structure or cobalt layer of tungsten film and cobalt film as in the second embodiment described in FIG. It is formed by a laminated structure of a film and a tungsten film.

For example, the first selective diffusion barrier 312 is deposited in a CoW film or a tungsten film and a cobalt film stacked structure on the entire structure by the method described in the first embodiment of FIG. 1 or the second embodiment of FIG. A photolithography process is performed to selectively form only the upper portion of the lower interconnection 310. Here, the first selective diffusion barrier 312 may also be formed on the first diffusion barrier 308.

Referring to FIG. 5, an insulating film (hereinafter referred to as a “second interlayer insulating film”) 314 is deposited on the entire structure using a low dielectric material, for example, silicon oxide, fluorine-containing silicon oxide, or fluorine-containing oxide. . The via hole 320 is formed in a part of the second interlayer insulating film 314 by a subsequent process.

Subsequently, a trench etch stop layer (hereinafter referred to as a “second etch stop layer”) 316 serving as an etch stop layer in an etching process for forming a subsequent trench 322 on the second interlayer insulating layer 314 is formed. Can be deposited.

Subsequently, an insulating film (hereinafter referred to as 'third interlayer insulating film') 318 is deposited on the second etch stop layer 316 by using any one of the same low dielectric materials as the second interlayer insulating film 314. . A trench 322 is formed in part of the third interlayer insulating film 318 by a subsequent process.

Subsequently, the via hole 320 and the trench 322 are formed by performing a dual damascene process using a sun via method or a post via method. In detail, in the via via method, the via hole 320 is formed by sequentially etching the third interlayer insulating layer 318, the second etch stop layer 316, and the second interlayer insulating layer 314 by first performing a photolithography process. do. Then, another photolithography process is performed to etch the third interlayer insulating film 318 and the second etch stop layer 316 to form a trench 322 that is wider than the via hole 320. In the Huvia method, a trench 322 is formed by first etching the third interlayer insulating layer 318 and the second etch stop layer 316 by performing a photolithography process. Then, another photolithography process is performed to etch the second interlayer insulating film 314 to form a via hole 320 that is narrower than the trench 322.

Meanwhile, as illustrated in FIG. 5, the second etch stop layer 316 may be patterned to the same width as the trench 322, and may be the same as the via hole 320 in designing in consideration of the characteristics of the semiconductor device and process convenience. It may be patterned in width. In addition, the first selective diffusion barrier 312 may be etched such that a portion of the first selective diffusion barrier 312 remains on the lower interconnection 310 in the process of forming the via hole 320, or the lower interconnection 310 is exposed. It may be etched as much as possible.

Referring to FIG. 6, a diffusion barrier (hereinafter, referred to as a second diffusion barrier) 324 is formed on the inner surfaces of the via hole 320 and the trench 322. For example, the second diffusion barrier 324 may be formed of Ta, TaN, TaAlN, TaSiN, to prevent the atoms of the second copper metal layer 326 from being diffused into the second interlayer dielectric 314 or the third interlayer dielectric 318. It is formed of any one of TaSi ₂ , Ti, TiN, TiSiN, WN, Co and CoSi ₂ .

Subsequently, a copper metal layer 326 is deposited on the entire structure to fill the via hole 320 and the trench 322. Here, the copper metal layer 326 may be deposited using an electroplating method. That is, the copper metal layer 326 deposits a seed layer (not shown) on the second diffusion barrier layer 324 with copper metal, and then deposits copper metal on the seed layer using the seed layer as a seed. Form.

Next, a planarization process using a chemical mechanical polishing (CMP) method is performed to planarize the copper metal layer 326 to fill the via hole 320 and the trench 322 to form a copper wiring. Hereinafter, as the copper metal layer 326 and the copper wiring are described as the same members, the reference numerals of the copper wirings will be used as the same reference numerals as the copper metal layer 326.

Referring to FIG. 7, a diffusion barrier layer (hereinafter, referred to as a second selective diffusion barrier layer 328) 328 is selectively formed on the copper wiring 326. The second selective diffusion barrier 328 is formed of a single film of CoW film as in the first embodiment described in FIG. 1, or a layered structure or cobalt layer of tungsten film and cobalt film as in the second embodiment described in FIG. It is formed by a laminated structure of a film and a tungsten film.

For example, the second selective diffusion barrier 328 is deposited on a CoW thin film or a tungsten film and a cobalt film stacked structure on the entire structure by the method described in the first embodiment of FIG. 1 or the second embodiment of FIG. The lithography process is performed to selectively form only the upper portion of the copper wiring 326. Here, the second selective diffusion barrier 328 may also be formed on the second diffusion barrier 324.

Referring to FIG. 8, a process of forming a trench (hereinafter, referred to as an 'top trench') (not shown) for forming a subsequent upper interconnection 336 on the entire structure will be described on the second selective diffusion barrier 328. A trench etch stop layer (hereinafter referred to as a “third etch stop layer”) 330 serving as an etch stop layer is formed on the substrate 330.

Subsequently, any one of SG (Sping On Glass), Un-doped Silicate Glass (USG), Bron Phosphorus Silicate Glass (BPSG), Phosphorus Silicate Glass (PSG), and TetraEthylOrtho Silicate Glass (TEOS) on the third etch stop layer 330. An insulating film (hereinafter referred to as a 'fourth interlayer insulating film') 332 is formed using one material.

Subsequently, the fourth interlayer insulating layer 332 and the third etch stop layer 330 are etched by performing a photolithography process. As a result, a trench for upper wiring through which the second selective diffusion barrier 328 is exposed is formed. In this case, the second selective diffusion barrier 328 may be etched to expose the copper wiring 326, or may be etched to partially remain on the copper wiring 326.

Subsequently, a diffusion barrier layer (hereinafter referred to as a third diffusion barrier layer) 334 is formed on the inner surface of the upper wiring trench. For example, the third diffusion barrier 334 may include Ta, TaN, TaAlN, TaSiN, TaSi ₂ , Ti, TiN, TiSiN, WN, It is formed of any one of Co and CoSi ₂ .

Subsequently, a metal layer is deposited to fill the upper wiring trench to form the upper wiring 336. The upper wiring 336 may be formed of a metal layer made of any one of Al, Pt (Platinum), Pd (Palladium), Ru (Rubidium), St (Strontium), Rh (Rhadium), and Co instead of copper metal. In this case, the upper wiring 336 may be formed using a physical vapor deposition (PVD) method or an electroplating method.

Although the technical spirit of the present invention described above has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, in the present invention, the formation of the copper silicide film formed between the copper wiring and the diffusion barrier film can be prevented by forming the diffusion barrier film of the CoW thin film on the copper wiring.

In addition, the present invention can suppress the occurrence of hillock phenomenon due to thermal stress by depositing the diffusion barrier film at a low temperature of 400 ℃ or less.

In addition, the present invention can improve the interface characteristics between the copper wiring and the diffusion barrier by forming a diffusion barrier of the CoW thin film on the copper wiring to minimize the defects occurring at the interface between the copper wiring and the diffusion barrier.

In addition, the present invention can improve the reliability of the semiconductor device.

Claims (8)

In order to prevent diffusion of the copper atoms of the lower interconnection between the lower structure including the lower interconnection of the uppermost layer is made of a copper metal layer, and the upper structure comprising the upper interconnection is made of a metal layer, The method of forming a copper diffusion barrier of the CoW thin film using a cobalt source precursor, a tungsten source precursor and a hydrogen reducing gas selectively on the lower wiring. The method of claim 1, The cobalt source precursor is Co ₂ (CO) ₈ , HCo (CO) ₄ or (CF ₃ ) Co (CO) _{4 It} characterized in that the copper diffusion barrier film forming method. The method of claim 1, The method of forming a copper diffusion barrier, characterized in that WF ₆ is used as the tungsten source precursor. The method of claim 1, The CoW thin film was deposited by LPCVD method, and the cobalt source precursor and the tungsten source precursor were respectively supplied to a deposition reactor at a flow rate of 10 sccm to 500 sccm, hydrogen was supplied at a flow rate of 200 sccm to 5000 sccm, and the pressure of the deposition reactor was 0.001. Torr to 100 Torr, the copper diffusion barrier film forming method characterized in that the deposition by setting the temperature of the deposition reactor to about 200 ℃ to 400 ℃. In order to prevent diffusion of the copper atoms of the lower interconnection between the lower structure including the lower structure of the uppermost layer is made of a copper metal and the upper structure comprising the upper wiring is made of a metal layer, A method of forming a copper diffusion barrier, wherein the copper diffusion barrier is formed of a laminated structure of a tungsten film and a cobalt film or a laminated structure of a cobalt film and a tungsten film. The method of claim 5, wherein The tungsten film was deposited by LPCVD, but WF ₆ was supplied at 5 sccm to 500 sccm as a deposition reactor, hydrogen was supplied at 50 sccm to 5000 sccm, the pressure of the deposition reactor was about 0.001 Torr to 100 Torr, and the temperature of the deposition reactor was 300 ° C. Copper diffusion barrier film forming method characterized in that the deposition is set to about 450 ℃. The method of claim 5, wherein The cobalt film is deposited by LPCVD, and Co ₂ (CO) ₈ , HCo (CO) ₄ or (CF ₃ ) Co (CO) ₄ is supplied at 5 sccm to 500 sccm as a deposition reactor, and hydrogen is 500 sccm to 5000 sccm as a deposition reactor. The copper diffusion barrier film forming method, characterized in that for supplying to the deposition reactor, the pressure of the deposition reactor is about 0.001 Torr to 100 Torr, the temperature of the deposition reactor is set to about 200 ℃ to 450 ℃. (a) forming a first interlayer insulating film on the semiconductor substrate on which the substructure is formed; (b) etching a portion of the first interlayer insulating film and forming a lower wiring made of copper metal on the portion to be etched; (c) forming a selective diffusion barrier layer on the lower wiring, wherein the selective diffusion barrier layer is formed of a CoW thin film using a cobalt source precursor, a tungsten source precursor and a hydrogen reducing gas, or a tungsten layer and a cobalt layer stacked structure Forming or forming a stacked structure of a cobalt film and a tungsten film; (d) forming a second interlayer insulating film over the entire structure; And (e) etching a part of the second interlayer insulating film so that a part of the selective diffusion barrier film is exposed, and forming an upper wiring made of a metal material on the portion to be etched.