KR100598259B1 - 반도체의 하이브리드 레이어 배선 형성방법 - Google Patents
반도체의 하이브리드 레이어 배선 형성방법 Download PDFInfo
- Publication number
- KR100598259B1 KR100598259B1 KR1020030053016A KR20030053016A KR100598259B1 KR 100598259 B1 KR100598259 B1 KR 100598259B1 KR 1020030053016 A KR1020030053016 A KR 1020030053016A KR 20030053016 A KR20030053016 A KR 20030053016A KR 100598259 B1 KR100598259 B1 KR 100598259B1
- Authority
- KR
- South Korea
- Prior art keywords
- aluminum
- layer wiring
- copper
- semiconductor
- dry etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 230000015572 biosynthetic process Effects 0.000 title description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 25
- 239000010949 copper Substances 0.000 claims abstract description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052802 copper Inorganic materials 0.000 claims abstract description 14
- 238000001312 dry etching Methods 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims abstract description 5
- 230000008021 deposition Effects 0.000 claims abstract description 4
- 239000007858 starting material Substances 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000002351 wastewater Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (4)
- 반도체의 레이어 배선 형성방법에 있어서,알루미늄(Al)을 임의의 두께만큼 시작 물질로 하여 ALD(Atomic layer deposition) 법으로 구리(Cu)와 알루미늄을 순차적으로 증착한 다음 마지막 물질을 알루미늄으로 마무리 증착하는 단계와,상기 마무리 증착이 완료된 후, 포토 레지스트로 원하는 만큼 패터닝(patterning)을 실시하고, 건식 식각을 수행하여 패턴(pattern)을 완성하는 단계를 포함하는 반도체의 하이브리드 레이어 배선 형성방법.
- 삭제
- 삭제
- 제 1 항에 있어서,상기 알루미늄과 구리를 각각 3∼2000Å 두께만큼 증착하는 것을 특징으로 하는 반도체의 하이브리드 레이어 배선 형성방법.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030053016A KR100598259B1 (ko) | 2003-07-31 | 2003-07-31 | 반도체의 하이브리드 레이어 배선 형성방법 |
US10/902,903 US7087520B2 (en) | 2003-07-31 | 2004-07-30 | Method for fabricating metal wiring |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030053016A KR100598259B1 (ko) | 2003-07-31 | 2003-07-31 | 반도체의 하이브리드 레이어 배선 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20050014396A KR20050014396A (ko) | 2005-02-07 |
KR100598259B1 true KR100598259B1 (ko) | 2006-07-07 |
Family
ID=34101793
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020030053016A Expired - Fee Related KR100598259B1 (ko) | 2003-07-31 | 2003-07-31 | 반도체의 하이브리드 레이어 배선 형성방법 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7087520B2 (ko) |
KR (1) | KR100598259B1 (ko) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7582557B2 (en) * | 2005-10-06 | 2009-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for low resistance metal cap |
US7446034B2 (en) * | 2005-10-06 | 2008-11-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for making a metal seed layer |
US7777344B2 (en) * | 2007-04-11 | 2010-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transitional interface between metal and dielectric in interconnect structures |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4855016A (en) * | 1987-07-16 | 1989-08-08 | Texas Instruments Incorporated | Method for etching aluminum film doped with copper |
US6291336B1 (en) * | 1996-05-20 | 2001-09-18 | Taiwan Semiconductor Manufacturing Company | AlCu metal deposition for robust Rc via performance |
US5795829A (en) * | 1996-06-03 | 1998-08-18 | Advanced Micro Devices, Inc. | Method of high density plasma metal etching |
JP2001196381A (ja) * | 2000-01-12 | 2001-07-19 | Toyo Kohan Co Ltd | 半導体装置、半導体上の回路形成に用いる金属積層板、および回路形成方法 |
US6384468B1 (en) * | 2000-02-07 | 2002-05-07 | International Business Machines Corporation | Capacitor and method for forming same |
US6873027B2 (en) * | 2001-10-26 | 2005-03-29 | International Business Machines Corporation | Encapsulated energy-dissipative fuse for integrated circuits and method of making the same |
-
2003
- 2003-07-31 KR KR1020030053016A patent/KR100598259B1/ko not_active Expired - Fee Related
-
2004
- 2004-07-30 US US10/902,903 patent/US7087520B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR20050014396A (ko) | 2005-02-07 |
US20050023698A1 (en) | 2005-02-03 |
US7087520B2 (en) | 2006-08-08 |
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