KR100479290B1 - Display device, method of manu facturing the same and wiring board - Google Patents

Abstract

This invention makes it a subject to obtain the liquid crystal display device which can prevent the short circuit between wiring.

The TFT (Thin Film Transistor) array substrate has a dummy signal line 36 which is a short circuit in order to prevent a short circuit caused by electrostatic breakdown between the signal line 33 which is an upper wiring and the gate line 34 which is a lower wiring. The dummy signal line 36 is formed in the outer circumferential region 32 of the TFT array substrate. The dummy signal line 36 has a three-layer structure from a lower layer to a lower silicon layer, an indium tin oxide (ITO) intermediate layer, and an upper layer of aluminum (Al). The silicon layer is formed by one continuous wiring at the time of its formation, but is etched simultaneously with the Al layer when the Al layer is patterned, and is electrically disconnected between the gate lines. Since the dummy wire is disconnected after the dummy wire is formed, even if the dummy wire and two or more gate lines are short-circuited, no short circuit is formed between the gate lines.

Description

DISPLAY DEVICE, METHOD OF MANU FACTURING THE SAME AND WIRING BOARD

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a display device, a method for manufacturing the same, and a wiring board, and more particularly, to a display device having a short circuit for suppressing a short circuit due to electrostatic breakdown between wirings by shorting with other wirings, a method for manufacturing the same, and a wiring board. will be.

As image display devices for personal computers and other various monitors, the spread of liquid crystal display devices (LCDs) is surprising. A liquid crystal display device generally has a liquid crystal display panel provided with a drive circuit and a backlight unit disposed on the rear surface thereof. The display panel displays an image by controlling the transmitted light. The display panel has a display region portion composed of a plurality of subpixel portions in the form of a matrix, and an outer peripheral region portion formed at the outer circumference thereof. Among the liquid crystal display devices, there is an active matrix LCD in which each subpixel portion has a switching element such as TFT (Thin Film Transistor) or MIM (Metal Insulator Metal).

Active matrix LCDs can display subtle gradations and have high contrast, and are therefore widely used in high definition display devices and color LCDs. A color LCD is usually formed by encapsulating a liquid crystal between an array substrate on which switching elements or pixel electrodes are formed in an array and a color filter substrate having a color filter. The color LCD has an RGB color filter for each subpixel unit, and color display is performed by controlling the amount of light from each subpixel unit. One pixel portion is formed by three RGB subpixel portions. In the monochrome LCD, each sub-pixel portion corresponds to the pixel portion.

1 is a configuration diagram schematically showing a subpixel portion having a TFT as a switching element. The subpixel portion only shows that formed on the TFT substrate side. Fig. 1 is a bottom gate type TFT, which uses amorphous silicon (a-Si) as a semiconductor. In addition, there exist a thing which used polysilicon as a semiconductor, a top gate type TFT, etc. The lower gate is a TFT in which the lower gate is disposed below the drain / source.

In the figure, 11 is a TFT as a switching element, 12 is a gate electrode, 13 is a gate insulating layer, and 14 is an amorphous silicon (a-Si) layer. 15 is a resistive layer for improving ohmic contact with the a-Si layer, an electrode 16 is a source electrode, 17 is a drain electrode, and 18 is a pixel electrode which applies an electric field to the liquid crystal. The resistive layer 15 is doped with phosphorus or arsenic as a donor. The gate electrode 12 is connected to the driver IC (not shown) on the Y axis through the gate line 19, and the source electrode 16 is connected to the driver IC (not shown) on the X axis through the signal line 20. have. In addition, since the TFT 11 is driven in alternating current, the source electrode 16 and the drain electrode 17 are reversed in time.

Explaining the behavior. A signal is sent from the Y-axis driver IC to each gate electrode 12 through the gate line 19. By this signal, the gate voltage of the TFT 11 is adjusted to turn the TFT 11 ON / OFF. In addition, a signal is sent from the X-axis driver IC to the source electrode 16 via the signal line 20. The presence or absence of signal transmission from the source electrode 16 to the drain electrode 17 is controlled by the gate electrode 12. The magnitude of the signal voltage to the drain electrode 17 is controlled by changing the signal voltage value from the X-axis driver IC to the source electrode 16. The pixel electrode 18 which sends a signal voltage from the drain electrode 17 applies a voltage to the liquid crystal between common electrodes (not shown) formed on the opposing substrate. The gray scale display can be performed by changing the voltage applied to the liquid crystal.

2 is a configuration diagram schematically showing a TFT array substrate. In the figure, 21 is a display area part, and 22 is an outer peripheral area part. 23 is a signal line, 24 is a gate line, and 25 is a short ring. In the manufacture of a TFT substrate, a wiring 25 called a short ring is formed outside the display area portion 21. The short ring is a wiring for shorting the ends of each signal line and gate line in order to prevent electrostatic breakdown of the active matrix wiring.

However, the short ring 25 functions after the gate line 24 and the signal line 23 are completed. Therefore, especially when the signal line 23 has a plurality of layers, there is a problem that a short circuit occurs between the signal line 23 and the gate line 24 before the uppermost layer of the signal line 23 is attached. In particular, it is known that electrostatic breakdown frequently occurs between the outermost signal line and the gate line below it in the display area 21. This is because the substrate end is held at the time of substrate transfer or the substrate end is in contact with the apparatus, so that charges that cause electrostatic breakdown tend to accumulate at the substrate end. Therefore, it is thought that electrostatic breakdown between outer conductors is easy to occur.

As described above, a dummy signal line is formed in the outer circumferential region as a means of preventing electrostatic breakdown before completion of the signal line. This is wiring formed in an electrically floating state on the outer side of the outermost signal line in the display area. This dummy wiring has the same configuration as that of the signal line and is formed simultaneously with the formation of the signal line. By forming such a dummy signal line, a short circuit due to the gate line and the electrostatic breakdown occurs between the dummy line, so that a defect due to a short circuit between the wiring and the gate line can be prevented.

However, even when the dummy line is formed in this way, there is a problem that the dummy line causes a short circuit with two or more gate lines. Thus, when two or more short-circuits are used, the two gate lines are electrically connected to each other, which results in a short circuit defect between the gate lines. Thus, in order to prevent the short circuit between gate lines, it is conceivable to cut a dummy line between each gate line. However, when the dummy line is disconnected in this manner, the capacity of each cut dummy line becomes small, and thus there is a problem that the outermost signal line and the gate line cause electrostatic breakdown, not between the dummy line and the gate line.

The present invention has been made to solve the above problems, and an object thereof is to obtain a display device, a method of manufacturing the same, and a wiring board which can prevent a short circuit between wirings. Another object of the present invention is to obtain a display device, a method of manufacturing the same, and a wiring board which can prevent the short circuit between the other wirings even when the dummy line and two or more other wirings are shorted. Another object of the present invention is to obtain a display device, a method of manufacturing the same, and a wiring board which are susceptible to short circuits in the dummy wirings, even when the dummy wirings are short-circuited with two or more other wirings. will be.

When the first aspect of the present invention is understood as a manufacturing method of a display device, it has a display area composed of a plurality of subpixel portions in the form of a matrix, and forms a plurality of lower layer wirings for sending electrical signals to the plurality of subpixel portions on a substrate. And forming an insulating layer on the plurality of lower layer wirings, a plurality of upper layer wirings for sending an electrical signal to a plurality of subpixels on the insulating layer, and short circuits on the outer side of the plurality of upper layer wirings and the outside of the display area. Forming and removing all or part of the short-circuit wiring to electrically disconnect the short-circuit wiring. For example, a display device in a liquid crystal monitor includes both a liquid crystal cell in which a liquid crystal is enclosed between two substrates, a liquid crystal cell in which a driver IC is mounted in the liquid crystal cell, and a liquid crystal monitor in which other devices such as a backlight are mounted. In addition, the short-circuit wiring can be formed simultaneously with the upper wiring so as to be removed when the upper wiring is etched.

Preferably, the short-circuit wiring has a plurality of layers, and in the removing step, when etching the upper layer of the short-circuit wiring, it is preferable to remove a portion of the lower layer and to electrically disconnect it. In addition, the short-circuit wiring preferably has the same composition as the upper wiring. Having the same composition means having the same number of layers formed of the same material, but not the same structure. Alternatively, it is preferable that the short-circuit wiring has a capacity substantially equal to or higher than that of the upper wiring.

The lower layer wiring is a gate line connected to the gate of the TFT formed in the subpixel section, the upper layer wiring is a signal line connected to the source / drain electrode of the TFT, and the short wiring has the same composition as the signal line and is formed simultaneously with the signal line, and is shorted with the signal line. The wiring has a lower Si layer and an upper Al layer, and the lower Si layer can be disconnected when etching the upper Al layer. The signal line and short-circuit wiring also have an indium tin oxide (ITO) intermediate layer between the Si lower layer and the Al upper layer, the ITO intermediate layer is formed by separating a plurality of wires, and the Si lower layer is disconnected at a portion exposed from the separation portion of the ITO intermediate layer. It is also possible to.

When another aspect of the present invention is understood as a method for manufacturing a display device, a method of manufacturing a display device having a display area composed of a plurality of subpixel parts in the form of a matrix, comprising: a plurality of electric signals sent to the plurality of subpixel parts on a substrate; Forming a lower wiring, forming an insulating layer on the plurality of lower wirings, forming a plurality of upper wirings for sending electrical signals to the plurality of subpixels on the insulating layer, forming a short circuit and And all or partly removed to electrically disconnect, and a short circuit due to dielectric breakdown between the short wiring and the lower wiring is more likely to occur than between the upper wiring and the lower wiring or between the lower wiring.

According to another aspect of the present invention, a display device having a display area composed of a plurality of subpixel parts in a matrix form, comprising: a substrate and a plurality of lower layers formed on the substrate and sending electrical signals to the plurality of subpixel parts. Wiring, an insulating layer formed on the plurality of lower layer wirings, a plurality of upper layer wirings formed on the insulating layer to send electrical signals to the plurality of subpixels, and an outer side of the plurality of upper layer wirings formed on the insulating layer and outside the display area. The short circuit is formed, and after the short circuit is formed, all or part of the short circuit is removed and electrically disconnected.

If another aspect of this invention is grasped | ascertained as a wiring board, the some lower layer wiring formed on the board | substrate, the insulating layer formed on the lower layer wiring, the some upper layer wiring formed on the insulating layer, and the lower layer wiring and the insulating layer formed on the insulating layer By short-circuiting through, it has short-circuit wiring which suppresses the short circuit between upper layer or lower layer wiring, and a short circuit wiring is removed all or partly and electrically disconnected after it is formed.

According to another embodiment of the present invention, a display device having a display area composed of a plurality of subpixel parts in a matrix form, comprising: a substrate and a plurality of lower layer wirings formed on the substrate and sending electrical signals to the plurality of subpixel parts. And an insulating layer formed on the plurality of lower layer wirings, a plurality of upper layer wirings formed on the insulating layer to send electrical signals to the plurality of subpixel parts, and short circuits formed on the insulating layer. After a short circuit, the short circuit is electrically disconnected after it is formed.

Example 1

Best Mode for Carrying Out the Invention Embodiments of the present invention will now be described with reference to the drawings. Each figure is for describing an embodiment, the dimensions or shape does not necessarily accurately reflect the actual device and method.

In this embodiment, the TFT (Thin Film Transistor) array substrate has a dummy signal line which is a short circuit in order to prevent a short circuit caused by electrostatic breakdown between the signal line which is an upper layer wiring and the gate line which is a lower layer wiring. The dummy signal line is formed in the outer peripheral region of the TFT array substrate. The dummy signal line has a three-layer structure from a lower layer to a lower silicon layer, an indium tin oxide (ITO) intermediate layer, and an upper layer of aluminum (Al). Although the silicon layer is formed as one continuous wiring at the time of its formation, when the Al layer is patterned, it is etched simultaneously with the Al layer and electrically disconnected between each gate line. In addition, disconnection means forming the isolation | separation part by removing a part of wiring part continuously formed, and does not include the wiring formed by separating previously.

3 is a configuration diagram schematically showing a TFT array substrate in this embodiment. The figure is a TFT array substrate after a wiring pattern is formed. In the figure, 31 is a display area portion composed of a subpixel portion in a matrix form, 33 is a signal line for sending a signal to a source electrode of a TFT, and 34 is a gate line for sending a signal to a gate electrode of a TFT. 32 is an outer periphery area | region part outside the display area part 31, 35 is a short ring, and 36 is a dummy signal line. The short ring 35 and the dummy wiring 36 are formed in the outer circumferential region 32. The dummy wiring 36 is formed outside the signal line which is the outermost of the signal lines in the display area portion 31. In this embodiment, they are formed on the outer side of both side portions of the display area portion 31, respectively. Since the structure in the display area part 31 is the same as that of the TFT array wiring of the prior art, detailed description is abbreviate | omitted. Further, in the color LCD, each subpixel unit has an RGB color filter, and color display is performed by controlling the amount of light from each subpixel unit. One pixel portion is formed by three RGB subpixel portions. In addition, in the monochrome LCD, each sub-pixel portion corresponds to the pixel portion.

4 is a circuit diagram showing a configuration of a short ring. Each gate line and signal line are each connected to one short ring, and each short ring is connected to a common wiring. The short ring is composed of two TFTs and has two terminals. A gate or a signal line is connected to one terminal, and the other terminal is connected to a common wiring. The gate line / signal line is connected to one end of the gate and source / drain of the first TFT, and connected to one end of the source / drain of the second TFT.

The common wiring is connected to one end of the gate and the source / drain of the second TFT, and connected to one end of the source / drain of the first TFT. After the signal line is completed, since the signal line and the gate line are connected to the short ring, a short circuit due to electrostatic breakdown is suppressed. When the high voltage is applied, the TFT is turned on so that the resistance is low. When the voltage is low, the TFT is turned off, so the resistance becomes high. Since normal use is about 5V, even high resistance does not interfere.

The gate line 34 is made of aluminum. The signal line 33 is composed of a silicon layer, an ITO layer, and an aluminum layer from below. The silicon layer is composed of a lower a-Si layer and an upper n + a-Si layer. The dummy signal line 36 has the same composition as the signal line 33 and is formed at the same time as the signal line 33. 9-B is a cross-sectional view showing the structure of the final dummy line 36. The dummy signal line has a three-layer structure of a silicon layer 66, an ITO layer 68, and Al layers 93 and 94. The silicon layer 66 is formed of two layers, an a-Si layer and an n + a-Si resistive layer. The silicon oxide layer 67 is attached to the entire surface on the glass substrate. The final dummy line is in a state where all three layers are separated between the gate lines 53.

In this example, the manufacturing method of a TFT array substrate is demonstrated and it demonstrates according to TFT array wiring which has a lower gate type (reverse stagger type) TFT. Thus, a gate electrode and a gate line are formed in the lower layer, and an insulating layer is deposited thereon. Source / drain electrodes and signal lines are disposed on the insulating layer. A-Si is used as a semiconductor. Formation of each wiring and insulating film is formed by deposition of a material, a photolithography process, and an etching process. The deposition of the material is performed by chemical vapor deposition such as physical vapor deposition or plasma CVD by sputtering or vacuum deposition. Photolithography processing is performed by each process of adhesion of photoresist, photosensitive through a mask pattern, formation of a resist pattern by development, and resist stripping.

The etching treatment is performed by dry etching such as plasma sputtering, RIE sputtering, or wet etching using etching liquid. These treatments are selected to be suitable for each process. These processes are well known techniques and will not be described in detail. In addition, the short ring 35 is formed in the outer circumferential region 32 simultaneously with the formation of the TFT and the respective wirings described below.

The formation of the dummy wiring on the array substrate will be described below in comparison with the formation of the TFT. First, the formation of the gate line layer will be described with reference to FIG. 5. An Al layer of 1000 kPa to 5000 kPa, preferably 2000 kPa is deposited on the entire upper surface of the glass substrate 51 by the sputtering method. Next, a photoresist is coated on the entire surface of the Al layer, and a photoresist development is performed to form a pattern of the photoresist. Using this resist as a protective film, the Al layer is etched by wet etching to form the gate electrode 52 and the gate line 53 of the TFT. The line width of the gate line 53 is usually 10-30 mu m. Thereafter, the resist is peeled off to form the gate line layer.

Next, a description will be given with reference to FIG. 6. First, an oxide insulator layer is formed. A silicon oxide (SiOx) film is deposited on the front surface of the substrate using plasma CVD. In the TFT, the silicon oxide layer functions as the gate insulating layer 61. In the signal line or the dummy wiring, it functions as an insulator layer 66 between the gate line 53 and the signal line / dummy line. The SiO _x film is deposited to a thickness of about 1500-6000 mm 3, and preferably has a thickness of 3500 mm 3. Subsequently, the amorphous silicon layer is deposited by plasma CVD at 200 to 1000 mW, preferably 500 mW.

Further, a silicon nitride layer (SiN _x ) 63 as an etching protective film is deposited by plasma CVD. An etching protective film is deposited in order to prevent etching of the underlying oxide film. The nitride protective film 63 is patterned by photolithography and wet etching. Thereafter, an n + a-Si layer is deposited as the resistive layer by plasma CVD. The a-Si layer and the n + a-Si layer are simultaneously subjected to photolithography and etching to form a pattern of the a-Si layer 62 and the n + a-Si layer 64. The a-Si layer and the n + a-Si layer are also formed of the first layer (Si layer) 67 of the signal line and the dummy line. The line width of the signal line is about 5 mu m.

Subsequently, ITO layers 65 and 68 are deposited on the entire surface of the substrate by sputtering at a thickness of 300-2000 kPa, preferably 400 kPa. A predetermined pattern is formed by photolithography and dry etching (Fig. 7). The ITO layer functions as the pixel electrode 71 and is formed as the second layers 72 and 73 of the signal line and the dummy line. The dummy line is formed by separating an ITO layer between each gate line 53. Of course, the ITO layer is not separated in the signal line and is formed as one continuous wiring. In this way, even if the ITO layers are separated, since the lower Si layer 67 is connected, the capacitance of the dummy wiring becomes substantially the same as the signal line.

Al layers 81 and 82 are deposited on the entire surface of the substrate by a sputtering method to a thickness of 1000-3000 mm 3 (Fig. 8). The Al layer is patterned by photolithography and wet etching (Fig. 9). The Al layer is formed as the source / drain electrodes 91 and 92. It is also formed on the signal line and the dummy line as these uppermost layers 93 and 94. In the dummy line, an Al layer is formed in a pattern separated from each gate wiring. The spacing 95 of the Al wirings is about 10 mu m. In the wet etching process of the Al layer, after the Al layer is etched, the Si layer 67 exposed through the separating portion 74 of the ITO layer is also etched and disconnected. Therefore, after the Al layers 93 and 94 are patterned, the dummy line is in an electrically disconnected state between the gate lines 53.

At the same time as the wiring pattern, a short ring in the outer circumferential region is formed. Therefore, after the Al layer is patterned as the uppermost layer and the signal line is completed, the short ring functions between each signal line and the gate line. After the short ring starts to function, a short circuit due to electrostatic breakdown between the gate line and the signal line is effectively suppressed by the short ring.

In this embodiment, since the dummy signal line serving as the short-circuit wiring is formed in the outer circumferential region, the short circuit caused by the electrostatic breakdown between the gate line serving as the lower wiring and the signal line serving as the upper wiring can be prevented. Since the dummy wiring is disconnected after a specific step, even when the dummy signal line is shorted with two or more gate lines, it is possible to prevent a short circuit between the gate lines. By disconnecting the dummy wirings between the respective gate wirings, a short circuit between the gate lines can be prevented even if any gate wiring and the dummy line are shorted. In addition, it is preferable that the dummy wiring has substantially the same capacitance or more as the signal line.

In this embodiment, the dummy wiring is disconnected when the signal line is completed. This is because, when the signal line is completed, the short ring in the outer circumferential region functions between each signal line and the gate line, so that the short ring can prevent a short circuit due to dielectric breakdown between the wirings. In addition, since the disconnection process of this dummy wiring may be performed until the final product as a display is completed, it is not limited to the completion of a signal line. Even if a short ring exists, short circuit prevention can be further ensured by providing a dummy wiring. However, by disconnecting the etching process of the uppermost layer of the signal line, it is possible to disconnect without newly adding the process.

In addition, the dummy wiring is not limited to three layers but may have two or less layers or four or more layers. In this embodiment, it is also possible not to form the ITO layer which is a 2nd layer. However, in order to make it easier to cause breakdown between the dummy line and the gate line than between the signal line and the gate line, it is preferable that the dummy wiring has a capacity almost equal to or higher than that of the signal line. Therefore, the dummy wiring preferably has the same composition as the signal line.

In the present embodiment, when etching the aluminum layer by sputtering, ITO is not formed by dividing into a plurality of wirings, but it is also possible to disconnect the dummy signal line by etching ITO and silicon simultaneously with Al etching. In this case, the ITO layer is formed as one continuous wiring like the silicon layer. Moreover, even when wet etching an aluminum layer, if the etching agent can etch ITO simultaneously with Al, ITO may not be dividedly formed. Amorphous ITO can be etched with a conventional etchant of Al. In the case where the ITO layer is attached behind the Al layer, the ITO layer may not be formed on the dummy signal line. This is because a sufficient capacity of the dummy wiring is ensured at the time when the Al layer is formed.

In this embodiment, an Al layer of a dummy line or a signal line is attached behind the ITO layer. However, it is also possible if ITO is last attached. In this case, Al and Si are etched simultaneously with ITO to disconnect them. Of course, the formation of the Al layer divided into a plurality of wirings is not excluded. The present invention can also be applied to a staggered TFT.

In the top gate TFT, the wiring formed on the insulating layer is a gate wiring, so that the upper wiring often has a one-layer structure. When the gate line and the dummy signal line as the upper layer wirings are formed only of the Al layer, the dummy signal lines are first formed as one continuous Al wiring. Thereafter, it is disconnected before the final product is completed. For example, it is disconnected just before the electrical inspection of the TFT array is performed. In this case, an additional process is required for the disconnection treatment. However, the dummy line of the present invention is particularly effective when the upper wiring has a plurality of layers.

Example 2.

As another embodiment, an embodiment in which the short-circuit wiring of the present invention is applied to the lead wire portion of the gate wiring will be described. The lead wire portion of the gate wiring refers to wiring of a portion where the gate wiring of the TFT array wiring is connected to the driver IC in the outer peripheral region. 10 is a configuration diagram schematically showing a lead portion of a gate wiring formed in an outer peripheral region on a TFT array substrate. In the drawing, reference numeral 101 denotes a lead wire of the gate wiring, 102 a short ring, and 103 a silicon wiring. The short ring 102 has a configuration in which two short rings of FIG. 4 are connected in series.

In the silicon wiring 103, as described in the formation of the signal line, an n-a-Si layer is formed as an a-Si layer and a resistive layer of the TFT. The silicon wiring 103 is formed to intersect with the gate drawing wiring portion 101 through the silicon oxide layer. The thickness of the silicon wiring is the same as that of the silicon layer of the dummy line. Moreover, the line width of a silicon wiring is usually 100-200 micrometers. 104 denotes a common peripheral line to which the short ring is connected, 105 denotes a pad, and 106 denotes a gate wiring portion. The gate wiring 106 and the common peripheral line 104 are not connected to each other.

Since the gate lead-out wiring portion 101 is formed with high density of wires, a short circuit due to electrostatic insulation breakdown between the lead wires is likely to occur. The spacing between the lead wirings is about 20 mu m, and the spacing between the lead wirings and the silicon wirings is usually 3500 kPa. Therefore, the lead wires adjacent to each other are not shorted, and the lead wires and the upper layer silicon wires cause a short circuit due to electrostatic destruction. By forming a silicon wiring, which is a short wiring, in the upper layer of the gate lead-out line through the insulating layer, a short circuit between the gate lines can be prevented.

The silicon wirings are all removed in the same process as the silicon layer of the dummy signal line is disconnected in the first embodiment. By removing all the silicon wirings, even if the silicon wirings are short-circuited with two or more lead wires in the lower layer, it is possible to prevent a short circuit between the gate wirings.

It is also possible that the gate lead line is formed by the lower gate line and the upper signal line on the insulating layer. In this case, the lower layer wiring and the upper layer wiring are electrically connected through the through holes. In this case, the short-circuit wiring has the same composition as the signal line, and has a Si lower layer, an ITO intermediate layer, and an Al upper layer. In addition, not all the short-circuit wirings are removed, but part of them is removed and disconnected. Short-circuit wiring is disconnected between each gate lead-out wiring. The width of the separator varies with the density of the leader line and is about 10 μm.

In the above two embodiments, Al was used as the metal layer, but Cr, Mo-Ta, Ta, and the like can be used as the metal wiring layer. As the gate insulating film or the protective film, silicon oxide or silicon nitride may be appropriately used, and Ta205 deposited by the sputtering method may be used as the insulating film. In this example, a-Si is used as the semiconductor, but it is of course possible to form a TFT or a wiring using polysilicon.

The short-circuit wiring of the present invention is not only limited to array wiring having an active element, but is also applicable to a device that does not include an active element in the form of a simple matrix. In addition, although TFT has been described as an active element as an example, it is also possible to apply the dummy wiring of the present invention to an array wiring having other active elements such as MIM. The present invention is not limited to the liquid crystal display device, but is also applicable to other display devices such as organic electroluminescence.

While the preferred embodiments of the invention have been described in detail, it will be readily apparent that various modifications and variations can be made herein without departing from the spirit and scope of the invention as defined in the appended claims.

1 is a schematic configuration diagram showing a sub-pixel of the prior art.

2 is a schematic configuration diagram showing a TFT array substrate of the prior art;

Fig. 3 is a schematic block diagram showing the TFT array substrate of the first embodiment.

4 is a schematic circuit diagram showing a short ring of the first embodiment.

5A and 5B are schematic configuration diagrams showing a method for forming a TFT array substrate wiring line of the first embodiment.

6A and 6B are schematic configuration diagrams showing a method for forming a TFT array substrate wiring line of the first embodiment.

7A and 7B are schematic configuration diagrams showing a method for forming a TFT array substrate wiring line of the first embodiment.

8A and 8B are schematic configuration diagrams showing a method for forming a TFT array substrate wiring line of the first embodiment.

9A and 9B are schematic configuration diagrams showing a method for forming a TFT array substrate wiring line of the first embodiment.

Fig. 10 is a schematic configuration diagram showing the gate lead-out wiring portion of the second embodiment.

<Description of the symbols for the main parts of the drawings>

11: TFT

12: gate electrode

13: gate insulation layer

14: amorphous silicon (a-Si) layer

15: resistive layer,

16: source electrode

17: drain electrode

18: pixel electrode

19: gate line

21: display area

22: outer area

23: signal line

24: gate line

25: short ring

31: display area

33: signal line

34: gate line

32: outer area

35: short ring

36: dummy signal line

53: gate line

66: silicon layer

67 silicon oxide layer

68: ITO layer

71: pixel electrode

72 73: second floor

81 82: Al layer

91 92: source / drain electrodes

93 94: Top floor

101: leader line

102: short ring

103: silicon wiring

104: common circumference

105: pad

106: gate wiring part

Claims (13)

In the manufacturing method of the display apparatus which has a display area comprised from the several subpixel part of matrix form, Forming a plurality of lower layer wirings for transmitting an electrical signal to the plurality of subpixel units on a substrate; Forming an insulating layer on the plurality of lower layer wirings; Forming a plurality of upper layer wirings for transmitting an electrical signal to the plurality of subpixel units on the insulating layer, and forming short-circuit wirings outside the plurality of upper layer wirings and outside of the display area; And removing at least a portion of the short circuit to electrically disconnect the short circuit. The method of claim 1, wherein the short wiring is formed simultaneously with the upper wiring and is removed when the upper wiring is etched. The method of claim 1, wherein the short-circuit wiring is made of a plurality of layers, And removing the portion of the lower layer to electrically disconnect the lower layer when the upper layer of the short circuit is etched. The method of claim 1, wherein the short wiring has the same composition as the upper wiring. The method of claim 1, wherein the short-circuit wiring has a capacitance substantially equal to or higher than that of the upper wiring. The semiconductor device according to claim 1, wherein the lower layer wiring line is a gate line connected to a gate of a TFT formed in the subpixel section, The upper wiring is a signal line connected to a source / drain electrode of the TFT, The short-circuit wiring has the same composition as the signal line and is formed simultaneously with the signal line, And a lower Si layer and an upper Al layer in the signal line and the short circuit, and the lower Si layer is disconnected when the upper Al layer is etched. The semiconductor device of claim 6, wherein the signal line and the short circuit line further include an ITO intermediate layer between the Si lower layer and the Al upper layer. The ITO intermediate layer is formed by separating a plurality of wires, And wherein the lower Si layer is disconnected at a portion exposed from the separation portion of the ITO intermediate layer. In the manufacturing method of the display apparatus which has a display area comprised from the several subpixel part of matrix form, Forming a plurality of lower layer wirings for transmitting an electrical signal to the plurality of subpixel units on a substrate; Forming an insulating layer on the plurality of lower layer wirings; Forming a plurality of upper layer wirings and short-circuit wirings for transmitting an electrical signal to the plurality of subpixel units on the insulating layer; Removing at least a portion of the short circuit and electrically disconnecting the circuit; A short circuit due to dielectric breakdown between the short wiring and the lower wiring is more likely to occur between the upper wiring and the lower wiring or between the lower wirings. In a display device having a display area composed of a plurality of subpixel parts in a matrix form, Substrate, A plurality of lower layer wirings formed on the substrate and sending electrical signals to the plurality of subpixel units; An insulating layer formed on the plurality of lower layer wirings, A plurality of upper wirings formed on the insulating layer to send electrical signals to the plurality of subpixel units; It is formed on the said insulating layer, and has the short circuit wiring formed in the outer side of the said several upper layer wiring, and the outer side of the said display area, And the at least part of the short wiring is removed and electrically disconnected. The display device of claim 9, wherein the short wiring has the same composition as the upper wiring. The display device of claim 9, wherein the short wiring has a capacitance substantially the same as or higher than that of the upper wiring. A plurality of lower layer wirings formed on the substrate, An insulating layer formed on the lower wiring line, A plurality of upper wirings formed on the insulating layer, A short circuit formed on the insulating layer, the short circuit forming a short circuit between the upper layer wirings and the lower layer wirings by shorting the lower wiring through the insulating layer; At least a portion of the short circuit is removed and electrically disconnected after the short circuit is formed. In a display device having a display area composed of a plurality of subpixel parts in a matrix form, Substrate, A plurality of lower layer wirings formed on the substrate to send electrical signals to the plurality of subpixel units; An insulating layer formed on the plurality of lower layer wirings, A plurality of upper wirings formed on the insulating layer to send electrical signals to the plurality of subpixel units; Short circuit wiring formed on the insulating layer, The short-circuit wiring is short-circuited with the lower wiring through the insulating layer, The short circuit is electrically disconnected after being formed.