JPH11249166A - Active matrix substrate and production thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display(LCD) device capable of reducing short-circuitting defects and improving yield. SOLUTION: On a substrate, gate wiring 14 and additional capacitive wiring 15 are formed, on that wiring, a gate insulating film is formed as well, on that film, a TFT 13, source wiring 16, drain electrode 19 and connecting electrode 18 are formed, on these components, an inter-layer insulating film is formed and on that film, a pixel electrode is provided. Concerning such an active matrix substrate, in areas 1, 2 and 3, the gate insulating film in the area near the connecting electrode 18 is removed and at the other sections, the gate insulating film is left. The inter-later insulating film is formed on that remaining film. Thus, the short-circuitting defects of the gate wiring 14 and the additional capacitive wiring 15 with the source wiring 16, drain electrode 13 and connecting electrode 18 can be reduced. The removal of the gate insulating film can be formed simultaneously with the formation of a terminal part and it is not necessary to increase the number of processes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having a large display area, enabling high-definition display, and achieving a high aperture ratio.

[0002]

2. Description of the Related Art FIG. 6 shows a thin film transistor (hereinafter referred to as TF).
FIG. 1 shows an equivalent circuit diagram of an active matrix substrate of a liquid crystal display device formed using T). Pixel electrodes 12 are arranged in rows and columns on a transparent insulating substrate 11 such as glass, and a TFT 13 is connected to each pixel electrode 12 as a switching element and connected to the pixel electrode 12. I have. Further, gate lines 14 as scanning lines and additional capacitance lines 15 are alternately formed along the rows of the pixel electrodes 12. In addition, source lines 16 which are signal lines are formed along the columns of the pixel electrodes 12.

[0003] The applicant has proposed in Japanese Patent Application Laid-Open No. 9-152625 a liquid crystal display device having a large display area, enabling high-definition display, and achieving a higher aperture ratio. The proposal is shown in FIGS. FIG. 7 is a plan view of the active matrix substrate in a state where the interlayer insulating film 17 and the pixel electrode 12 are not formed on the substrate 11, and FIG. 8 is a plan view of the active matrix substrate on which the pixel electrode 12 is formed. FIG. 9 is a cross-sectional view taken along the line AA of FIGS. 7 and 8. The pixel electrode 12 is formed on the interlayer insulating film 17, and is formed through a contact hole 28 penetrating through the interlayer insulating film 17.
The FT 13 is connected to the drain electrode 19 and the connection electrode 18. The connection electrode 18 and the drain electrode 19 are electrically connected.

FIG. 11 shows the structure of the TFT 13 shown in FIG. On the substrate 11, a gate electrode 22, a gate insulating film 20, a silicon semiconductor layer 23, and an etching stopper 24 as a channel protection layer are sequentially formed. These three
The layers are sequentially formed sequentially. Next, the first n ⁺ silicon film 2
5 and a second n ⁺ silicon film 26 formed separately, the first n ⁺ silicon film 25 and the source electrode 27 of the two layers formed are electrically connected, the second n ⁺ silicon film 26 And 2
It is electrically connected to the drain electrode 19 for forming the layer.

FIG. 10 shows a method of manufacturing an active matrix substrate having a cross section AA in FIGS. 7 and 8. FIG. 10 (a)
As shown in FIG. 7, after a gate wiring 14 and an additional capacitance wiring 15 (both not shown) are formed on a substrate 11, a gate insulating film 20 is formed. Next, as shown in FIG.
When the FT 13 is formed, the source wiring 16 and the connection electrode 18 are formed. Next, as shown in FIG. 10C, an interlayer insulating film 17 is formed on the source wiring 16 and the connection electrode 18. Then, the pixel electrode 12 is formed on the interlayer insulating film 17 so as to overlap with the source wiring 16.

As described above, the active matrix substrate is configured. Since the interlayer insulating film 17 is formed on the gate wiring 14 and the source wiring 16, the pixel electrode 12 can overlap each wiring. With such a structure, the aperture ratio can be improved, and further, by shielding the electric field caused by each wiring, there is an effect that poor alignment of the liquid crystal can be suppressed. In addition, since the pixel electrode 12 is on the interlayer insulating film 17, short circuit failure with the source wiring 16 can be reduced, and the yield can be improved.

Furthermore, the applicant has proposed a method of reducing the short-circuit defect with the source wiring 16 and improving the yield in Example 5 of Japanese Patent Laid-Open No. 10-10583. The proposal is shown in FIG. 12 and FIG. FIG. 12 is a plan view of the active matrix substrate, and FIG. 13 is a cross-sectional view taken along the line AA.

[0008] A region 1 indicated by oblique lines in FIG. 12 is a region surrounded by the source wiring 16, the additional capacitance wiring 15, and the connection electrode 18. The region 2 is a region surrounded by the source wiring 16, the additional capacitance wiring 15, the connection electrode 18, and the gate wiring 14. The region 3 is a region surrounded by the source wiring 16, the additional capacitance wiring 15, and the gate wiring 14.

In regions 1, 2, and 3, gate insulating film 20 is removed. With this configuration, the gate insulating film 2
The patterning failure of the n ⁺ silicon film 25, which is the conductive film on 0, and the etching residue can be removed at the same time. Therefore, the short circuit failure caused by them can be further reduced.

[0010]

However, in the case where the gate insulating film 20 is removed in the regions 1, 2, and 3 in FIG. 12, the following problem occurs. That is, the gate wiring 1 is removed to remove the gate insulating film 20.
4. If the patterning failure of the additional capacitance wiring 15 occurs, the conductive film is exposed in the removal region. As a result, the possibility of short-circuit failure with the conductive film due to poor patterning of the source wiring 16, the connection electrode 18, and the drain electrode 19, which cannot occur conventionally, increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems described above, and an object of the present invention is to provide an active matrix substrate capable of reducing short circuit defects and improving yield.

[0012]

An active matrix substrate according to claim 1, wherein a scanning line and an additional capacitance line for controlling a switching element are formed on the substrate, a gate insulating film is formed thereon, and Forming the switching elements in a matrix on an insulating film, forming a signal wiring for supplying a data signal to the switching element so as to be orthogonal to the scanning wiring, and forming a connection between a drain electrode and a pixel electrode of the switching element. Forming a connection electrode to be used, forming an interlayer insulating film on the switching element, the connection electrode, and the signal wiring; forming the pixel electrode on the interlayer insulating film; An active matrix substrate in which the connection electrode and the drain electrode of the switching element are connected by a contact hole penetrating Wherein at least a proximity region along a part of the connection electrode forms the interlayer insulating film on the substrate, and the other portion forms the gate insulating film and the interlayer insulating film. And

According to a second aspect of the present invention, there is provided a method of manufacturing an active matrix substrate, comprising: forming a scanning line and an additional capacitance line for controlling a switching element on a substrate; forming a gate insulating film thereon; Forming a switching element in a matrix, forming a signal line for supplying a data signal to the switching element so as to be orthogonal to the scanning line, and using a connection used as a connection between a drain electrode and a pixel electrode of the switching element. Forming electrodes,
An interlayer insulating film is formed on the switching element, the connection electrode, and the signal wiring; the pixel electrode is formed on the interlayer insulating film; and the pixel electrode is connected by a contact hole penetrating the interlayer insulating film. In the method for manufacturing an active matrix substrate in which an electrode and a drain electrode of the switching element are connected, after forming the gate insulating film on the scanning wiring and the additional capacitance wiring on the substrate, at least the connection is performed. A step of removing the gate insulating film in a region adjacent to a part of the electrode and leaving the gate insulating film in the other part; and a region in the vicinity of the connection electrode and the gate insulating film left. On the membrane,
A step of forming the interlayer insulating film.

The operation of the above configuration will be described. Claim 1
With the configuration described above, it is possible to reduce short-circuit defects between the scanning wiring and the additional capacitance wiring and the signal wiring, the drain electrode, and the connection electrode. Further, in forming a scanning wiring, a disconnection failure of a signal wiring caused by a patterning failure which is likely to occur due to unevenness of a gate insulating film can be reduced.

According to the manufacturing method of the second aspect, the removal of the gate insulating film can be performed at the same time when the terminal portion is formed, and the process is not increased.

[0016]

(Embodiment 1) An active matrix substrate according to Embodiment 1 will be described with reference to FIGS. FIG. 1 is a plan view of an active matrix substrate, FIG. 2 is a sectional view taken along line AA, and FIG.
This is a method for manufacturing the A section.

Pixel electrodes 12 are arranged close to each other in rows and columns on a transparent insulating substrate 11 such as glass. A TFT 13 is connected to each of the pixel electrodes 12 as a switching element. It is connected. Further, gate lines 14 as scanning lines and additional capacitance lines 15 are alternately formed along the rows of the pixel electrodes 12. In addition, source lines 16 which are signal lines are formed along the columns of the pixel electrodes 12.

The pixel electrode 12 is formed on the interlayer insulating film 17 and, via a contact hole (corresponding to 28 in FIG. 8) penetrating the interlayer insulating film 17, the drain electrode 19 of the TFT 13 is formed.
And the connection electrode 18. The connection electrode 18 and the drain electrode 19 are electrically connected. This structure is the same as the structure disclosed in Japanese Patent Application Laid-Open No. 9-152625.

The present invention is different from the conventional example in the region 1,
In steps 2 and 3, the gate insulating film 20 in the region adjacent to the connection electrode 18 is removed, and the other portions are removed.
Is different. 4 indicated by hatching in FIG.
Are regions where the gate insulating film 20 is removed.

In the region 1, the gate insulating film 20 in a region adjacent to the connection electrode 18 is removed. The removal region 4 of the gate insulating film has a U-shape along the connection electrode 18. The gate insulating film 20 is left except for the removal region 4 of the gate insulating film. The removal region 4 of the gate insulating film may have any shape as long as it includes a portion along the connection electrode 18 in addition to the U-shape.

Similarly, in the region 2, the gate insulating film 20 in the region adjacent to the connection electrode 18 is removed. The removal region 4 of the gate insulating film is L-shaped along the connection electrode 18. The gate insulating film 20 except for the region 4 where the gate insulating film is removed
Leave. The removal region 4 of the gate insulating film may have any shape as long as it includes a portion along the connection electrode 18 in addition to the L shape.

Similarly, in the region 3, the gate insulating film 20 in the region adjacent to the connection electrode 18 is removed. The removal region 4 of the gate insulating film has a band shape along the connection electrode 18.
The gate insulating film 20 is left except for the removal region 4 of the gate insulating film. The removal region 4 of the gate insulating film may have any shape as long as it includes a portion along the connection electrode 18 in addition to the band shape.

The region adjacent to the connection electrode 18 which is the region 4 where the gate insulating film is removed is not limited to the shape shown in FIG.
It changes depending on the shape of the connection electrode 18 and the location where the defect occurs. That is, any area may be used as long as it is an adjacent area along at least a part of the connection electrode.

Next, a method of manufacturing the region 1 will be described. The same applies to the case of the region 2 and the region 3. As shown in FIG. 3A, a gate wiring 14 and an additional capacitance wiring 15 (both not shown) are formed on the substrate 11 by using tantalum for about 30 minutes.
It is formed with a thickness of 0 nm. Thereafter, the gate insulating film 20 is formed to a thickness of about 300 nm using silicon nitride.

Next, as shown in FIG.
In the above, the gate insulating film 20 in the region near the connection electrode 18
Is removed. The region to be removed is the removed region 4 of the gate insulating film in FIG. Other portions leave the gate insulating film 20. The removal of the gate insulating film 20 can be performed simultaneously with the formation of the terminal portion, and does not increase the process. Similarly, in the case of the regions 2 and 3, the gate insulating film 20 in the region adjacent to the connection electrode 18 is removed.
The region to be removed is the removed region 4 of the gate insulating film in FIG. Other portions leave the gate insulating film 20.

Next, as shown in FIG.
At the time of forming 3, the source wiring 16 and the connection electrode 18 are formed. Next, as shown in FIG. 3D, an interlayer insulating film 17 is formed on the source wiring 16 and the connection electrode 18. Then, the pixel electrode 12 is formed on the interlayer insulating film 17 so as to overlap with the source wiring 16. The pixel electrode 12 is made of ITO (Indium Tin Oxide) and has a thickness of about 100 nm. The active matrix substrate is configured as described above.

When patterning failure of the gate wiring 14 and the additional capacitance wiring 15 occurs in at least one of the regions 1, 2, and 3, the conductive film is exposed in the removal region 4 of the gate insulating film. Since the other portion has the gate insulating film 20, short circuit failure with the conductive film due to poor patterning of the source wiring 16, the connection electrode 18, and the drain electrode 19 can be reduced.

Therefore, by adopting such a structure, it is possible to reduce short-circuit defects between the gate wiring 14, the additional capacitance wiring 15, the source wiring 16, the drain electrode 13, and the connection electrode 18.

Further, when the source wiring 16 is formed, a disconnection failure of the source wiring 16 caused by a patterning failure which is likely to be caused by the unevenness of the gate insulating film 20 can be reduced.

(Embodiment 2) The active matrix substrate of Embodiment 2 will be described with reference to FIGS.
FIG. 4 is a plan view of the active matrix substrate, and FIG.
Is a sectional view taken along the line A-A.

In the regions 1, 2, and 3, the embodiment 2 is the same as the embodiment 1 except that the gate insulating film 20 is removed. Region 1,
In steps 2 and 3, the gate insulating film 20 in the vicinity of each wiring (the source wiring 16, the gate wiring 14, the additional capacitance wiring 15, and the connection electrode 18) is removed.
Is different in that the gate insulating film 20 remains. FIG.
4 indicates a region where the gate insulating film 20 is removed. The manufacturing method for removing the gate insulating film 20 is the same as in the first embodiment.

When patterning failure of the gate wiring 14 and the additional capacitance wiring 15 occurs in at least one of the regions 1, 2, and 3, the conductive film is exposed in the removal region 4 of the gate insulating film. Other than that, since there is a gate insulating film 20, the source wiring 16, the connection electrode 1
8. Short circuit failure with the conductive film due to poor patterning of the drain electrode 19 can be reduced.

Therefore, by adopting such a structure, it is possible to reduce short-circuit defects between the gate wiring 14, the additional capacitance wiring 15, and the source wiring 16, the drain electrode 13, and the connection electrode 18.

[0034]

According to the structure of the present invention, the gate wiring 1
4. Short circuit failure between the additional capacitance wiring 15, the source wiring 16, the drain electrode 13, and the connection electrode 18 can be reduced. Further, in forming the source wiring 16, a disconnection failure of the source wiring 16 caused by a patterning defect which is likely to be caused by the unevenness of the gate insulating film 20 can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view of an active matrix substrate according to a first embodiment.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a manufacturing method of the AA cross section of FIG. 1;

FIG. 4 is a plan view of an active matrix substrate according to a second embodiment.

FIG. 5 is a sectional view taken along line AA of FIG. 4;

FIG. 6 is an equivalent circuit diagram of an active matrix substrate of a liquid crystal display device formed using a TFT.

FIG. 7 is a plan view of the active matrix substrate at a stage where the interlayer insulating film 17 and the pixel electrode 12 are not formed on the substrate 11.

FIG. 8 is a plan view of the active matrix substrate on which the pixel electrodes 12 are formed.

FIG. 9 is a cross-sectional view taken along the line AA of FIGS. 7 and 8;

FIG. 10 shows a method for manufacturing an active matrix substrate having a cross section AA in FIGS. 7 and 8;

FIG. 11 shows a configuration of a TFT 13.

FIG. 12 is a plan view of a conventional active matrix substrate.

13 is a cross-sectional view taken along the line AA of FIG.

[Explanation of symbols]

 1 region 2 region 3 region 4 removal region of gate insulating film 11 substrate 12 pixel electrode 13 TFT 14 gate wiring 15 additional capacitance wiring 16 source wiring 17 interlayer insulating film 18 connection electrode 19 drain electrode 20 gate insulating film 22 gate electrode 27 source electrode 28 Contact hole

Claims (2)

[Claims] 1. A scanning line and an additional capacitance line for controlling a switching element are formed on a substrate, a gate insulating film is formed thereon, and the switching element is formed in a matrix on the gate insulating film. Forming a signal wiring for supplying a data signal to the switching element so as to be orthogonal to the scanning wiring, forming a connection electrode used as a connection between a drain electrode of the switching element and a pixel electrode,
An interlayer insulating film is formed on the switching element, the connection electrode, and the signal wiring; the pixel electrode is formed on the interlayer insulating film; and the pixel electrode is connected by a contact hole penetrating the interlayer insulating film. In an active matrix substrate in which an electrode and a drain electrode of the switching element are connected, at least a proximity region along a part of the connection electrode forms the interlayer insulating film on the substrate, and other portions are An active matrix substrate comprising the gate insulating film and the interlayer insulating film. 2. A scanning line and an additional capacitance line for controlling a switching element are formed on a substrate, a gate insulating film is formed thereon, and the switching element is formed in a matrix on the gate insulating film. Forming a signal wiring for supplying a data signal to the switching element so as to be orthogonal to the scanning wiring, forming a connection electrode used as a connection between a drain electrode of the switching element and a pixel electrode,
An interlayer insulating film is formed on the switching element, the connection electrode, and the signal wiring; the pixel electrode is formed on the interlayer insulating film; and the pixel electrode is connected by a contact hole penetrating the interlayer insulating film. In a method for manufacturing an active matrix substrate in which an electrode and a drain electrode of the switching element are connected, after forming the gate insulating film on the scanning wiring and the additional capacitance wiring on the substrate, at least the connection A step of removing the gate insulating film in an adjacent region along a part of the electrode, and leaving the gate insulating film in the other part; and a step of removing the gate insulating film in a proximity region of the connection electrode. A method for manufacturing an active matrix substrate, comprising a step of forming the interlayer insulating film on a film.