KR100451515B1 - Method for fabricating capacitor of semiconductor device - Google Patents
Method for fabricating capacitor of semiconductor device Download PDFInfo
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- KR100451515B1 KR100451515B1 KR10-2002-0036669A KR20020036669A KR100451515B1 KR 100451515 B1 KR100451515 B1 KR 100451515B1 KR 20020036669 A KR20020036669 A KR 20020036669A KR 100451515 B1 KR100451515 B1 KR 100451515B1
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- 239000003990 capacitor Substances 0.000 title claims abstract description 49
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910000859 α-Fe Inorganic materials 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 16
- 230000010354 integration Effects 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체소자의 캐패시터 제조방법에 관한 것으로, 반도체기판의 디램셀 영역과 로직부 및 디램페리부에 제1 및 2 트렌치를 형성하는 단계; 상기 디램셀영역의 제1트렌치 및 로직부 및 디램페리부의 제2트렌치내에 트렌치산화막을 형성하는 단계; 상기 제1트렌치내에 매립된 트렌치 산화막의 일부를 제거하는 단계; 상기 트렌치산화막의 일부가 제거된 제1트렌치의 측면을 포함한 반도체기판의 표면상에 산화막을 형성하는 단계; 상기 산화막상에 폴리실리콘층을 형성한후 이를 선택적으로 패터닝하여 디램셀영역의 캐패시터 플레이트전극과 게이트전극을 형성하는 단계를 포함하여 구성된다.The present invention relates to a method of manufacturing a capacitor of a semiconductor device, comprising: forming first and second trenches in a DRAM cell region, a logic unit, and a DRAM ferrite unit of a semiconductor substrate; Forming a trench oxide film in a first trench and a logic portion of the DRAM cell region and a second trench in the DRAM ferrite portion; Removing a portion of the trench oxide film embedded in the first trench; Forming an oxide film on a surface of the semiconductor substrate including a side surface of the first trench from which a portion of the trench oxide film is removed; And forming a polysilicon layer on the oxide film and then selectively patterning the polysilicon layer to form a capacitor plate electrode and a gate electrode of the DRAM cell region.
Description
본 발명은 반도체소자의 캐패시터 제조방법에 관한 것으로서, 보다 상세하게는 깊은 트렌치를 이용한 플라나셀의 캐패시턴스를 증가시킬 수 있는 반도체소자의 캐패시터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, to a method for manufacturing a capacitor of a semiconductor device capable of increasing the capacitance of a planar cell using a deep trench.
모스(MOS) 캐패시터는 게이트 공정시, 동시에 만들어져서 공정이 매우 단순한 이점이 있으나 단위면적이 너무 커서 고집적화 추세인 현재의 디램으로는 적합하지 않다.The MOS capacitor is made at the same time during the gate process, so the process has a very simple advantage, but the unit area is so large that it is not suitable for the current DRAM which is highly integrated.
이는 일반적인 디램이 입체적인 캐패시터 구조를 가지고 있는데 반해, 모스 캐패시터는 평판위에 캐패시터를 형성하여 동작시키는 이차원적인 구조를 가져야 하기 때문이다.This is because general DRAMs have a three-dimensional capacitor structure, whereas MOS capacitors must have a two-dimensional structure that operates by forming a capacitor on the plate.
여기서, 플라나 셀의 동작월리를 간단히 설명하면, 모스 캐패시터의 플레이트에 전압을 걸어 웰스토리지 노드에 강한 반전층(inversion layer)을 형성한 상태와 그 반전층의 전하를 외부전압을 이용하여 디플리션 상태로 만들어 주었을 때 발생하는 전하량의 차이를 이용하여 데이터를 저장하는 방식의 디램이다.Here, the operation wall plan of the planar cell will be briefly described. The voltage is applied to the plate of the MOS capacitor to form a strong inversion layer at the well storage node, and the charge of the inversion layer is depleted using an external voltage. It is a DRAM that stores data by using the difference in the amount of charge generated when it is made into a state.
그러나, 웰을 스토리지노드로 사용하기 때문에 입체적인 구조로 가지 못하고 평판구조로 가져갈 수 밖에 없어서 스토리지노드 셀이라고 불리는 것이다. 충분한 캐패시터 용량을 가져가기 위해서는 그만큼의 면적이 필요하므로 셀 단위면적이 커지게 되므로 플라나 셀의 집적화에 가장 큰 걸림돌이 되고 있다.However, since the well is used as a storage node, it cannot be moved into a three-dimensional structure but can be brought into a flat structure, which is called a storage node cell. In order to have sufficient capacitor capacity, such area is required, which increases the cell unit area, which is the biggest obstacle to the integration of planar cells.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 단위 면적이 동일한 셀에서 캐패시턴스를 증가시켜 디램의 센싱 마진을 증가시키고 단위 셀의 크기를 줄여 집적률을 증가시키는 한편 셀간 누설전류를 최소화시킬 수 있는 반도체소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, the capacitance in the cell of the same unit area increases the sensing margin of the DRAM to increase the integration rate by reducing the size of the unit cell while leakage current between cells Its purpose is to provide a method for manufacturing a semiconductor device that can minimize the
도 1은 본 발명에 따른 반도체소자의 캐패시터의 제조방법에 있어서, 캐패시터의 문턱전압 조절용 마스크 및 트렌치산화막의 레이아웃도이다.1 is a layout diagram of a mask and a trench oxide film for adjusting the threshold voltage of a capacitor in a method of manufacturing a capacitor of a semiconductor device according to the present invention.
도 2 내지 도 5는 본 발명에 따른 반도체소자의 캐패시터 제조방법을 설명하기 위한 캐패시터 제조 공정 단면도이다.2 to 5 are cross-sectional views of a capacitor manufacturing process for explaining a capacitor manufacturing method of a semiconductor device according to the present invention.
도 6은 본 발명에 따른 반도체소자의 캐패시터 제조공정을 통해 얻어진 반도체소자의 캐패시터의 레이아웃도이다.6 is a layout view of a capacitor of a semiconductor device obtained through a capacitor manufacturing process of the semiconductor device according to the present invention.
[도면부호의설명][Description of Drawing Reference]
11 : 반도체기판 13a : 제1트렌치11: semiconductor substrate 13a: first trench
13b : 제2트렌치 15a, 15b : 트렌치산화막13b: second trenches 15a and 15b: trench oxide films
17 : 문턱전압 조절용 마스크 19a, 19b, 19 : 이온주입영역17: threshold voltage control mask 19a, 19b, 19: ion implantation area
21 : 산화막 23 : 폴리실리콘층21: oxide film 23: polysilicon layer
23a : 플레이트전극 23b : 게이트전극23a: plate electrode 23b: gate electrode
25 : 활성영역 27 : 비트라인콘택25: active area 27: bit line contact
A : 디램셀부 B : 로직부 및 디램페리부A: DRAM Cell B: Logic and DRAM Ferri
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 캐패시터 제조방법 은, 반도체기판의 디램셀 영역과 로직부 및 디램페리부에 제1 및 2 트렌치를 형성 하는 단계; 상기 디램셀영역의 제1트렌치 및 로직부 및 디램페리부의 제2트렌치 내에 트렌치산화막을 형성하는 단계; 상기 제1트렌치내에 매립된 트렌치 산화막의 일부를 제거하는 단계; 상기 트렌치산화막의 일부가 제거된 제1트렌치의 측면을 포함한 반도체기판의 표면상에 산화막을 형성하는 단계; 상기 산화막상에 폴리 실리콘층을 형성한후 이를 선택적으로 패터닝하여 디램셀영역의 캐패시터 플레이트 전극과 게이트전극을 형성하는 단계를 포함하여 구성되는 것을 특징 으로한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: forming first and second trenches in a DRAM cell region, a logic unit, and a DRAM ferrite unit of a semiconductor substrate; Forming a trench oxide film in a first trench and a logic portion of the DRAM cell region and a second trench of the DRAM ferrite portion; Removing a portion of the trench oxide film embedded in the first trench; Forming an oxide film on a surface of the semiconductor substrate including a side surface of the first trench from which a portion of the trench oxide film is removed; And forming a polysilicon layer on the oxide film and then selectively patterning the polysilicon layer to form a capacitor plate electrode and a gate electrode of the DRAM cell region.
또한, 본 발명은 디램셀영역의 제1트렌치는 로직부 및 디램 페리부의 제2 트렌치에 비해 깊게 형성되어 있으며, 제1트렌치의 측면부에 형성된 산화막 부분은 캐패시터 의 유전체로 사용한다.Further, in the present invention, the first trench of the DRAM cell region is formed deeper than the second trench of the logic portion and the DRAM ferry portion, and the oxide film portion formed on the side portion of the first trench is used as the dielectric of the capacitor.
그리고, 본 발명은, 산화막의 일부가 제거된 제1트렌치측면에 캐패시터의 문턱전압 조절용 이온주입을 진행한다.In the present invention, ion implantation for adjusting the threshold voltage of the capacitor is performed on the side of the first trench in which a part of the oxide film is removed.
더욱이, 본 발명은, 상기 이온주입은 틸트를 주어 평판의 도핑농도와 동일 하게 진행하는 것을 특징으로한다.Furthermore, the present invention is characterized in that the ion implantation proceeds in the same manner as the doping concentration of the plate by giving a tilt.
(실시예)(Example)
이하, 본 발명에 따른 반도체소자의 캐패시터 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 따른 반도체소자의 캐패시터의 제조방법에 있어서, 캐패시터의 문턱전압 조절용 마스크 및 트렌치산화막의 레이아웃도이다.1 is a layout diagram of a mask and a trench oxide film for adjusting the threshold voltage of a capacitor in a method of manufacturing a capacitor of a semiconductor device according to the present invention.
도 2 내지 도 5는 본 발명에 따른 반도체소자의 캐패시터 제조방법을 설명하기 위한 캐패시터 제조 공정 단면도이다.2 to 5 are cross-sectional views of a capacitor manufacturing process for explaining a capacitor manufacturing method of a semiconductor device according to the present invention.
도 6은 본 발명에 따른 반도체소자의 캐패시터 제조공정을 통해 얻어진 반도체소자의 캐패시터의 레이아웃도이다.6 is a layout view of a capacitor of a semiconductor device obtained through a capacitor manufacturing process of the semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 캐패시터 제조방법은, 도 1 및 2에 도시된 바와같이, 먼저 반도체기판(11)상에 얕은트렌치분리공정(STI)에 의해 제1 및 2 트렌치(13a)(13b)을 형성한다. 이때, 얕은 트렌치분리공정(STI; shallow trench isolation)진행시에 디램 셀부(A)의 제2트렌치(13a) 깊이는 로직부 또는 디램 페리부(B)의 제2트렌치(13b)의 깊이보다 깊게 형성한다.In the method of manufacturing a capacitor of a semiconductor device according to the present invention, as shown in FIGS. 1 and 2, first and second trenches 13a and 13b are first formed by a shallow trench isolation process (STI) on a semiconductor substrate 11. To form. At this time, the depth of the second trench 13a of the DRAM cell portion A may be greater than the depth of the second trench 13b of the logic portion or the DRAM ferry portion B during the shallow trench isolation process (STI). Form.
그다음, 셀과 셀을 절연시키기 위해 트렌치된 부분에 산화막을 채운후 이를 전면식각에 의해 선택적으로 제거하여 디램셀영역의 트렌치산화막(15a)(15b)를 각각 형성한다.Then, an oxide film is filled in the trench to insulate the cell and then selectively removed by etching the entire surface to form trench oxide films 15a and 15b of the DRAM cell region, respectively.
이어서, 도 3에 도시된 바와같이, 캐패시터 문턱전압용 마스크(17)를 사용하여 디램셀영역의 트렌치산화막(15a)의 일부두께를 제거한후 캐패시터의 스토리지노드지역에 임플란트 공정을 진행한다. 이때, 상기 산화막의 식각량은 캐패시터와 캐패시터간 전류 누설이 발생하지 않는 범위인 트렌치 깊이의 약 70% 정도가 된다.Subsequently, as shown in FIG. 3, the thickness of the trench oxide layer 15a in the DRAM cell region is removed using the mask 17 for capacitor threshold voltage, and then an implant process is performed in the storage node region of the capacitor. At this time, the etching amount of the oxide layer is about 70% of the trench depth, which is a range in which current leakage between the capacitor and the capacitor does not occur.
또한, 이온주입은 캐패시터 지역의 문턱전압을 낮추기 위해 웰(미도시)과 반대타입의 도우즈를 주입하고, 트렌치 측면을 평판과 동일한 조건으로 도핑하기 위해 틸트를 주어 주입하게 된다.In addition, ion implantation injects wells (not shown) and the opposite type of dose to lower the threshold voltage of the capacitor region, and injects by tilting the trench to dope the trench side with the same conditions as the plate.
그다음, 도 4에 도시된 바와같이, 문턱전압 조절용 마스크(17)를 제거한후 산화막의 일부가 제거된 활성영역의 측면, 즉 트렌치(13a)의 측면을 포함한 반도체기판(11)의 표면상에 게이트산화막(21)을 성장시킨후 이어 폴리실리콘층(23)을 증착한다. 이때, 캐패시터의 면적으로는 활성영역과 트렌치(13a)의 측면부를 포함하므로 약 35 내지 45% 정도의 캐패시터 용량의 증가를 가져올 수 있게 된다.Then, as shown in FIG. 4, the gate on the surface of the semiconductor substrate 11 including the side of the active region, that is, the side of the trench 13a, in which the portion of the oxide film is removed after the threshold voltage adjusting mask 17 is removed. After the oxide film 21 is grown, the polysilicon layer 23 is deposited. At this time, since the area of the capacitor includes the active region and the side portions of the trench 13a, an increase in the capacitor capacity of about 35 to 45% can be obtained.
이어서, 도면에는 도시하지 않았지만, 상기 폴리실리콘층(23)상에 게이트 및 캐패시터 플레이트 형성용 마스크(미도시)를 형성한후 이 마스크를 이용하여 상기 폴리실리콘층(23)과 게이트산화막(21)을 선택적으로 제거하여 캐패시터의 플레이트전극(23a)과 게이트(23b)을 형성하므로써 동일한 크기에서 캐패시터 용량이 증가되는 입체적인 구조의 플라나 셀을 완성하게 된다.Subsequently, although not shown in the drawing, a mask for forming a gate and capacitor plate (not shown) is formed on the polysilicon layer 23, and then the polysilicon layer 23 and the gate oxide film 21 are formed using the mask. By selectively removing and forming the plate electrode 23a and the gate 23b of the capacitor, a planar cell having a three-dimensional structure in which the capacitor capacity is increased at the same size is completed.
이와 같이 공정순에 의해 제조된 플라나셀을 구성하는 활성영역(25)과 비트라인콘택(27) 및 캐패시터의 플레이트전극(23a)이 도 6에 도시되어 있다.As shown in FIG. 6, the active region 25, the bit line contact 27, and the plate electrode 23a of the capacitor constituting the planar cell manufactured according to the process sequence are shown in FIG. 6.
상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 캐패시터 제조방법에 의하면, 디램 셀영역의 트렌치깊이를 로직 및 페리부의 트렌치 깊이보다 깊게 한후 STI 산화막을 일정량 제거하고 그때 발생된 활성영역의 측면을 캐패시터 면적으로 사용한다.As described above, according to the method of fabricating a capacitor of a semiconductor device according to the present invention, after the trench depth of the DRAM cell region is deeper than the trench depth of the logic and periphery portions, a certain amount of the STI oxide film is removed and the side surface of the active region generated at that time is removed from the capacitor. Use as area.
또한, 웰을 스토리지 노드로 사용하므로써 트렌치 측면의 도핑조건을 평판의 조건과 동일하게 가져 가야 하는데 캐패시터 문턱전압용 이온주입을 틸트를 주어 주입하는 방법을 사용하므로써 해결하였다.In addition, by using the well as a storage node, the doping conditions on the trench side should be the same as that of the flat plate, but the solution was solved by using a method of injecting the ion implantation for the capacitor threshold voltage by giving a tilt.
단위면적이 동일한 셀에서 캐패시턴스를 약 35 내지 45 % 정도 늘려 디램의 센싱마진을 증가시키고 단위 셀 크기를 줄여 집적률을 ??이는 방법인 동시에 트렌치 깊이를 깊게 하므로써 셀간 누설전류를 최소화할 수 있다.In the same unit area, the capacitance is increased by about 35 to 45% to increase the sensing margin of the DRAM and reduce the unit cell size to reduce the integration rate, while deepening the trench depth, thereby minimizing the inter-cell leakage current.
즉, 평면상의 면적은 늘리지 않고 캐패시터 용량을 증가시킬 수 있고, 플라나셀의 센싱 마진을 늘여 소자의 특성을 좋게 하고, 단위 셀 크기를 줄임으로써 집적도를 높이는 효과를 가져 온다.That is, the capacitance of the capacitor can be increased without increasing the area of the plane, and the sensing margin of the plane cell is increased to improve the characteristics of the device and reduce the unit cell size, thereby increasing the degree of integration.
또한, 기존의 캐패시터의 문턱전압조절용 마스크를 사용하므로써 포토공정이 추가로 필요하지 않아 공정이 매우 단순하다.In addition, by using a mask for adjusting the threshold voltage of the existing capacitor, the photo process is not required additionally, so the process is very simple.
그리고, 단위 셀 크기가 작을수록 얕은 트렌치 측면의 캐패시터의 면적부분이 커지게 되므로 기술이 고집적될수록 쉬링크 능력(shrink ability)이 좋아져서 집적률을 높일 수 있는 이점이 있다.In addition, the smaller the unit cell size, the larger the area portion of the capacitor in the shallow trench side, the higher the technology, the better the shrink ability (shrink ability) has the advantage of increasing the integration rate.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR910007111A (en) * | 1989-09-26 | 1991-04-30 | 야마지 게이조오 | Formation method of deposited film and manufacturing method of semiconductor device |
| JPH056967A (en) * | 1991-02-13 | 1993-01-14 | Sony Corp | Gate array |
| KR0175007B1 (en) * | 1995-06-30 | 1999-02-01 | 김광호 | Semiconductor device and its fabrication method having voltage up capacitor |
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| KR910007111A (en) * | 1989-09-26 | 1991-04-30 | 야마지 게이조오 | Formation method of deposited film and manufacturing method of semiconductor device |
| JPH056967A (en) * | 1991-02-13 | 1993-01-14 | Sony Corp | Gate array |
| KR0175007B1 (en) * | 1995-06-30 | 1999-02-01 | 김광호 | Semiconductor device and its fabrication method having voltage up capacitor |
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