JPH06342887A - MIST dynamic random access memory cell and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Structure] A stack-trench mixed type dynamic random access memory cell and a method of manufacturing the same, wherein a stack capacitor having a relatively shallow trench depth is provided while making the trench depth of the trench capacitor different. The area of the storage electrode portion is formed larger than the area of the storage electrode portion of the stack capacitor in which the depth of the trench is relatively deep. In particular, a memory cell having a deep trench and a memory cell having a shallow trench are formed in one active region. The present invention provides a memory cell that overcomes the punch-through phenomenon of a trench type memory cell and has a capacitance necessary for data storage of an ultra-scale integrated circuit (ULSI) in which a coupling phenomenon in a stack type capacitor does not occur.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a dynamic random access memory cell (Dynamic Random).
(Access Memory, hereafter referred to as DRAM)
, And a method of manufacturing the same, in particular, a stack trench mixed type (MIST: Mixed Stacked)
TECHNICAL FIELD The present invention relates to a method for manufacturing a memory cell of a large-capacity DRAM having a Trench type) capacitor.

[0002]

2. Description of the Related Art In the technical field of semiconductor memory, efforts are being made to increase the number of memory cells on one chip. In order to achieve such an object, it is important to minimize the area of a memory cell array in which a large number of memory cells are formed on the surface of a limited chip. Therefore, it is a well-known fact that it is preferable to form one transistor and one capacitor memory cell in terms of the minimum area. However, in one transistor and one capacitor cell, the capacitor occupies most of the area. It is important to increase the capacitance of the capacitor while facilitating information detection in stored data and reducing soft errors due to α-particles, while minimizing the area occupied by the capacitor.

As described above, in order to maximize the capacity of the storage capacitor while minimizing the surface area occupied by the capacitor, a technique has been developed for forming the capacitor on the wall surface of the trench in which the cylindrical groove is formed on the surface of the chip. It was As a conventional memory cell structure having such a trench type capacitor, [IEDM (Internationala
l Electron Devices Meetin
g) Tech. Dig. , Pp. 710-713, 19
85]. This technique uses a wafer in which a p epitaxial layer is grown on a high-concentration p ⁺ substrate, and digs a cylindrical groove with the high-concentration p ⁺ layer,
An insulating film is formed on the wall surface of the groove, filled with n ⁺ polysilicon, and connected to the source region of the pass transistor.

However, in the structure of the trench capacitor as described above, since the thickness of the epitaxial layer is several μm, the depth of the trench must be increased in order to obtain the capacitance value suitable for the operation of the DRAM. ,
A thin oxide film (insulating film) is formed on the wall surface of the trench, and the insulating film is broken by the voltage applied to the polysilicon serving as the electrode of the capacitor filled in the trench due to the sharp corner of the bottom of the trench. The problem will occur. Further, by applying the polysilicon voltage,
Information is stored in the capacitor by forming a strong inversion layer at the interface between the P-type epitaxial layer and the wall surface of the trench. A punch-through phenomenon may occur between the capacitor and the capacitor, stored charges may be lost, and a leakage current may occur. In particular, such a phenomenon remarkably occurs when the storage current is used as the semiconductor substrate and the plate electrode is formed in the insulating layer.

As another technique for maximizing the capacity of a storage capacitor in a memory cell having a fixed area, a stacked capacitor (Stacked Ca) is used.
technology regarding a DRAM cell in which a transistor (STC) is selected, and a spread stacked capacitor (Spread Stacked Ca) in which the disadvantages of this technology are improved.
The technology relating to the DRAM cell in which the (PSC: SSC) is selected is described in [IEDM Tech. Dig. , S. INO
UE. , Pp. 31-34, 1989] and the like.

The above conventional technique will be described in more detail with reference to FIGS. 12 and 13.

FIG. 12 is a sectional perspective view of a DRAM cell provided with a stack type capacitor, in which SiO ₂ is removed so that the memory structure can be easily understood. Here, 21 is a storage electrode, 22 is a word line,
Reference numeral 23 is a field oxide film.

However, since the storage electrode 21 of the DRAM cell uses only one memory cell region of itself, it has a sufficient storage capacitance within the limited cell region of a memory device having a storage capacity of 16 Mbits or more. There is a disadvantage that Cs cannot be obtained.

On the other hand, FIG. 13 shows a structure in which each storage electrode 31, 32, 33 occupies two memory cell regions in order to increase the storage capacitance Cs of the STC type memory cell shown in FIG. In FIG. 13, 31 is a storage electrode of the first memory cell, 32 is a storage electrode of the second memory cell, 33 is a storage electrode of the third memory cell, 34 is a bit line, 35 is a common drain region, and 36 and 37 are gates. Word lines that are electrodes, 3
Reference numerals 8 and 39 are source electrodes, and 40 is a field oxide film.

In this SSC type memory cell, two memory cells, that is, a first memory cell and a second memory cell are formed between the field oxide film 40 and the field oxide film 40. The spread stacked storage electrode 31 of one memory cell is located between the bit line 34 and the storage electrode 32 of the second memory cell at the top and bottom, and the second storage electrode 32 at the left and right.
And the third storage electrode 33 are formed over the length corresponding to the two memory cell regions. Therefore, the storage capacitance Cs is greatly increased because it is proportional to the area.

However, since the distances between the first storage electrode 31, the second storage electrode 32, and the third storage electrode 33 are too close to each other, coupling is severely generated between the electrodes, and the stacked layers above and below are stacked. The structure may be disturbed.

Therefore, the present invention basically aims to solve the problems of the punch-through phenomenon and the coupling phenomenon, which occur in the conventional memory cell having the trench structure and the memory cell having the stacked structure, respectively. And

[0013]

In order to solve the above problems, the present invention provides a DRAM cell having a stacked trench type capacitor having a sufficient storage capacitance applicable to an ultra large scale integrated circuit (ULSI). And a method for manufacturing the same.

The present inventor has found the following matters. That is, in order to reduce the above-mentioned coupling between the storage electrodes in the stacked structure, first, the intersections (overlaps) between the electrodes must be reduced as much as possible. Also, in order to increase the vertical distance or the adjacent distance between the storage electrodes of the stack capacitor and reduce the intersection between the storage electrodes, the total capacitance must be increased by using a trench structure. Further, when the trench structure is also used, the depths of the trenches are set to be different in the present invention in order to reduce the leakage current due to the punch-through phenomenon between the trenches.

That is, according to the present invention, in a dynamic random access memory cell including one transistor and one capacitor, the capacitor is a trench capacitor having a trench structure, and the trench capacitor is vertically connected to the trench forming portion. And a stack capacitor having a stack structure to be formed, wherein a trench depth of the trench capacitor is set to be different from a trench depth of a trench capacitor of an adjacent memory cell, and the trench depth is relatively shallow. The storage electrode area of the stack capacitor of the first memory cell including the memory cell is larger than the storage electrode area of the stack capacitor of the adjacent second memory cell including the trench capacitor having a relatively deep trench depth. To provide a random access memory cell.

Furthermore, the present invention comprises one transistor and one capacitor, wherein the capacitor is
In a method of manufacturing a stack trench mixed type dynamic random access memory cell having a structure in which a stack type capacitor and a trench type capacitor are combined,
Forming a first trench having a predetermined depth using a first mask when forming the trench type capacitor;
The method includes the step of forming a second trench relatively deeper than the depth of the first trench using a second mask, and the step of forming the stack type capacitor. The area of the first storage electrode forming the stack capacitor of the first memory cell including the first trench capacitor formed in the trench is defined as the area of the stack capacitor of the second memory cell including the second trench capacitor formed in the second trench. Provided is a method of manufacturing a stack trench mixed type dynamic random access memory cell which is formed to have a larger area than a second storage electrode to be formed.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

1 to 11 show a MIS according to this embodiment.
FIG. 6 is a cross-sectional view for explaining a manufacturing process of a DRAM cell including a T-type capacitor.

FIG. 1 shows the steps for defining the active and inactive regions, and p is performed by the usual method.
The field oxide film 2 is grown on the silicon substrate 1.

In FIG. 2, the gate insulating film 3 is formed by the thermal oxidation method.
Then, polysilicon is deposited to a thickness of 2000 angstroms and patterned so that two memory cells are arranged per active region to form two gate electrodes 4, and the remaining portions are etched away. It shows that it did.

FIG. 3 shows the source region 5 for the first memory cell,
Common drain region 6 and source region 7 for second memory cell
FIG. 3 shows a process for forming a source and a common drain region by implanting arsenic As ions at 40 keV at a dose rate of 5 ¹⁵ atoms / cm ² .

FIG. 4 shows a step of depositing the first insulating film 8 on the structure obtained in FIG. 3, which is a high temperature oxide film HT.
O (High Temperature Oxidat
ion), for example, SiO ₂ is formed to a thickness of 1000 angstroms.

FIG. 5 shows a process for forming the bit line 9, in which polysilicon is deposited to a thickness of 500 Å and patterned to form the bit line 9.

FIG. 6 shows a step of forming the second insulating film 10 on the structure obtained in FIG.
It is formed to a thickness of 00 angstrom.

FIG. 7 shows a step of forming the first trench 11 having a shallow depth. More specifically, a photoresist is applied to the surface of the second insulating film 10 to form a trench through the source region 5 of the left first memory cell of the two memory cells arranged in one active region. Exposure and development are performed using a first trench mask for the purpose. After that, reactive ion etching (Reacti
The second insulating film 10, the first insulating film 8 and the gate insulating film 3 are etched by the ve Ion Etching (RIE) method, but the insulating film surrounding the gate 4 needs to be etched so as not to be damaged. Subsequently, the source region 5 and the p-type silicon substrate 1 are etched using the same method to form the first trench 11, and the photoresist remaining on the surface of the substrate is removed.

FIG. 8 shows a step of forming the second trench 12 having a deep depth. The second trench 12 is formed so that the position where the trench is formed penetrates the source region 7 of the second memory cell on the right side. A method similar to the above-described step of FIG. 7 is used except that a mask is used and the etching time is adjusted so that the depth of the second trench 12 becomes relatively deeper than that of the first trench 11. To do.

The above-described trench forming step in FIGS. 7 and 8 can be made into one step by forming a stepped structure in advance in the portion where the trench is formed. For example, this is performed by making the thickness of the insulating film (10) relatively thick in advance in the portion where the shallow trench is to be formed.

FIG. 9 shows a step of forming the first electrode of the capacitor. An insulating film 13 of a silicon oxide layer is formed inside the trenches 11 and 12 formed by the step of FIG. A first electrode material is formed by depositing a polysilicon layer 14 that will be the first electrode of the capacitor by the CVD method and immersing it in POCl ₃ to diffuse phosphorus P or by ion implantation of P or As. .

FIG. 10 shows a process of forming a stack type storage electrode, in which a first trench having a shallow depth is formed.
In order to compensate for the lacking storage capacitance, the right side portion of the storage electrode 15 of the stack capacitor portion is provided with the gate electrode 3 of the second memory cell.
For the second memory cell which is formed to extend to the upper portion of the stack and has a sufficiently deep trench, by patterning the polysilicon layer 14 so that the left side portion of the storage electrode 16 of the stack capacitor portion is formed short. An opening 17 is formed to separate the storage electrodes 15 and 16.

Then, a dielectric material having a high dielectric constant [SiO ₂ or ONO (SiO ₂ , Si ₃ N _{4) is formed} on the first electrode layer.
And SiO ₂ )] film is formed. A polysilicon layer 19 serving as a second electrode is grown on the entire surface including the insulating layer 18 by a CVD method and is immersed in POCl ₃ to diffuse phosphorus P to form a second electrode material of the capacitor.

A DRAM including the stack trench mixed type capacitor according to the present embodiment is manufactured by the above process. FIG. 11 is a cross-sectional perspective view showing the DRAM completed by this embodiment with the insulating layer removed.

[0032]

As is apparent from the above, in the DRAM of the present invention, the depths of the trenches 11 and 12 between the adjacent memory cells are set to be different from each other to prevent the punch-through phenomenon between the adjacent trenches. The capacitance of the trench capacitor, which can be suppressed and has a small capacitance, can be compensated for as the capacitance of a stack type capacitor having a relatively large area, and in this case, without the stepping as in the conventional case ( Coupling does not occur between adjacent storage electrodes because sufficient capacitance is compensated (without overlapping each other).

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a manufacturing process of a DRAM cell including a MIST type capacitor according to an embodiment of the present invention.

FIG. 2 is a sectional view illustrating a process of manufacturing a DRAM cell including a MIST type capacitor according to an embodiment of the present invention.

FIG. 3 is a sectional view illustrating a process of manufacturing a DRAM cell including a MIST type capacitor according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a manufacturing process of a DRAM cell including a MIST type capacitor according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining a manufacturing process of a DRAM cell including a MIST type capacitor according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a process of manufacturing a DRAM cell including a MIST type capacitor according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a process of manufacturing a DRAM cell including a MIST type capacitor according to an embodiment of the present invention.

FIG. 8 is a sectional view illustrating a process of manufacturing a DRAM cell including a MIST type capacitor according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view for explaining a manufacturing process of a DRAM cell including a MIST type capacitor according to an embodiment of the present invention.

FIG. 10 is a cross-sectional view for explaining a manufacturing process of a DRAM cell including a MIST type capacitor according to an embodiment of the present invention.

FIG. 11 is a MIST type DR manufactured according to the above embodiment.
Cross-sectional perspective view of memory structure showing AM cell with SiO ₂ removed

FIG. 12: DR equipped with a conventional stacked capacitor
Cross-sectional perspective view of the memory structure of the AM cell with SiO ₂ removed.

FIG. 13 is a cross-sectional perspective view of a memory structure in which SiO ₂ is removed from a DRAM cell including a conventional spread-stacked capacitor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... P-type silicon substrate 2 ... Field oxide film 3 ... Gate insulating film 4 ... Gate electrode 5, 7 ... Source region 6 ... Common drain region 8 ... 1st insulating film 9 ... Bit line 10 ... 2nd insulating film 11 ... DESCRIPTION OF SYMBOLS 1 trench 12 ... 2nd trench 13 ... insulating film 14, 19 ... polysilicon layer 15, 16 ... storage electrode part 17 ... contact opening 18 ... insulating layer

Claims (5)

[Claims] 1. A dynamic random access memory cell (DR) including one transistor and one capacitor.
AM), the capacitor is composed of a trench capacitor having a trench structure and a stack capacitor having a stack structure that is vertically formed on the transistor formation portion following the trench capacitor, and the trench depth of the trench capacitor is The area of the storage electrode of the stack capacitor of the first memory cell including the trench capacitor, which is set to be different from the trench depth of the trench capacitor of the adjacent memory cell and has a relatively shallow trench depth, is determined by the depth of the trench. Dynamic random access memory cell, wherein the area is larger than the storage electrode area of the stack capacitor of the adjacent second memory cell including the deep trench capacitor. 2. A first memory cell including a capacitor having a shallow trench and a large storage electrode formation area of a stack structure, and a capacitor having a deep trench and a narrow storage electrode formation area of a stack structure. The dynamic random access memory cell according to claim 1, wherein the second memory cell including the second random access memory cell is formed in one active region. 3. A method of manufacturing a stacked trench mixed type dynamic random access memory cell, comprising: one transistor and one capacitor, wherein the capacitor has a structure in which a stack capacitor and a trench capacitor are combined. When forming a capacitor, a step of forming a first trench with a predetermined depth using a first mask, and a step of forming a second trench relatively deeper than the depth of the first trench using a second mask And a step of forming a stack capacitor, wherein in the step of forming the stack capacitor, the first
The area of the first storage electrode forming the stack capacitor of the first memory cell including the first trench capacitor formed in the trench is defined as the area of the stack capacitor of the second memory cell including the second trench capacitor formed in the second trench. A method of manufacturing a stack trench mixed dynamic random access memory cell, which is characterized in that the area is larger than the area of the second storage electrode to be formed. 4. The method of manufacturing a dynamic random access memory cell according to claim 3, wherein the first memory cell and the second memory cell are formed in one active region. 5. The step of forming the first trench and the second trench is performed in a single etching step by forming a stepped structure in a region where the trench is formed in advance. Of manufacturing a dynamic random access memory cell of.