JPH0815207B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a semiconductor memory device, the present invention extends the memory capacitors of adjacent memory cells onto a plurality of word lines existing between the access transistors of each other. By arranging a part of the stacked memory capacitor so that it is partially stacked, it is possible to obtain about 1.5 to 2 times the capacity of the conventional stacked memory capacitor.

[Industrial applications]

The present invention relates to a semiconductor memory device whose structure is improved so that the capacity of a memory capacitor can be increased without impairing the integration.

[Conventional technology]

Generally, semiconductor memory devices of the type described above, i.e., dynamic random access memory (dynamic random access memory).
High integration of access memory (DRAM) is being sought after equally.

Also, as is well known, a DRAM comprises an array of memory cells consisting of one access transistor and one memory capacitor.

Therefore, as described above, when high integration of DRAM is intended,
The area of the memory cell must be reduced, and naturally, the area of the memory capacitor is also reduced, so that its capacity is also reduced.

However, the capacity of the memory capacitor is closely related to the reliability of the operation of the DRAM, that is, the quality of the S / N, and it is preferable that the capacity of the memory capacitor is large in terms of radiation countermeasures.

Therefore, various researches and developments have been conventionally performed to increase the capacity of the memory capacitor.

FIG. 6 is for explaining the stacked memory capacitor used in the conventional IM bit DRAM.
A cutaway side view of a main part of the DRAM, (B) shows an equivalent main circuit diagram.

In the figure, 1 is a silicon semiconductor substrate, 2 is a field insulating film, 3A and 3B are impurity diffusion regions for bit line contacts, 4A and 4B are impurity diffusion regions for memory / capacitor electrode contacts, and WL0, WL1, WL2, WL3. Is a word line formed of the first conductive layer (polycrystalline silicon containing impurities),
Reference numeral 5 is an insulating film, 6A and 6B are individual electrodes of the memory capacitor formed of the second conductive layer (polycrystalline silicon containing impurities), 7A and 7B are insulating films which serve as a dielectric in the memory capacitor, 8 is a common counter electrode (cell plate) of the memory capacitor formed of the third conductive layer (polycrystalline silicon containing impurities), 9 is phosphosil glass (phosphosil)
icate glass: PSG) insulation film, BL and ▲ ▼
Each bit line is made of Al.

The insulating films 7A and 7B, which are the dielectrics in the DRAM memory capacitor shown here, are individual electrodes of polycrystalline silicon that extend to the access transistor and form a curved surface.
Since it is formed up to 6A and 6B and the side walls thereof,
A very large capacitance can be obtained, which is called a three-dimensional stacked memory capacitor, and can be applied to a folded bit line configuration.

[Problems to be solved by the invention]

The DRAM memory capacitor described with reference to FIG. 6 is compared with a memory capacitor in a conventional planar memory cell, that is, an insulating film serving as a dielectric is formed on a silicon semiconductor substrate. Needless to say, it is a very excellent capacitor because it can obtain a much larger capacity than an ordinary stacked memory capacitor to which an open bit line configuration cannot be applied. Considering a 4M-bit DRAM or the like that must be provided, the area that can be allocated per memory cell is significantly reduced, and it is considered that the capacity is still insufficient even if the structure of the memory capacitor described above is applied.

The present invention provides a semiconductor memory device which has a large capacity by making a simple improvement to the memory capacitor in the DRAM described with reference to FIG. 6 and which can cope with higher integration and higher midpoint density. To do.

[Means for solving problems]

In the semiconductor memory device according to the present invention, two adjacent memory cells each including one access transistor and one memory capacitor are paired, and the respective memory capacitors are connected to each other. It has a structure in which it is extended to above the transistor and the two are laminated in a double layer.

[Action]

By adopting the above means, the area of the memory capacitor, and therefore the capacitance, is at least 1.5 times as large as that of the conventional stacked memory capacitor. Therefore, the semiconductor memory device can be further highly integrated to reduce the size of the memory cell. Even if it is set, a sufficient capacity for accumulating necessary information can be obtained, and if not downsized, the S / N becomes good and the resistance to soft error becomes high.

〔Example〕

1 to 5 are sectional side views of a main part of a semiconductor memory device in process steps for explaining a case of manufacturing an embodiment of the present invention. Hereinafter, with reference to these drawings, FIG. explain. The same symbols as those used in FIG. 6 represent the same parts or have the same meanings.

See FIG. 1 (1) By applying a normal technique, a field insulating film 2 and a gate insulating film 2G are formed on a silicon semiconductor substrate 1, and a first conductive layer made of impurity-containing polycrystalline silicon is formed thereon. A layer is formed and the first conductive layer is patterned to form word lines WL0, WL1, WL2, WL3.

(2) By applying the self-alignment type ion implantation method using each of the word lines as a mask,
As ions are implanted to form the source and drain regions of the access transistor, that is, the impurity diffusion regions 3A and 3B for bit line contacts, the impurity diffusion regions 4A and 4B for memory capacitor electrode contacts, and the like.

(3) chemical vapor deposition
The thickness of SiO _{2 is} about 2 by applying the n: CVD method.
An insulating film 5 having a thickness of about 000 [Å] is formed, and is patterned by applying a normal photolithography technique to form an electrode contact window 5A for the impurity diffusion region 4A for the memory capacitor electrode contact.

See Fig. 2 (4) By applying the CVD method, a second conductive layer of polycrystalline silicon containing impurities with a thickness of about 2000 [Å] is formed, and ordinary photolithography technology is applied to this. Patterning by applying one of the memory
The individual electrode 6A of the capacitor is formed. As is apparent from the figure, the individual electrodes 6A are extended to a plurality of word lines existing between adjacent access transistors.

(5) By applying the thermal oxidation method, the insulating film 7A having a thickness of about 100 [Å] is formed on the surface including the side surface of the individual electrode 6A. It goes without saying that the insulating film 7A serves as the dielectric of one of the memory capacitors.

See Fig. 3 (6) By applying the CVD method, a third conductive layer with a thickness of about 2000 [Å] made of impurity-containing polycrystalline silicon is formed, and the ordinary photolithography technique is applied to this. Is applied to form the common counter electrode 8 of the memory capacitor. The common counter electrode 8 is generally known as a cell plate.

(7) By applying the thermal oxidation method, the insulating film 7 having a thickness of about 100 [Å] is formed on the surface including the side surface of the common counter electrode 8.
Form B. Needless to say, this insulating film 7B serves as the dielectric of the other memory capacitor.

See Fig. 4 (8) The insulating film 5 is etched by applying ordinary photolithography technology, and the electrode contact window 5B to the impurity diffusion region 4B for the memory capacitor electrode contact and the impurity for the bit line contact are formed. Electrode contact windows 5C and 5D for the diffusion regions 3A and 3B are formed.

(9) By applying the CVD method, form a fourth conductive layer of polycrystalline silicon containing impurities with a thickness of about 2000 [Å], and apply ordinary photolithography technology to it. Patterning the other memory
An aluminum punch-through prevention film is formed on the impurity diffusion regions 3A and 3B for bit line contacts while forming the individual electrode 6B of the capacitor.
Form 6C and 6D.

See FIG. 5 (10) The insulating film 9 made of PSG is formed by applying the CVD method, and etching is performed by applying ordinary photolithography technology to the insulating film 9, and the bit line contact window 9A and 9B is formed and a glass flow heat treatment is performed if necessary.

(11) An Al film is formed by applying a vapor deposition method,
Patterning is performed by applying a normal photolithography technique to this, and the bit line BL (and ▲ ▼) is formed.

As is apparent from the figure, in the semiconductor memory device manufactured in this manner, the memory capacitors in the adjacent memory cells are overlaid on the access transistors of the respective counterparts and doubly stacked. Due to this structure, the area is approximately doubled, and at least 1.5 times larger, so the capacity is increased in proportion to it. still,
As described above, even if the memory capacitors are double-layered, there is no adverse effect on the operation.

〔The invention's effect〕

In the semiconductor memory device according to the present invention, two adjacent memory cells each including one access transistor and one memory capacitor are paired, and each individual electrode in the memory capacitor is a memory cell. The cell extends over the word line of the cell itself and a plurality of adjacent word lines, and the individual electrodes thereof have a portion in which adjacent ones overlap each other.

By adopting such a configuration, the area of the memory capacitor in one memory cell is about twice, or at least 1.5 times, as compared with the conventional stacked memory capacitor, so that the capacity is also increased. Of course, since the semiconductor memory device is increased to the same degree, and the semiconductor memory device is further highly integrated, even if the area of the memory cell is reduced, the same capacity as the conventional one or more can be obtained, which is sufficient. Information can be stored, and if not miniaturized, S / N is improved and resistance to soft error is increased.

[Brief description of drawings]

1 to 5 are sectional side views of essential parts of a semiconductor memory device in process steps for explaining a case of manufacturing an embodiment of the present invention, and FIG. 6 is a view for explaining a conventional example. so,
(A) shows a cutaway side view of a main part, and (B) shows an equivalent circuit diagram of the main part. In the figure, 1 is a silicon semiconductor substrate, 2 is a field insulating film, 2G is a gate insulating film, 3A and 3B are impurity diffusion regions for bit line contacts, 4A and 4B are impurity diffusion regions for memory / capacitor electrode contacts, and WL0. , WL1, WL2, WL3 are word lines formed of the first conductive layer (polycrystalline silicon containing impurities), 5 is an insulating film, 5A, 5B, 5C, 5D are electrode contact windows, and 6A and 6B are first Individual electrodes of the memory capacitor formed of the second conductive layer (polycrystalline silicon containing impurities), 6C and 6D are Al punch-through prevention films, and 7A and 7B are memory
An insulating film serving as a dielectric in the capacitor, 8 is a common counter electrode (cell plate) of the memory capacitor formed of the third conductive layer (polycrystalline silicon containing impurities), 9
Is an insulating film made of PSG, 9A and 9B are bit line contact windows, and BL and ▲ ▼ are bit lines made of Al, respectively.

Claims (1)

[Claims] 1. Adjacent two memory cells consisting of one access transistor and one memory capacitor.
In the memory capacitor, individual electrodes extend to a word line of the memory cell itself and a plurality of adjacent word lines, and the individual electrodes have portions where adjacent ones overlap each other. A characteristic semiconductor memory device.