KR100448242B1 - Method for fabricating capacitor top electrode in semiconductor device - Google Patents
Method for fabricating capacitor top electrode in semiconductor device Download PDFInfo
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- KR100448242B1 KR100448242B1 KR10-2002-0023021A KR20020023021A KR100448242B1 KR 100448242 B1 KR100448242 B1 KR 100448242B1 KR 20020023021 A KR20020023021 A KR 20020023021A KR 100448242 B1 KR100448242 B1 KR 100448242B1
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- nitride film
- titanium nitride
- oxygen
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- 239000003990 capacitor Substances 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 38
- 239000012298 atmosphere Substances 0.000 claims abstract description 36
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 35
- 239000001301 oxygen Substances 0.000 claims abstract description 35
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 35
- 238000010438 heat treatment Methods 0.000 claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 7
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 2
- 239000002243 precursor Substances 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 238000005429 filling process Methods 0.000 abstract description 3
- 229910052715 tantalum Inorganic materials 0.000 description 9
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 3
- 229910003071 TaON Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229910052741 iridium Inorganic materials 0.000 description 3
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910052746 lanthanum Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010406 interfacial reaction Methods 0.000 description 1
- 229910000457 iridium oxide Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
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- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체 소자의 캐패시터 제조시 산소충진공정이 포함된 상부전극 형성방법을 적용하여 특성을 향상시킨 캐패시터 제조방법에 관한 것으로, 이를 위한 본 발명은 기판상에 하부전극과 유전체를 차례로 형성하는 단계; 상기 유전체 상에 50 ∼ 100Å의 두께를 갖는 제1 티타늄질화막을 형성하는 단계; 상기 제1 티타늄질화막에 산소를 충진시키되, 산소를 충진시키는 공정은 오존분위기(O3), 산소분위기, 산소플라즈마 분위기, N2O 분위기, N2O 플라즈마 분위기, N2+O2분위기, N2+O2플라즈마 분위기 또는 전술한 여러 분위기를 혼합한 분위기에서 5초 ∼ 1분 동안 급속열처리 하는 단계; 및 상기 제1 티타늄질화막 상에 도전층을 형성하는 단계를 포함하여 이루어진다.The present invention relates to a method for manufacturing a capacitor having improved characteristics by applying an upper electrode forming method including an oxygen filling process when manufacturing a capacitor of a semiconductor device. The present invention provides a step of sequentially forming a lower electrode and a dielectric on a substrate. ; Forming a first titanium nitride film having a thickness of 50 to 100 Å on the dielectric; Filling the first titanium nitride film with oxygen, but the step of filling the oxygen is ozone atmosphere (O 3 ), oxygen atmosphere, oxygen plasma atmosphere, N 2 O atmosphere, N 2 O plasma atmosphere, N 2 + O 2 atmosphere, N Rapid heat treatment for 5 seconds to 1 minute in a 2 + O 2 plasma atmosphere or an atmosphere mixed with the above-described various atmospheres; And forming a conductive layer on the first titanium nitride film.
Description
본 발명은 반도체 소자의 캐패시터 상부전극 형성시에, 상부전극을 2단계로 형성하고 산소충진 공정을 도입하여 캐패시터의 특성을 향상시킨 것이다.The present invention improves the characteristics of a capacitor by forming an upper electrode in two stages and introducing an oxygen filling process when forming a capacitor upper electrode of a semiconductor device.
현재, 반도체 메모리 소자는 크게 RAM(Random Access Memory)과 ROM(Read only Memory)로 구분할 수가 있다. 특히, RAM은 다시 다이나믹램(Dynamic RAM, 이하 DRAM이라 칭함)과 스태틱램(Static RAM)으로 나눠지며, 이 중에서도 DRAM은 1개의 트랜지스터(transistor)와 1개의 캐패시터로 1개의 단위셀(unit cell)이 구성되어 집적도에서 가장 유리하기 때문에 메모리 시장을 주도하고 있다.Currently, semiconductor memory devices can be largely classified into random access memory (RAM) and read only memory (ROM). In particular, the RAM is divided into a dynamic RAM (hereinafter referred to as DRAM) and a static RAM, among which a DRAM is a unit cell with one transistor and one capacitor. This configuration is leading the memory market because it is most advantageous in density.
반도체 소자에서 사용되는 캐패시터는 하부전극, 유전체 및 상부전극이 적층되어 구성되는데, 이와 같은 캐패시터 제조공정을 도1을 참조하여 설명한다.The capacitor used in the semiconductor device is formed by stacking a lower electrode, a dielectric, and an upper electrode, and the capacitor manufacturing process will be described with reference to FIG. 1.
도1은 종래의 캐패시터 제조공정을 도시한 순서도로서 먼저, 소정공정이 완료된 반도체 기판상에 캐패시터의 하부전극을 형성하는 단계가 도시되어 있다. 캐패시터의 하부전극으로는 폴리실리콘이나 금속물질이 사용될 수 있으며, 또는 여러가지 물질이 적층된 구조가 캐패시터의 하부전극으로 적용되기도 한다.1 is a flowchart illustrating a conventional capacitor manufacturing process. First, a step of forming a lower electrode of a capacitor on a semiconductor substrate on which a predetermined process is completed is illustrated. Polysilicon or a metal material may be used as the lower electrode of the capacitor, or a structure in which various materials are stacked may be used as the lower electrode of the capacitor.
다음으로, 하부전극 상에 캐패시터의 유전체를 형성하는 단계를 수행한다.초기에는 캐패시터의 유전체로 SiO2/Si3N4등의 실리콘 화합물을 이용하였는데, 메모리 셀의 집적도가 증가함에 따라, 좁은 면적에서도 충분한 캐패시턴스를 확보하기 위해서 고유전율을 갖는 새로운 유전물질을 사용하게 되었다.Next, a capacitor dielectric is formed on the lower electrode. In the beginning, a silicon compound such as SiO 2 / Si 3 N 4 was used as the dielectric of the capacitor. In order to secure sufficient capacitance, new dielectric materials with high dielectric constants have been used.
탄탈륨산화막(Ta2O5), Al2O3, SrTiO3, TaON 등의 고유전물질이나 (Bi,La)4Ti3O12(이하 BLT), SrBi2Ta2O9(이하 SBT), SrxBiy(TaiNbj)2O9(이하 SBTN), BaxSr(1-x)TiO3(이하, BST), Pb(Zr,Ti)O3(이하 PZT) 와 같은 강유전체는 종래의 ONO 유전물질에 비해 수배에서 수십배에 달하는 유전율을 가지고 있기 때문에 제한된 면적에서도 충분한 캐패시턴스를 확보할 수 있어, 이에 대한 연구가 활발히 이루어지고 있으며 탄탈륨 유전체(Ta2O5, TaON)의 경우는 공정에 적용되고 있다.High dielectric materials such as tantalum oxide (Ta 2 O 5 ), Al 2 O 3 , SrTiO 3 , TaON, (Bi, La) 4 Ti 3 O 12 (hereinafter BLT), SrBi 2 Ta 2 O 9 (hereinafter SBT), Ferroelectrics such as Sr x Bi y (Ta i Nb j ) 2 O 9 (hereinafter SBTN), Ba x Sr (1-x) TiO 3 (hereinafter BST) and Pb (Zr, Ti) O 3 (hereinafter PZT) Since the dielectric constant of several times to several tens of times compared to the conventional ONO dielectric material, sufficient capacitance can be secured even in a limited area, and research on this is being actively conducted. In the case of tantalum dielectrics (Ta 2 O 5 and TaON), Is being applied to.
탄탈륨 유전체을 캐패시터의 유전체로 사용할 경우에는, 800℃ 이상의 고온에서 탄탈륨 유전체를 증착한 뒤에, 탄탈륨 유전체를 결정화시키면서 탄탈륨 유전체에 산소를 공급하기 위한 열처리 단계가 수행된다.When the tantalum dielectric is used as the dielectric of the capacitor, after the tantalum dielectric is deposited at a high temperature of 800 ° C. or higher, a heat treatment step for supplying oxygen to the tantalum dielectric while crystallizing the tantalum dielectric is performed.
이와 같은 유전체 열처리 단계 이후에, 유전체상에 상부전극을 형성한다. 캐패시터의 상부전극으로는 폴리실리콘이나 티타늄질화막을 사용할 수도 있으며 또는 백금, 이리듐, 루테늄 등 귀금속물질을 상부전극으로 사용하기도 한다.After the dielectric heat treatment step, the upper electrode is formed on the dielectric. Polysilicon or titanium nitride may be used as the upper electrode of the capacitor, or a precious metal material such as platinum, iridium, or ruthenium may be used as the upper electrode.
상부전극으로 티타늄질화막과 폴리시리콘이 적층된 구조를 사용하는 경우에는, 티타늄질화막을 먼저 300Å 정도의 두께로 형성하고, 상기 티타늄질화막 상의 단차를 따라 도핑된 폴리실리콘을 1000 ∼ 3000 Å의 두께로 증착하여 상부전극 구조를 완성한다.When using a structure in which a titanium nitride film and polysilicon are stacked as an upper electrode, the titanium nitride film is first formed to a thickness of about 300 GPa, and the doped polysilicon is deposited to a thickness of 1000 to 3000 GPa along the step on the titanium nitride film. To complete the upper electrode structure.
종래에는 이와 같이 상부전극을 형성하는 단계 이후에, 도핑된 폴리실리콘 내의 도판트(dopant)들의 활성화, 유전체와 상부전극간의 계면특성향상, 유전체의 안정화 등을 위하여 700 ∼ 800℃의 온도, 질소분위기에서 30분 정도의 열처리 단계를 수행하였다.Conventionally, after forming the upper electrode, a temperature of 700 to 800 ° C. and a nitrogen atmosphere for activating dopants in the doped polysilicon, improving interface characteristics between the dielectric and the upper electrode, stabilizing the dielectric, and the like. A heat treatment step of about 30 minutes was performed.
하지만 이러한 열처리 단계는 유전체와 상부전극 물질인 티타늄질화막 간의 계면반응을 유발하여 저유전상수를 가지는 티타늄산화물을 형성하므로, 캐패시터의 충전용량을 감소시키며 또한, 유전체에 공급된 산소 중 일부를 티타늄질화막에 빼앗기게 됨에 따라, 유전체 내에는 금속성분이 많아지게 되어, 누설전류가 증가하는 등 캐패시터 특성이 열화되는 단점이 있었다.However, this heat treatment step induces an interfacial reaction between the dielectric material and the titanium nitride film, the upper electrode material, to form a titanium oxide having a low dielectric constant, thereby reducing the charging capacity of the capacitor and depriving the titanium nitride film of some oxygen supplied to the dielectric material. As a result, there are many metal components in the dielectric, which results in a deterioration of capacitor characteristics such as an increase in leakage current.
본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 캐패시터 상부전극과 유전체 사이의 계면에 저유전율을 갖는 산화막이 생성되는 것을 억제하여, 특성을 향상시킨 캐패시터 제조방법을 제공함을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to provide a method of manufacturing a capacitor having improved characteristics by suppressing generation of an oxide film having a low dielectric constant at an interface between a capacitor upper electrode and a dielectric.
도1은 종래기술에 따른 캐패시터 제조공정을 도시한 순서도,1 is a flow chart showing a capacitor manufacturing process according to the prior art,
도2a 내지 도2b는 본 발명의 일실시예에 따른 캐패시터 제조공정을 도시한 단면도,2a to 2b is a cross-sectional view showing a capacitor manufacturing process according to an embodiment of the present invention,
도3은 본 발명의 일실시예에 따른 캐패시터 제조공정을 도시한 순서도.Figure 3 is a flow chart showing a capacitor manufacturing process according to an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
20 : 기판20: substrate
21 : 제1 절연막21: first insulating film
22 : 플러그22: plug
23 : 제2 절연막23: second insulating film
24 : 하부전극24: lower electrode
25 : 유전체25: dielectric
26 : 제1 티타늄질화막26: first titanium nitride film
27 : 제2 티타늄질화막27: second titanium nitride film
28 : 도핑된 폴리실리콘28: doped polysilicon
상기한 목적을 달성하기 위한 본 발명은, 기판상에 하부전극과 유전체를 차례로 형성하는 단계; 상기 유전체 상에 50 ∼ 100Å의 두께를 갖는 제1 티타늄질화막을 형성하는 단계; 상기 제1 티타늄질화막에 산소를 충진시키되, 산소를 충진시키는 공정은 오존분위기(O3), 산소분위기, 산소플라즈마 분위기, N2O 분위기, N2O 플라즈마 분위기, N2+O2분위기, N2+O2플라즈마 분위기 또는 전술한 여러 분위기를 혼합한 분위기에서 5초 ∼ 1분 동안 급속열처리 하는 단계; 및 상기 제1 티타늄질화막 상에 도전층을 형성하는 단계를 포함하여 이루어진다.The present invention for achieving the above object, the step of sequentially forming a lower electrode and a dielectric on the substrate; Forming a first titanium nitride film having a thickness of 50 to 100 Å on the dielectric; Filling the first titanium nitride film with oxygen, but the step of filling the oxygen is ozone atmosphere (O 3 ), oxygen atmosphere, oxygen plasma atmosphere, N 2 O atmosphere, N 2 O plasma atmosphere, N 2 + O 2 atmosphere, N Rapid heat treatment for 5 seconds to 1 minute in a 2 + O 2 plasma atmosphere or an atmosphere mixed with the above-described various atmospheres; And forming a conductive layer on the first titanium nitride film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명한다.Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.
도2a 내지 도2b는 본 발명에 따른 캐패시터 제조공정을 도시한 단면도로서 이를 참조하여 설명하면, 먼저 트랜지스터, 비트라인, 워드라인 등의 소정공정이 완료된 반도체 기판(20) 상에 제1 절연막(21)을 형성한 후에, 제1 절연막(21)을 관통하여 상기 기판(20)에 콘택되는 플러그 (22)를 형성한다. 플러그 물질로는 폴리실리콘 또는 텅스텐 등이 사용될 수 있으며, 콘택플러그 구조에는 물질 상호간의 확산을 막는 확산방지막과 오믹접촉을 이루는 실리사이드층이 통상적으로 적용된다.2A and 2B are cross-sectional views illustrating a capacitor manufacturing process according to the present invention. First, the first insulating film 21 is formed on the semiconductor substrate 20 on which predetermined processes such as transistors, bit lines, and word lines are completed. ), A plug 22 penetrating the first insulating film 21 to contact the substrate 20 is formed. Polysilicon or tungsten may be used as the plug material, and a silicide layer that makes ohmic contact with a diffusion barrier that prevents diffusion between materials is typically applied to the contact plug structure.
다음으로 플러그(22)를 포함하는 제1 절연막(21) 상에 제2 절연막(23)을 형성하고, 상기 제2 절연막(23)을 선택적으로 식각하여 콘택플러그 부분을 노출시키는 트렌치 홀을 형성한다. 여기서 트렌치 홀을 캐패시터의 하부전극영역을 정의한다.Next, a second insulating film 23 is formed on the first insulating film 21 including the plug 22, and the trench is formed to selectively expose the contact plug portion by selectively etching the second insulating film 23. . Here, the trench hole defines the lower electrode region of the capacitor.
상기 제1 내지 제2 절연막은 모든 종류의 유리질 실리콘 산화막 (예를 들면 USG, PSG, TEOS, HTO, PE-TEOS, SOG 등)을 이용하여 형성할 수 있으며, 통상적인 화학기상증착법 (Chemical Vapor Deposition : CVD)또는 플라즈마 인핸스드 화학기상증착법 (Plasma Enhanced CVD)을 이용하여 형성한다.The first to second insulating films may be formed using all kinds of glassy silicon oxide films (eg, USG, PSG, TEOS, HTO, PE-TEOS, SOG, etc.), and a conventional chemical vapor deposition method. : Formed using CVD) or plasma enhanced CVD.
다음으로 트렌치 홀을 포함한 제2 절연막(23) 상에 하부전극을 적절한 두께로 증착하고, 제2 절연막(23)의 표면이 노출될 때까지 화학기계연마 (Chemical Mechanical Polishing : CMP)를 수행하여 고립된 하부전극(24)을 형성한다.Next, a lower electrode is deposited to an appropriate thickness on the second insulating film 23 including the trench holes, and chemical mechanical polishing (CMP) is performed until the surface of the second insulating film 23 is exposed. The lower electrode 24 is formed.
하부전극(24)으로는 폴리실리콘, 백금(Pt), 티타늄질화막(TiN), 루테늄(Ru), 루테늄산화막(RuO2), 이리듐(Ir), 이리듐산화막(IrO2) 등이 사용될 수 있으며 또는 이들을 적층하여 사용할 수도 있다.The lower electrode 24 may be polysilicon, platinum (Pt), titanium nitride (TiN), ruthenium (Ru), ruthenium oxide (RuO 2 ), iridium (Ir), iridium oxide (IrO 2 ), or the like. These can also be laminated | stacked and used.
하부전극(24)을 형성하고 난 뒤에, 하부전극을 포함한 제2 절연막(23) 상에 유전체(25)를 형성하는데, 유전체(25)로는 Ta2O5, TaON 등의 고유전체와 SiO2/Si3N4등의 통상적인 유전체 또는 (Bi,La)4Ti3O12(이하 BLT), SrBi2Ta2O9(이하 SBT), SrxBiy(TaiNbj)2O9(이하 SBTN), BaxSr(1-x)TiO3(이하, BST), Pb(Zr,Ti)O3(이하 PZT) 와 같은 강유전체가 사용될 수 있으며, 화학기상증착법 또는 원자층증착법 (Atomic Layer Deposition : ALD)을 이용하여 형성한다.To form the lower electrode dielectric 25 on the second insulating film 23 including the lower electrode 24 and the back I form the dielectric (25) includes Ta 2 O 5, TaON, such as the high-dielectric and SiO 2 / Conventional dielectric such as Si 3 N 4 or (Bi, La) 4 Ti 3 O 12 (hereinafter BLT), SrBi 2 Ta 2 O 9 (hereinafter SBT), Sr x Bi y (Ta i Nb j ) 2 O 9 ( Ferroelectrics such as SBTN), Ba x Sr (1-x) TiO 3 (hereinafter referred to as BST) and Pb (Zr, Ti) O 3 (hereinafter referred to as PZT) may be used, and chemical vapor deposition or atomic layer deposition (Atomic Layer) Deposition: ALD).
본 발명의 일실시예에서는 탄탈륨 유전체를 적용하였으며, 탄탈륨 유전체는 800℃ 이상의 고온에서 증착되며, 탄탈륨 유전체를 형성하고 난 후에, 탄탈륨 유전체의 결정화 및 산소공급을 위하여 800℃ 이상의 온도와 산소분위기에서 한번의 열처리 단계가 수행된다.In an embodiment of the present invention, a tantalum dielectric is applied, and the tantalum dielectric is deposited at a high temperature of 800 ° C. or higher, and after forming the tantalum dielectric, once in a temperature and oxygen atmosphere of 800 ° C. or higher for crystallization and oxygen supply of the tantalum dielectric. The heat treatment step of is performed.
이와 같은 유전체 열처리 단계 이후에 상부전극을 형성하는데, 본 발명의 일실시예에 따른 산소를 충진시키는 공정이 포함된 상부전극 형성방법에 대해 도2b를 참조하여 설명한다.After forming the upper electrode after the dielectric heat treatment step, the method of forming the upper electrode including the step of filling the oxygen according to an embodiment of the present invention will be described with reference to Figure 2b.
본 발명의 일실시예에서는 상부전극으로 티타늄질화막과 도핑된 폴리실리콘이 적층된 구조를 사용하는데, 티타늄질화막은 TiCl4선구물질과 NH3가스를 이용하여 화학기상증착법 또는 원자층증착법을 이용하여 형성된다.In an embodiment of the present invention, a titanium nitride layer and a doped polysilicon layer are stacked as an upper electrode. The titanium nitride layer is formed using a chemical vapor deposition method or an atomic layer deposition method using a TiCl 4 precursor and NH 3 gas. do.
본 발명의 일실시예에서는, 티타늄질화막 형성은 2단계로 진행되는데 먼저, 50 ∼ 100Å 정도의 매우 얇은 두께를 갖는 제1 티타늄질화막(26)을 증착한 후, 산소분위기에서 짧은 시간동안 열처리를 수행하여 제1 티타늄질화막(26)에 산소를 충진시킨다.In an embodiment of the present invention, the titanium nitride film is formed in two steps. First, after depositing the first titanium nitride film 26 having a very thin thickness of about 50 to about 100 μs, the heat treatment is performed in an oxygen atmosphere for a short time. To fill the first titanium nitride film 26 with oxygen.
본 발명의 일실시예에 따른 제1 티타늄질화막은 얇은 두께를 갖고 있기 때문에 산소충진이 용이하다. 하지만, 산소충진 공정이 수행되는 동안에 제1 티타늄질화막(26)은 완전히 산화되어 부도체가 되어서는 안되며, 산소와 결합하더라도 전도체로서의 성질을 갖고 있어야 한다.Since the first titanium nitride film according to the embodiment of the present invention has a thin thickness, oxygen filling is easy. However, during the oxygen filling process, the first titanium nitride film 26 should not be completely oxidized to become a non-conductor, and should have a property as a conductor even when combined with oxygen.
제1 티타늄질화막(26)에 산소를 충진시키기 위한 열처리는 400 ∼ 700℃의 온도에서 5초 내지 1분동안 급속열처리 방식으로 수행되는데, 이러한 열처리는 여러 분위기에서 수행될 수 있다.The heat treatment for filling oxygen into the first titanium nitride film 26 is carried out in a rapid heat treatment method for 5 seconds to 1 minute at a temperature of 400 ~ 700 ℃, this heat treatment may be performed in various atmospheres.
우선, 산소분위기, 오존분위기(O3), 산소플라즈마 분위기 등과 같이 산소가 포함된 분위기에서 수행될 수 있으며 또한, N2O 분위기, N2O 플라즈마 분위기, N2+O2분위기, N2+O2플라즈마 분위기 등과 같이 질소와 산소가 포함된 분위기에서 수행될 수도 있다. 또는 전술한 여러 분위기를 혼합한 분위기에서 열처리가 수행될 수도 있다.First, it may be performed in an atmosphere containing oxygen, such as an oxygen atmosphere, an ozone atmosphere (O 3 ), an oxygen plasma atmosphere, and also an N 2 O atmosphere, an N 2 O plasma atmosphere, an N 2 + O 2 atmosphere, and an N 2 + It may be performed in an atmosphere containing nitrogen and oxygen, such as an O 2 plasma atmosphere. Alternatively, the heat treatment may be performed in an atmosphere in which the various atmospheres are mixed.
전술한 여러 분위기에서 5초 내지 1분 동안 급속열처리하면 상기 제1 티타늄질화막(26)에 충분한 산소를 공급해 줄 수 있다.Rapid heat treatment for 5 seconds to 1 minute in the aforementioned various atmospheres may supply sufficient oxygen to the first titanium nitride film 26.
이러한 열처리 이후에 나머지 티타늄질화막(27)을 100 ∼ 400Å의 두께로 형성하고, 그 상부에 도핑된 폴리실리콘(28)을 1000 ∼ 3000Å의 두께로 형성하여 상부전극 구조를 완성한다.After the heat treatment, the remaining titanium nitride film 27 is formed to a thickness of 100 to 400 kPa, and the polysilicon 28 doped thereon is formed to a thickness of 1000 to 3000 kPa to complete the upper electrode structure.
이후에 도핑된 폴리실리콘 내부의 도판트(dopant)들의 활성화, 유전체와 상부전극간의 계면특성향상, 유전체의 안정화 등을 위하여, 종래와 같이 600 ∼ 800℃의 온도, 질소분위기에서 30분 정도의 열처리 단계를 수행한다.Afterwards, to activate dopants in the doped polysilicon, to improve the interfacial characteristics between the dielectric and the upper electrode, and to stabilize the dielectric, heat treatment for about 30 minutes in a nitrogen atmosphere at a temperature of 600 to 800 ° C. Perform the steps.
600 ∼ 800℃의 온도, 질소분위기에서 수행되는 열처리는 퍼니스(furnace)에서 20 ∼40분 동안 수행될 수 있으며, 급속열처리를 이용하는 경우에는 1분 ∼ 3분 동안 수행된다.Heat treatment carried out in a nitrogen atmosphere at a temperature of 600 ~ 800 ℃ can be carried out in the furnace (furnace) for 20 to 40 minutes, when using rapid heat treatment is carried out for 1 to 3 minutes.
이와같이 얇은 두께의 제1 티타늄질화막(26)을 먼저 형성하고 산소를 공급해 주는 열처리를 수행하면, 티타늄질화막의 전기적인 저항은 조금 증가하게 되지만, 티타늄질화막에 산소가 충진되어 있으므로 후속 열처리시에 상부전극이 유전체로부터 산소를 빼앗아 가는 경우가 감소하기 때문에 누설전류도 감소하게 되며, 유전체와 티타늄질화막 사이의 계면에서 티타늄산화물의 형성도 억제되어 유전율 감소와 같은 단점이 억제되는 효과가 있다.When the thin first titanium nitride film 26 is formed in this manner and the heat treatment for supplying oxygen is performed, the electrical resistance of the titanium nitride film is slightly increased. However, since the titanium nitride film is filled with oxygen, the upper electrode during the subsequent heat treatment. The leakage of oxygen from the dielectric is reduced, so that the leakage current is also reduced, and the formation of titanium oxide at the interface between the dielectric and the titanium nitride film is also suppressed, thereby reducing the disadvantages such as decreasing the dielectric constant.
본 발명은 도3에 도시된 바와 같이 상부전극형성을 2단계로 진행하고, 제1 상부전극형성 후, 제1 상부전극에 산소를 충진시키기 위한 열처리 공정을 도입하여 유전체의 특성저하를 방지하고 상부전극과 유전체 사이의 계면에 저유전율을 갖는 산화물의 생성을 억제한 것이다.In the present invention, as shown in FIG. 3, the upper electrode is formed in two stages, and after forming the first upper electrode, a heat treatment process for filling oxygen into the first upper electrode is introduced to prevent deterioration of the characteristics of the dielectric and The formation of an oxide having a low dielectric constant at the interface between the electrode and the dielectric is suppressed.
본 발명의 일실시예에서는 상부전극으로 티타늄질화막과 폴리실리콘이 적층되는 구조를 사용하였지만, 상부전극으로 루테늄, 루테늄산화물, 이리듐, 이리듐산화물 등을 사용하는 경우에는 상부전극 형성후, 산소를 충진시켜 주는 공정을 추가하면 유사한 효과를 얻을 수 있다.In the exemplary embodiment of the present invention, a structure in which a titanium nitride film and polysilicon are stacked is used as the upper electrode. However, when ruthenium, ruthenium oxide, iridium, or iridium oxide is used as the upper electrode, oxygen is charged after forming the upper electrode. A similar effect can be obtained by adding the giving process.
이상에서 설명한 바와 같이 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.
본 발명을 반도체 소자의 캐패시터 제조공정에 적용하게 되면, 상부전극과 유전체 사이의 계면에 저유전율막이 생성되는 것을 억제할 수 있으며, 또한 상부전극 증착시 유전체의 표면에 손상된 부분을 완전히 회복시킬 수 있으므로 신뢰성 있고 전기적인 특성이 우수한 캐패시터를 제조할 수 있다.When the present invention is applied to a capacitor manufacturing process of a semiconductor device, it is possible to suppress the formation of a low dielectric constant film at the interface between the upper electrode and the dielectric, and also to completely recover the damaged part of the surface of the dielectric during deposition of the upper electrode. Capacitors with reliable and excellent electrical properties can be manufactured.
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| KR20000027391A (en) * | 1998-10-28 | 2000-05-15 | 김영환 | Method for forming capacitor having tungsten nitride electrode |
| KR20000041427A (en) * | 1998-12-22 | 2000-07-15 | 김영환 | Method for fabricating capacitor having ta2o5 as dielectric film |
| KR20020016313A (en) * | 2000-08-25 | 2002-03-04 | 박종섭 | Method for manufactruing capacitor in semiconductor device |
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