KR100388465B1 - Ferroelectric capacitor having ruthenium bottom electrode and forming method thereof - Google Patents
Ferroelectric capacitor having ruthenium bottom electrode and forming method thereof Download PDFInfo
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- KR100388465B1 KR100388465B1 KR10-2001-0038679A KR20010038679A KR100388465B1 KR 100388465 B1 KR100388465 B1 KR 100388465B1 KR 20010038679 A KR20010038679 A KR 20010038679A KR 100388465 B1 KR100388465 B1 KR 100388465B1
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- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 title claims abstract description 34
- 229910052707 ruthenium Inorganic materials 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000003990 capacitor Substances 0.000 title claims abstract description 28
- 239000010408 film Substances 0.000 claims abstract description 65
- 239000010409 thin film Substances 0.000 claims abstract description 29
- -1 ruthenium tungsten nitride Chemical class 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 9
- 239000010937 tungsten Substances 0.000 claims abstract description 9
- 230000008021 deposition Effects 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- KLBQHAQKKVXWCI-UHFFFAOYSA-N bismuth lanthanum(3+) oxygen(2-) titanium(4+) Chemical compound [O--].[O--].[O--].[O--].[O--].[Ti+4].[La+3].[Bi+3] KLBQHAQKKVXWCI-UHFFFAOYSA-N 0.000 claims 1
- 238000000137 annealing Methods 0.000 abstract description 6
- 229910001925 ruthenium oxide Inorganic materials 0.000 abstract description 6
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 4
- 239000001301 oxygen Substances 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- VNRRSGPRRULRLF-UHFFFAOYSA-N oxotungsten;ruthenium Chemical compound [Ru].[W]=O VNRRSGPRRULRLF-UHFFFAOYSA-N 0.000 abstract description 2
- 230000002265 prevention Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 239000012298 atmosphere Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- 229910052743 krypton Inorganic materials 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052754 neon Inorganic materials 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052724 xenon Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/694—Electrodes comprising noble metals or noble metal oxides
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
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Abstract
본 발명은 반도체 제조 기술에 관한 것으로, 특히 강유전체 박막을 유전체로 사용하는 강유전체 캐패시터 형성 공정에 관한 것이며, 더 자세히는 루테늄(Ru) 하부전극을 갖는 강유전체 캐패시터 구조 및 형성 공정에 관한 것이다. 본 발명은 루테늄 하부전극 적용시 강유전체 박막의 어닐링에 의해 루테늄 하부전극 표면에 루테늄산화물이 형성되는 것을 방지할 수 있는 반도체 소자의 강유전체 캐패시터 및 그 형성방법을 제공하는데 그 목적이 있다. 본 발명에서는 강유전체 박막과 루테늄 하부전극의 계면에 루테늄텅스텐질화막(RuWNx)을 삽입한다. 루테늄텅스텐질화막은 산소 확산 방지력이 뛰어나기 때문에 루테늄산화물의 생성을 방지할 수 있다. 루테늄텅스텐산화막은 루테늄 하부전극 상에 텅스텐질화막(WNx)을 증착하고 소정의 열처리를 수행하여 형성한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a ferroelectric capacitor forming process using a ferroelectric thin film as a dielectric, and more particularly, to a ferroelectric capacitor structure and a forming process having a ruthenium (Ru) lower electrode. SUMMARY OF THE INVENTION An object of the present invention is to provide a ferroelectric capacitor of a semiconductor device and a method of forming the same, which can prevent ruthenium oxide from being formed on the surface of the ruthenium lower electrode by annealing the ferroelectric thin film when the ruthenium lower electrode is applied. In the present invention, a ruthenium tungsten nitride film (RuWNx) is inserted at the interface between the ferroelectric thin film and the ruthenium lower electrode. The ruthenium tungsten nitride film can prevent the generation of ruthenium oxide because of its excellent oxygen diffusion prevention ability. The ruthenium tungsten oxide film is formed by depositing a tungsten nitride film (WNx) on a ruthenium lower electrode and performing a predetermined heat treatment.
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 강유전체 박막을 유전체로 사용하는 강유전체 캐패시터 형성 공정에 관한 것이며, 더 자세히는 루테늄(Ru) 하부전극을 갖는 강유전체 캐패시터 구조 및 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a ferroelectric capacitor forming process using a ferroelectric thin film as a dielectric, and more particularly, to a ferroelectric capacitor structure and a forming process having a ruthenium (Ru) lower electrode.
강유전체 물질은 높은 유전상수(dielectric constant), 분극현상의 비휘발성(nonvolatile)으로 인해 반도체 메모리에 응용되어 DRAM(dynamic random access memory)의 고직접화(1Gb 이상) 및 새로운 형태의 비휘발성 반도체 메모리(FeRAM)의 구현에 필요한 물질로 등장하였다.Ferroelectric materials have been applied to semiconductor memories due to their high dielectric constant, polarity, and non-volatile properties, resulting in high directivity (1Gb or more) of dynamic random access memory (DRAM) and new types of nonvolatile semiconductor memory ( FeRAM) has emerged as a material for the implementation.
한편, 대표적인 강유전체 물질로는 Pb(ZrxTix-1)O3(PZT), (Sr,Bi)Ta2O9(SBT), SrBi2(Ta, Nb)2O9(SBTN), (BixLay)Ti3O12(BLT) 등이 있으며, 우수한 강유전체의 특성을 구현하기 위해서는 상/하부전극 물질 등의 주변 물질 및 공정의 제어가 필수적이다.Representative ferroelectric materials include Pb (Zr x Ti x-1 ) O 3 (PZT), (Sr, Bi) Ta 2 O 9 (SBT), SrBi 2 (Ta, Nb) 2O 9 (SBTN), (Bi x La y ) Ti 3 O 12 (BLT) and the like, it is necessary to control the peripheral materials and processes, such as the upper and lower electrode materials in order to implement excellent ferroelectric properties.
통상적으로, 강유전체 캐패시터의 상/하부전극 물질로서 Pt, Ir, IrO2, Ru, RuO2, W, WN, TiN 등을 사용하고 있다. 이 중에서도 Ru막은 기상유기화학증착법으로 증착이 가능하여 실린더형 캐패시터나 오목형 캐패시터를 구현하기에 적합한 장점이 있어 고집적 비휘발성 메모리 소자에의 적용이 유망한 전극재료로, 그에 대한 많은 연구가 진행되고 있다.Typically, Pt, Ir, IrO 2 , Ru, RuO 2 , W, WN, TiN, and the like are used as the upper and lower electrode materials of the ferroelectric capacitor. Among these, the Ru film can be deposited by vapor phase organic chemical vapor deposition, which is suitable for implementing cylindrical capacitors and concave capacitors. .
그런데, 루테늄 하부전극 상에 강유전체 박막을 증착할 때, 높은 분극 특성을 갖도록 하기 위해서는 반드시 고온의 산화 분위기의 어닐 공정을 수반해야 한다. 이때, 강유전체 박막에 어닐이 수행되면서 강유전체 박막에 접하는 루테늄 하부전극이 산화되어 Ru0x와 같은 산화막이 형성된다. Ru0x는 RuO2(x=2)와 같이 전극 재료로 사용되는 경우도 있으나, RuO4(x=4)의 경우에는 막질이 매우 떨어지는 경향이 있다. 즉, 강유전체 박막과 루테늄 하부전극 사이에 생성된 산화막은 막질이 다공성(porous)이며 일함수(work function)가 낮아 캐패시터의 누설전류를 증가시키고 강유전체 박막의 분극 특성을 열화시키는 문제점이 있다.However, when depositing a ferroelectric thin film on the ruthenium lower electrode, in order to have a high polarization characteristics must be accompanied by an annealing process of a high temperature oxidizing atmosphere. At this time, while annealing is performed on the ferroelectric thin film, the ruthenium lower electrode in contact with the ferroelectric thin film is oxidized to form an oxide film such as Ru0 x . Ru0 x may be used as an electrode material such as RuO 2 (x = 2), but in the case of RuO 4 (x = 4), the film quality tends to be very poor. That is, the oxide film formed between the ferroelectric thin film and the ruthenium lower electrode has a problem that the film quality is porous and the work function is low, thereby increasing the leakage current of the capacitor and deteriorating the polarization characteristics of the ferroelectric thin film.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 루테늄 하부전극 적용시 강유전체 박막의 어닐링에 의해 루테늄 하부전극 표면에 루테늄산화물이 형성되는 것을 방지할 수 있는 반도체 소자의 강유전체 캐패시터 및 그 형성방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the problems of the prior art, a ferroelectric capacitor of a semiconductor device capable of preventing the formation of ruthenium oxide on the surface of the ruthenium lower electrode by annealing the ferroelectric thin film when the ruthenium lower electrode is applied and The purpose is to provide a method of forming the same.
도 1 내지 도 5는 본 발명의 일 실시예에 따른 강유전체 캐패시터 형성 공정도.1 to 5 are ferroelectric capacitor formation process diagram according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
18 : 폴리실리콘 플러그18: polysilicon plug
19 : 실리사이드막19: silicide film
20 : 장벽금속층20: barrier metal layer
21 : 하부전극용 루테늄막21: ruthenium film for the lower electrode
22 : RuWNx 박막22: RuWNx thin film
23 : BLT 박막23: BLT thin film
24 : 상부전극용 루테늄막24: ruthenium film for upper electrode
상기의 기술적 과제를 해결하기 위한 본 발명의 일 측면에 따르면, 반도체 소자의 강유전체 캐패시터에 있어서, 소정의 하부층 상에 제공되는 루테늄 하부전극; 상기 루테늄 하부전극 상에 제공되는 루테늄텅스텐질화막; 상기 루테늄텅스텐질화막 상에 제공되는 강유전체 박막; 및 상기 강유전체 박막 상에 제공되는 상부전극을 구비하는 반도체 소자의 강유전체 캐패시터가 제공된다.According to an aspect of the present invention for solving the above technical problem, a ferroelectric capacitor of a semiconductor device, ruthenium lower electrode provided on a predetermined lower layer; A ruthenium tungsten nitride film provided on the ruthenium lower electrode; A ferroelectric thin film provided on the ruthenium tungsten nitride film; And a ferroelectric capacitor of a semiconductor device having an upper electrode provided on the ferroelectric thin film.
또한, 본 발명의 다른 측면에 따르면, 반도체 소자의 강유전체 캐패시터 형성방법에 있어서, 기판 상에 하부전극용 루테늄막을 형성하는 제1 단계; 상기 하부전극용 루테늄막 상에 루테늄텅스텐질화막을 형성하는 제2 단계; 상기 루테늄텅스텐질화막 상에 강유전체 박막을 형성하는 제3 단계; 및 상기 강유전체 박막 상에 상부전극용 전도막을 형성하는 제4 단계를 포함하는 반도체 소자의 강유전체 캐패시터 형성방법이 제공된다.Further, according to another aspect of the present invention, a method of forming a ferroelectric capacitor of a semiconductor device, comprising: a first step of forming a ruthenium film for a lower electrode on a substrate; A second step of forming a ruthenium tungsten nitride film on the ruthenium film for the lower electrode; Forming a ferroelectric thin film on the ruthenium tungsten nitride film; And a fourth step of forming a conductive film for an upper electrode on the ferroelectric thin film.
바람직하게, 상기 제2 단계는, 상기 하부전극용 루테늄막 상에 텅스텐질화막을 형성하는 제5 단계와, 열처리를 실시하여 상기 텅스텐질화막을 상기 루테늄텅스텐질화막으로 개질하는 제6 단계를 포함한다.Preferably, the second step includes a fifth step of forming a tungsten nitride film on the ruthenium film for the lower electrode, and a sixth step of modifying the tungsten nitride film to the ruthenium tungsten nitride film by performing heat treatment.
본 발명에서는 강유전체 박막과 루테늄 하부전극의 계면에 루테늄텅스텐질화막(RuWNx)을 삽입한다. 루테늄텅스텐질화막은 산소 확산 방지력이 뛰어나기 때문에 루테늄산화물의 생성을 방지할 수 있다. 루테늄텅스텐산화막은 루테늄 하부전극 상에 텅스텐질화막(WNx)을 증착하고 소정의 열처리를 수행하여 형성한다.In the present invention, a ruthenium tungsten nitride film (RuWNx) is inserted at the interface between the ferroelectric thin film and the ruthenium lower electrode. The ruthenium tungsten nitride film can prevent the generation of ruthenium oxide because of its excellent oxygen diffusion prevention ability. The ruthenium tungsten oxide film is formed by depositing a tungsten nitride film (WNx) on a ruthenium lower electrode and performing a predetermined heat treatment.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 1 내지 도 5는 본 발명의 일 실시예에 따른 강유전체 캐패시터 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1 to 5 illustrate a process of forming a ferroelectric capacitor according to an embodiment of the present invention, which will be described with reference to the following.
본 실시예에 따른 강유전체 캐패시터 형성 공정은, 우선 도 1에 도시된 바와같이 실리콘 기판(10) 상에 소자분리막(11), 워드라인(13), 비트라인(16) 등을 형성하고, 그 과정에서 형성된 층간절연막(15, 17)를 선택 식각하여 하부전극 콘택홀을 형성한 다음, 콘택홀 내에 폴리실리콘 플러그(18), 실리사이드막(19) 및 장벽금속층(20)을 형성하고, 전체 구조 상부에 하부전극용 루테늄막(21)을 형성한다. 여기서, 실리사이드막(19)은 저항성 접촉(ohmic contact)을 위한 것으로 Ti 실리사이드를 사용하는 것이 바람직하며, 장벽금속층(20)으로는 TiN막을 사용하는 것이 바람직하다. 또한, 하부전극용 루테늄막(21)은 씨드층으로 100∼800Å 두께의 TiN막을 씨드층으로 사용하여 증착하는 것이 바람직하며, 이를 위해 장벽금속층(20)을 콘택 내에만 잔류시키지 않고 층간절연막(17) 상부에도 잔류시킬 수 있다. 미설명 도면 부호 '12'는 게이트 산화막, '14'는 측벽 스페이서 산화막을 각각 나타낸 것이다.In the ferroelectric capacitor forming process according to the present embodiment, first, as shown in FIG. 1, an isolation layer 11, a word line 13, a bit line 16, etc. are formed on a silicon substrate 10, and the process Selectively etching the interlayer insulating layers 15 and 17 formed in the lower electrode contact holes to form a polysilicon plug 18, a silicide layer 19 and a barrier metal layer 20 in the contact holes, The lower electrode ruthenium film 21 is formed on the substrate. Here, the silicide film 19 is for ohmic contact, preferably Ti silicide, and the barrier metal layer 20 is preferably a TiN film. In addition, the lower electrode ruthenium film 21 is preferably deposited by using a TiN film having a thickness of 100 to 800 으로 as the seed layer, and for this purpose, the interlayer insulating film 17 without remaining the barrier metal layer 20 only in the contact. ) Can be left on top. Reference numeral '12' denotes a gate oxide film and '14' denotes a sidewall spacer oxide film, respectively.
다음으로, 도 2에 도시된 바와 같이 하부전극용 루테늄막(21) 상부에 20∼1000Å 두께의 WNx막을 증착하고, 400∼700℃의 온도의 N2분위기에서 급속열처리(RTA) 또는 전기로(furnace)열처리 방식으로 어닐을 실시하여 RuWNx막(22)을 형성한다. 이때, WNx막은 CVD법 또는 ALD법을 사용하며 증착할 수 있으며, CVD법으로 증착하는 경우 증착 압력은 1mTorr∼10Torr, 증착 온도는 200∼600℃가 적절하고, ALD법으로 증착하는 경우 증착 온도는 200∼400℃가 적절하다.Next, using a ruthenium lower electrode film 21 is deposited a film of thickness on the upper 20~1000Å WNx, and temperature of the rapid thermal annealing (RTA) or electrical in N 2 atmosphere at 400~700 ℃ for, as shown in Figure 2 ( The RuWNx film 22 is formed by annealing by heat treatment. At this time, the WNx film may be deposited using CVD or ALD method. In the case of CVD deposition, the deposition pressure is 1 mTorr to 10 Torr, and the deposition temperature is appropriately 200 to 600 ° C., and the deposition temperature is ALD. 200-400 degreeC is suitable.
이어서, 도 3에 도시된 바와 같이 RuWNx막(22) 상에 50∼2000Å 두께의 BLT 박막(23)을 증착한다. BLT 박막(23)의 증착은 스핀-온(spin-on)법, MOD(metal-orgnic decomposition)법, LSMCD(liquid source mist chemical deposition)법 등과같이 상온에서 액상 소스를 도포하고, 솔벤트 제거를 위한 베이크 공정을 실시한 후, 300∼450℃의 온도에서 10∼500W의 플라즈마 파워를 사용하여 산소 플라즈마 처리를 수행하여 박막의 산화를 이루고, O2, N2O, N2, Ar, Ne, Kr, Xe, He 등을 단독 또는 혼합 사용한 분위기에서 500∼900℃ 온도로 급속열처리(RTA)를 수행하여 핵 생성 및 성장을 유도하고, O2, N2O, N2, Ar, Ne, Kr, Xe, He 등을 단독 또는 혼합 사용한 분위기에서 500∼900℃ 온도로 전기로(furnace)열처리를 실시하여 결정립을 성장시키는 과정을 거친다. 한편, BLT 막막(23)은 Bi가 3.25∼3.35 원자농도, La가 0.80∼0.90 원자농도를 가지도록 조성비를 조절한다.Next, as illustrated in FIG. 3, a BLT thin film 23 having a thickness of 50 to 2000 μs is deposited on the RuWNx film 22. The deposition of the BLT thin film 23 is performed by applying a liquid source at room temperature such as spin-on, metal-orgnic decomposition (MOD), liquid source mist chemical deposition (LSMCD), and the like for solvent removal. After the baking process, oxygen plasma treatment is performed using a plasma power of 10 to 500 W at a temperature of 300 to 450 ° C. to oxidize the thin film, and O 2 , N 2 O, N 2 , Ar, Ne, Kr, Xe , performing the rapid heat treatment in 500~900 ℃ temperature such as in the He alone or in combination with an atmosphere (RTA) to induce nucleation and growth, and O 2, N 2 O, N2 , Ar, Ne, Kr, Xe, He The furnace is subjected to an electric furnace heat treatment at a temperature of 500 to 900 ° C. alone or in a mixed atmosphere to grow crystal grains. On the other hand, in the BLT film 23, the composition ratio is adjusted so that Bi has a concentration of 3.25 to 3.35 and La has a concentration of 0.80 to 0.90.
다음으로, 도 4에 도시된 바와 같이 상부전극용 루테늄막(24)을 형성한다.Next, as shown in FIG. 4, a ruthenium film 24 for upper electrodes is formed.
계속하여, 도 5에 도시된 바와 같이 상부전극용 루테늄막(24), BLT 박막(23), RuWNx막(22), 하부전극용 루테늄막(21)을 차례로 식각하여 캐패시터 구조를 형성한다.Subsequently, as shown in FIG. 5, the upper electrode ruthenium film 24, the BLT thin film 23, the RuWNx film 22, and the lower electrode ruthenium film 21 are sequentially etched to form a capacitor structure.
상기와 같은 공정을 실시하는 경우, 루테늄 하부전극과 BLT막의 계면에 산소 확산 방지력이 뛰어난 RuWNx막이 존재하기 때문에 막질이 떨어지는 루테늄산화물의 생성을 방지할 수 있다.In the above process, since the RuWNx film having excellent oxygen diffusion preventing ability exists at the interface between the ruthenium lower electrode and the BLT film, it is possible to prevent the generation of ruthenium oxide having poor film quality.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
예컨대, 전술한 실시예에서는 PP 구조의 캐패시터를 형성하는 경우를 일례로 들어 설명하였으나, 본 발명은 NPP 구조의 캐패시터를 형성하는 경우에도 적용할 수 있다.For example, in the above-described embodiment, a case of forming a capacitor having a PP structure has been described as an example, but the present invention can be applied to a case of forming a capacitor having an NPP structure.
또한, 전술한 실시예에서는 상부전극용 전도막으로 Ru를 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 상부전극용 전도막으로 Pt, Ir, IrO2, RuO2, W, WN, TiN 등을 사용하는 경우에도 적용된다.Further, in the above embodiment has been described for the case of using a Ru conductive film for the upper electrode as an example, the present invention is a conductive film for the upper electrode Pt, Ir, IrO 2, RuO 2, W, WN, TiN, etc. This also applies when using.
또한, 전술한 실시예에서는 강유전체 박막으로 BLT를 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 강유전체 박막 형성시 고온의 산화 분위기에서의 어닐 공정을 수반하는 PZT, SBT, SBTN 등을 사용하는 경우에도 적용된다.In addition, in the above-described embodiment, a case in which BLT is used as the ferroelectric thin film has been described as an example. However, the present invention uses PZT, SBT, SBTN, etc., which involves annealing in a high temperature oxidizing atmosphere when forming the ferroelectric thin film. Also applies.
전술한 본 발명은 루테늄 하부전극과 강유전체 박막의 계면에서 루테늄산화물의 생성을 방지하는 효과가 있으며, 이로 인하여 소자의 신뢰도 및 수율의 향상을 기대할 수 있다.The present invention described above has the effect of preventing the generation of ruthenium oxide at the interface between the ruthenium lower electrode and the ferroelectric thin film, thereby improving the reliability and yield of the device can be expected.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10135418A (en) * | 1997-10-07 | 1998-05-22 | Nec Corp | Ferroelectric capacitor and storage cell structure |
| KR20000014388A (en) * | 1998-08-20 | 2000-03-15 | 윤종용 | Ferroelectric memory capacitor and forming method thereof |
| KR20010008586A (en) * | 1999-07-02 | 2001-02-05 | 김영환 | Method of forming capacitor provied with TaON dielectric layer |
| KR20010046108A (en) * | 1999-11-10 | 2001-06-05 | 윤종용 | Capacitor of semiconductor memory device |
| KR20010064415A (en) * | 1999-12-29 | 2001-07-09 | 박종섭 | Method of forming high efficiency capacitor in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH10135418A (en) * | 1997-10-07 | 1998-05-22 | Nec Corp | Ferroelectric capacitor and storage cell structure |
| KR20000014388A (en) * | 1998-08-20 | 2000-03-15 | 윤종용 | Ferroelectric memory capacitor and forming method thereof |
| KR20010008586A (en) * | 1999-07-02 | 2001-02-05 | 김영환 | Method of forming capacitor provied with TaON dielectric layer |
| KR20010046108A (en) * | 1999-11-10 | 2001-06-05 | 윤종용 | Capacitor of semiconductor memory device |
| KR20010064415A (en) * | 1999-12-29 | 2001-07-09 | 박종섭 | Method of forming high efficiency capacitor in semiconductor device |
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