KR100365750B1 - Self-aligned contact formation method of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a self aligned contact in a semiconductor device is provided to be capable of simplifying self aligned contact processing by using a nitride spacer instead of an oxide spacer. CONSTITUTION: A gate oxide layer(32) is formed on a semiconductor substrate(31). After forming a gate electrode(33) on the gate oxide layer(32), an LDD(Lightly Doped Drain) region(34) is formed in the substrate. A nitride spacer(35) is then formed at both sidewalls of the gate electrode(33) and a nitride layer remains on the gate electrode. A source/drain region(36) is then formed in the substrate by implanting heavily doped dopants using the nitride spacer and the gate electrode as a mask. An oxide layer(37) is formed on the resultant structure. A contact hole is then formed to expose the source/drain region(36) by selectively etching the oxide layer using a photoresist pattern(38) as a mask.

Description

Self-aligned contact formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a self-aligned contact of a semiconductor device, and more particularly, to a method of forming a contact of a semiconductor device in which a contact of the semiconductor device is easily formed using a nitride film spacer.

In general, when a field effect transistor having a MOS structure is formed in manufacturing a semiconductor device, spacers are formed on the side of the gate electrode to form a lightly doped drain (LDD) structure. 1, a semiconductor substrate, 2 a gate oxide film, 3 a gate electrode, 4 an insulating film, 5 an oxide spacer, 10 a source / drain region, 11 an oxide film, and 12 a photoresist film. Represent each.

As shown in the drawing, after the gate electrode 3 is formed, a low concentration of ions are implanted, the insulating film 4 and the oxide film spacer 5 are formed, and a high concentration of ions are implanted to thereby source / drain regions 10. To form a transistor having an LDD structure.

However, when the oxide film is used as the spacer to form the LDD structure, as shown in FIG. 1, when the contact hole is formed in a subsequent process, the spacer is also etched when the contact hole is formed because the spacer is also an oxide film.

The etching of the spacers causes the electric field to be close to the gate electrode when the conductive film is deposited in the contact hole after the formation of the contact hole, so that a high amount of electric field is generated and the remaining spacer oxide layer is not etched, or a problem such as gate including drain leak There was a problem that could cause.

In order to solve this problem, a method of forming a self-aligned contact is illustrated in FIG. 2, in which a nitride film is deposited on an oxide spacer and then etched under an etching condition having a high etching selectivity with respect to the nitride film. In FIG. 2, the first reference numeral and the same reference numeral indicate the same name.

In the figure, the nitride film 6 is deposited before the insulating film 11 is formed so as to protect the underlying oxide spacers during the etching of the insulating film 11.

However, this method has a problem that the process is complicated by the addition of a nitride film deposition process.

An object of the present invention is to provide a method for forming a self-aligned contact of a semiconductor device capable of simplifying the process of forming a contact hole by self-alignment by replacing the oxide spacer with a nitride film spacer.

In order to achieve the above object, the present invention, forming a gate oxide film on a semiconductor substrate; Forming a gate electrode on the gate oxide film; Forming a low concentration impurity diffusion layer on the semiconductor substrate by implanting low concentration impurity ions using the gate electrode as a mask; Forming a nitride film over the structure including the gate electrode; Etching the entire surface of the nitride film to form a nitride film spacer in contact with both sidewalls of the gate electrode, and simultaneously leaving the nitride film at a predetermined thickness on the gate electrode; Forming a high concentration impurity diffusion layer connected to the low concentration impurity diffusion layer by high concentration impurity ion implantation using the nitride spacer and the gate electrode as a mask; Applying an oxide film over the entire structure; Forming a photoresist pattern for forming a contact hole on the oxide layer; And etching the oxide film using the photoresist pattern as a mask to expose the high concentration impurity diffusion layer.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 3.

In FIG. 3, reference numeral 31 denotes a semiconductor substrate, 32 a gate oxide film, 33 a gate electrode, 34 an LDD region, 35 a nitride spacer, 36 a source / drain region, 37 an oxide film, and 38 a photoresist pattern region, respectively. Indicates.

That is, according to the present invention, the gate oxide film 32 is formed on the semiconductor substrate 31 in the same manner as the general MOS transistor manufacturing method, and then the gate electrode 33 having a predetermined size is formed on the gate oxide film 32. Subsequently, the LDD region 34 is formed on the semiconductor substrate 31 on both sides of the gate electrode 33 by low concentration impurity ion implantation using the gate electrode 33 as a mask.

Subsequently, a nitride film is formed on the structure, and the entire surface is etched to form a nitride film spacer 35 in contact with both sidewalls of the gate electrode 33. Then, the nitride film spacer 35 and the gate electrode 33 are formed at high concentration. A source / drain region 36 connected to the LDD region 34 is formed by impurity ion implantation.

Subsequently, an oxide film 37 is applied over the entire structure, and a photoresist film is applied on the oxide film 37, and then patterned by exposure and development processes. Subsequently, the oxide layer 37 is etched using the patterned photoresist 38 as a mask to form a contact hole exposing an active region of the semiconductor substrate 31.

At this time, since the nitride spacer 35 has a large difference in etching selectivity with the oxide film 37 in a subsequent process, no loss occurs during etching of the oxide film 37 forming the contact hole. By maintaining a constant distance between the embedded conductive film and the gate electrode 33, it is possible to prevent breakage of the insulating film and leakage current.

When the nitride layer spacer 35 is formed, a nitride film having a predetermined thickness remains on the gate electrode 33. The reason is to insulate the gate electrode when the contact slightly deviates from the gate electrode 33.

In addition, it is easily understood by those skilled in the art that the present invention can prevent high electric field induced between the contact buried layer and the conductive film, which may occur in the process of forming contact holes between the conductive films formed on the interlayer insulating film. Could be.

According to the present invention as described above, the spacer formed in the gate electrode is formed of a nitride film, thereby minimizing an electric field with the contact buried layer connected to the active region of the substrate through the contact hole, and preventing insulation breakdown of the spacer insulating film, thereby improving device reliability. There is an effect that can be improved.

1 is a cross-sectional view illustrating a method for forming a self-aligned contact according to a conventional embodiment;

2 is a cross-sectional view illustrating a method for forming a self-aligned contact according to another embodiment of the prior art;

3 is a cross-sectional view illustrating a method for forming a self-aligned contact according to the present invention.

* Explanation of symbols for the main parts of the drawings

31: semiconductor substrate 32: gate oxide film

33: gate electrode 34: LDD region

35 nitride film spacer 36 source / drain regions

37: oxide film 38: photoresist pattern turn

Claims (1)

Forming a gate oxide film on the semiconductor engine; Forming a gate electrode on the gate oxide film; Forming a low concentration impurity diffusion layer on the semiconductor substrate by implanting low concentration impurity ions using the gate electrode as a mask; Forming a nitride film over the structure including the gate electrode; Etching the entire surface of the nitride film to form nitride spacers in contact with both sidewalls of the gate electrode, and simultaneously leaving the nitride film at a predetermined thickness on the gate electrode; Forming a high concentration impurity diffusion layer connected to the low concentration impurity diffusion layer by high concentration impurity ion implantation using the nitride spacer and the gate electrode as a mask; Applying an oxide film over the entire structure; And Forming a photoresist pattern for forming a contact hole on the oxide film; Etching the oxide layer using the photoresist pattern as a mask to expose the high concentration impurity diffusion layer; Self-aligning contact forming method of a semiconductor device comprising a.