KR20020052680A - Method of manufacturing a transistor in a semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a transistor of a semiconductor device is provided to reduce a junction leakage current by preventing attacks of a silicide layer from a gate electrode. CONSTITUTION: After forming a gate oxide layer(12) and a polysilicon layer(13) on a semiconductor substrate(11), an LDD(Lightly Doped Drain) region is formed. Then, an HLD oxide and a nitride layer are sequentially formed on the resultant structure. A first spacer(16a) is formed by firstly etch-back of the nitride layer. The exposed portion of the HLD oxide is removed. By secondly etch-back the first spacer, a gate spacer(16) including a nitride spacer(16a) and an HLD spacer(15) is formed. Source and drain regions(14) are formed in the substrate. A silicide layer(17) is formed on the gate electrode(13) and the source and drain regions(14).

Description

Method of manufacturing a transistor in a semiconductor device

The present invention relates to a method of manufacturing a transistor of a semiconductor device, and more particularly to a method of manufacturing a transistor of a semiconductor device that can improve the electrical properties by forming a silicide layer on the gate electrode and the source / drain to lower the resistance.

In recent years, as the channel length becomes shorter in the transistor of a semiconductor device having a design rule of 0.15 μm or less, the source / drain is formed in the LDD structure in which the gate electrode is formed at a low concentration and the remaining portions are formed at a high concentration. In order to form the source / drain of this structure, a gate spacer must be formed on the sidewall of the gate electrode. In addition, a silicide layer is formed on the surface in order to reduce the resistance of the gate electrode and the source / drain.

Referring to FIG. 1A, after the gate oxide layer 2 and the polysilicon layer 3 are sequentially formed on the semiconductor substrate 1, the polysilicon layer 3 and the gate may be formed by an etching process using the gate electrode mask as an etching mask. The oxide film 2 is patterned. Thereafter, a low concentration impurity ion implantation process is performed to form a source / drain of LDD structure to form a low concentration impurity region 4a. Again, the HLD oxide film 5 and the nitride film 6a are sequentially formed on the whole.

At this time, the HLD oxide film 5 is formed to a thickness of 140 to 160Å, ideally formed to a thickness of 150Å. Further, the nitride film 6a is formed to a thickness of 450 to 550 mm 3, and ideally formed to a thickness of 500 mm 3.

Referring to FIG. 1B, the nitride film 6a is etched entirely to form a spacer on the sidewall of the polysilicon layer 3.

Referring to FIG. 1C, an exposed portion of the HLD oxide film 5 is removed by an etching process using BOE to form a gate spacer 6 formed together with the nitride film 6a. At this time, an over etch of the HLD oxide film 5 occurs at the end A of the gate spacer 6.

In general, an advantage of the BOE etching process may prevent surface damage of the semiconductor substrate 1 when the HLD oxide layer 5 is etched. However, the BOE etching process can remove the HLD oxide film 5 without damaging the surface of the semiconductor substrate 1, but at the same time, the remaining HLD oxide film 5 is excessively etched at the lower end A of the gate spacer 6. Part is etched.

Referring to FIG. 1D, after forming the high concentration impurity region 4b by the high concentration impurity ion implantation process, heat treatment is performed to activate the ion implanted impurities to form the source / drain 4 of the LDD structure. Thereafter, the silicide process is performed to form the silicide layer 7 on the polysilicon layer 3 and the source / drain 4.

The silicide layer 7 is formed to lower the contact resistance of the polysilicon layer 3 and the source / drain 4. However, in the process of FIG. 1C, a portion of the HLD oxide film 5 under the gate spacer 6 is etched by the excessive etching, and the silicide layer 7 penetrates to the etched portion. When the silicide layer 7 penetrates toward the polysilicon layer 3, various problems may occur depending on the degree of penetration. That is, junction leakage may occur due to the silicide layer 7 formed under the gate spacer 6, and the electrical characteristics of the device may be degraded to cause defects.

Accordingly, the present invention is to solve the above problems by forming the gate spacer thicker than normal by the excessive etching amount of the HLD oxide film expected, and then etching the HLD oxide film to form a normal shape, so that the silicide layer is a gate electrode in a subsequent process. It is an object of the present invention to provide a method for manufacturing a transistor of a semiconductor device that can prevent penetration of the silicon layer to prevent the occurrence of junction leakage current and to stabilize the operation of the device to improve electrical characteristics.

1A to 1D are cross-sectional views of a device for explaining the transistor manufacturing method of a conventional semiconductor device.

2A to 2E are cross-sectional views of devices sequentially shown in order to explain a transistor manufacturing method of a semiconductor device according to the present invention.

<Description of the symbols for the main parts of the drawings>

1, 11: semiconductor substrate 2, 12: gate oxide film

3, 13: polysilicon layer 4a, 14a: low concentration impurity region

4b and 14b: high concentration impurity regions 4 and 14 source / drain

5, 15: HLD oxide film 6a, 16a: nitride film

6, 16 gate spacers 7, 17 silicide layer

In the method of manufacturing a transistor of a semiconductor device according to the present invention, after forming a low concentration impurity region in a semiconductor substrate on which a gate electrode is formed by primary impurity ion implantation, an oxide film and a nitride film are sequentially formed on the entire upper portion, and the nitride film is firstly etched first. Forming a spacer having a first thickness, etching and removing the exposed portion of the oxide film, etching the spacer-type nitride film to form a target thickness by secondary etching, and forming a gate spacer formed together with the oxide film, and having a low concentration. Second impurity ion implantation is performed on the exposed portion of the impurity region to form a high concentration impurity region, and then ion implanted impurities are activated by heat treatment to form a source / drain and a silicide layer on the gate electrode and the source / drain. Forming step.

The oxide film is formed of an HLD oxide film, but is formed to a thickness of 140 to 160Å, ideally formed to a thickness of 150Å. The nitride film is formed to a thickness of 450 to 550 GPa, ideally, to a thickness of 500 GPa. The first thickness of the nitride film is made about 150 mm thicker than the target thickness. Etching of the oxide film is performed using BOE, so that over etching of about 150 GPa occurs at the bottom of the gate spacer.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

2A through 2E are cross-sectional views of devices sequentially illustrated to explain a method of manufacturing a transistor of a semiconductor device according to the present invention.

Referring to FIG. 2A, after the gate oxide layer 12 and the polysilicon layer 13 are sequentially formed on the semiconductor substrate 11, the polysilicon layer 13 and the gate may be formed by an etching process using the gate electrode mask as an etching mask. The oxide film 12 is patterned. Thereafter, a low concentration impurity ion implantation process is performed to form a source / drain of LDD structure to form a low concentration impurity region 14a. Again, the HLD oxide film 15 and the nitride film 16a are sequentially formed on the whole.

At this time, the HLD oxide film 15 is formed to a thickness of 140 to 160Å, ideally formed to a thickness of 150Å. Further, the nitride film 16a is formed to a thickness of 450 to 550 mm 3, and ideally formed to a thickness of 500 mm 3.

Referring to FIG. 2B, the nitride film 16a is first etched to form a spacer on the sidewall of the polysilicon layer 13.

In this case, the nitride film 16a is formed in a spacer shape thicker than the normal thickness in consideration of the excessive etching of the HLD oxide film 15 in a subsequent process, and ideally, is formed to be about 150 GPa thicker.

Referring to FIG. 2C, the gate spacer 16 is formed together with the nitride layer 16a by removing the exposed portion of the HLD oxide layer 15 by an etching process using BOE. In this case, overetch of the HLD oxide layer 15 occurs at the end portion B of the gate spacer 16. However, since the nitride film 16a in the form of a spacer is formed in consideration of the excessive etching of the HLD oxide film 15, the HLD oxide film 15 is formed in the target shape by the excessive etching of the HLD oxide film 15. Is formed. In other words, since excessive etching of the HLD oxide film 15 cannot be avoided, the nitride film 16a is formed thick in advance, and then the HLD oxide film 15 having the target shape is formed by using the transient etching.

Referring to FIG. 2D, the second entire surface is etched to form the nitride film 16a to a target thickness. As a result, a gate spacer 16 in which the lower edge of the nitride film 16a and the end of the HLD oxide film 15 coincide with each other are formed. After forming the high concentration impurity region 14b by the high concentration impurity ion implantation process, heat treatment is performed to activate the ion implanted impurities to form the source / drain 14 of the LDD structure.

In this case, the second front side etching process may not be performed. However, if the gate spacers 16 are formed thick without performing the secondary front side etching process, it is preferable to perform the second front side etching process because they occupy the source / drain 14 region and the junction region becomes narrower.

Referring to FIG. 2E, a silicide process is performed to form the silicide layer 17 on the polysilicon layer 13 and the source / drain 14.

The silicide layer 17 is formed to lower the contact resistance between the polysilicon layer 13 and the source / drain 14. In the present invention, even when excessive etching occurs, the thickness of the nitride film 16a may be adjusted to form the HLD oxide film 15 in a target shape, thereby forming only a predetermined region of the silicide layer 17. Therefore, the silicide layer 17 may be prevented from penetrating into the polysilicon layer 13 to suppress the occurrence of junction leakage, thereby preventing the electrical characteristics of the device from being lowered.

As described above, the present invention controls the thickness of the nitride film for forming the gate spacer to form the HLD oxide film in a normal shape, thereby preventing the silicide layer from growing laterally and penetrating toward the gate electrode, thereby blocking the leakage current path. The operation is stabilized to improve the electrical characteristics of the transistor.

Claims (6)

Forming a low concentration impurity region by primary impurity ion implantation in a semiconductor substrate on which the gate electrode is formed, and then sequentially forming an oxide film and a nitride film over the entire surface; First etching the nitride film to form a spacer having a first thickness; Etching to remove the exposed portion of the oxide film; Forming a gate spacer formed with the oxide layer by etching the spacer-type nitride layer on the second front surface to a target thickness; Performing secondary impurity ion implantation on the exposed portion of the low concentration impurity region to form a high concentration impurity region and then activating the ion implanted impurity by heat treatment to form a source / drain; Forming a silicide layer on the gate electrode and the source / drain. The method of claim 1, The oxide film is formed of an HLD oxide film, but a thickness of 140 to 160 kHz, and ideally formed to a thickness of 150 kHz transistor manufacturing method of a semiconductor device. The method of claim 1, The nitride film is formed to a thickness of 450 to 550 Å, ideally formed to a thickness of 500 트랜지스터 transistor manufacturing method of a semiconductor device. The method of claim 1, And said first thickness of said nitride film is about 150 [mu] s thicker than said target thickness. The method of claim 1, The etching of the oxide film is a transistor manufacturing method of a semiconductor device, characterized in that performed using BOE. The method of claim 1, The etching of the oxide film is a method of manufacturing a transistor of a semiconductor device, characterized in that the excessive etching of about 150Å occurs in the lower portion of the gate spacer.