KR100303934B1 - Thin-film field-effect transistor with organic semiconductor requiring low operating voltages - Google Patents

Abstract

The present invention provides high field effect mobility, high current modulation, and a smaller sub-threshold slope in the region below the threshold voltage at lower operating voltages compared to current organic TFT devices. A thin film transistor (TFT) device structure based on an organic semiconductor material represented. The present invention relates to a method of manufacturing such a structure, in particular to a method of depositing a gate insulator using a chemical solution. The structure of the present invention can be protected by covering a set of conductive gate electrodes covered with high dielectric constant insulators, layers of organic semiconductors, several sets of electrically conductive source and drain electrodes corresponding to each gate line, and optionally device structures. Passive passivation layers comprise suitable substrates positioned in sequence.

The use of high dielectric constant gate insulators exploits the unexpected gate voltage dependence of organic semiconductors to achieve high field effect mobility levels at very low operating voltages. Appropriate selection and combination of such insulator materials and means for integrating them into the TFT structure is said to facilitate fabrication on organic or plastic substrates and that such devices can be used for flat panel display applications.

Description

THIN-FILM FIELD-EFFECT TRANSISTOR WITH ORGANIC SEMICONDUCTOR REQUIRING LOW OPERATING VOLTAGES}

TECHNICAL FIELD The present invention relates to the field of organic thin film field effect transistors, and more particularly to flat liquid crystal displays using such transistors.

More particularly, the present invention relates to an organic thin film field effect transistor (TFT) comprising a gate dielectric in which barium strontium titanate is deposited by a chemical solution process. In particular, the present invention relates to flat panel liquid crystal displays using such transistors.

Thin film field effect transistors used in liquid crystal displays (LCDs) typically use amorphous silicon (a-Si: H) as the semiconductor and silicon oxide and / or silicon nitride as the gate insulator. Recent studies of materials have shown that organic oligomers such as hexathiophene and derivatives thereof and organic molecules such as pentacene as potential semiconductors for amorphous silicon as semiconductors in thin film field effect transistors (G.Horowitz, D. Fichou, X. Peng, Z. Xu, F. Garnier, Solid State Commun. Volume 72, pg. 381, 1989 and US Patent No. 5,347,144 to F. Garnier, Z. Horwitz, D. Pichou.

The highest field effect mobility of TFTs based on thiophene-oligomers is typically about 0.06 cm ² V ⁻¹ sec ⁻¹ (F. Garnier, R. Hajlaui, A. Yasa (A. Yassar), see P. Srivastava, Science, Volume 265, pg 1684, 1994, which is much lower than the mobility of standard a-Si: H TFTs. Higher field effect mobility was measured only when cyanoethyl pullulan organic insulators were used (see US Pat. No. 5,347,144 to 0.4 cm ² V ⁻¹ sec ⁻¹ , F. Garnier, Z. Horowitz, D. Pichou). ). However, these insulators have poor dielectric strength and mobile charges {H. Horowitz, F. Deloffre, F. Garnier, Al. Hazlawi, M. Men. Hmyene), see A. Yassar, Synthetic Metals, Volume 54, pg 435, 1993. Some undesirable properties are indicated such as being susceptible to moisture. Therefore, it is not suitable for use as a gate insulator in the manufacture of practical TFT elements.

In recent years, field effect mobility of 0.6 cm ² V ⁻¹ sec ⁻¹ or less has been achieved in pentacene-based TFTs having SiO ₂ as a gate insulator {YYLin, D. J. See DJGundlach, TNJackson, 54 ^th Annual Device Research Conference Digest, 1996 pg. 80, which became potential candidates for such use. The main drawback of these pentacene-based organic TFTs is that high operating voltages (typically 0.4 μm thick SiO ₂ insulators typically required to achieve high threshold voltages, high mobility and at the same time high current modulation are typically used. 100V), which is a large slope (S) in the region below the threshold voltage, compared to about 0.3V per 10 current modulations achieved in a TFT based on a-Si: H (CYChen). , J. South Nicky see document ^{[54 th Annual Device Research Conference Digest} , 1996, pg.68] of (J.Kanicki)}, current modulation is about 10 per 14V {Y. Y. Lin, D. J. tiers Latch, T. N. Jackson, 54 ^th Annual Device Research Conference Digest, 1996, pg. 80. Reducing the thickness of a gate insulator improves the above-described characteristics, but is limited to reducing the thickness of the insulator. This is related to ease of manufacture and reliability issues. G. In the production of the current TFT LCD device, the thickness of the TFT gate dielectric is typically 0.4㎛.

Recently, organic TFTs comprising relatively high dielectric constant gate dielectrics, which have comparable performance to amorphous silicon TFTs and relatively low operating voltages, have been described (C.D.Dimitraco, which is incorporated herein by reference). From CDDimitrakopoulus, B.K.Furman, S.Purushothaman, D.A.Neumayer and P.D.Duncombe. See Docket No. YO997-057).

Processes for preparing metal oxide films by chemical solution processes have been described in recent years, particularly where metal alkoxyalkoxide solutions are used {D.A, filed March 10, 1997, which is incorporated herein by reference. See Newyer, P. Duncan (Docket No. YO997-069).

The electrical properties of a TFT with pentacene as a semiconductor, a heavily doped Si-wafer as a gate electrode, and a SiO ₂ , Au source and drain electrode thermally grown on the Si-wafer surface as a gate insulator are known standard field effect transistor equations { Suitably modeled by Szeze ("Physics of Semiconductor Devices", Wiley, New York, 1981, pg 442) {Gehrowitz, D. Pichou, X.Feng, Jet Esch, F. Garnier, Solid State Commun. Volume 72, pg. 381, 1989l and C. D. dimitracopulose, A. Brown, A. Pomp, J. Appl. Phys. Volume 80, pg 2501, 1996]. Pentacene used in these devices acts as a p-type semiconductor. Figure 1 of Y. Lynn, D. J. Gundlas, T. & Jackson [54 ^th Annual Device Research Conference Digest, 1996, pg. 80] shows the individual voltage (V _G) applied to the gate electrode. ) Shows the dependence of the current flow (I _D ) between the source and drain electrodes on the voltage (V _D ) applied to the drain electrode. When the gate electrode is biased with respect to the ground source electrode with a negative (−), the pentacene-based TFT operates in an accumulation mode and the accumulated carrier is a hole. At low V _D , I _D increases linearly with V _D (linear relationship) and is approximately represented by the following equation:

Where L is the channel length, W is the channel width, C _i is the capacitance per unit area of the insulating layer, V _T is the threshold voltage, and μ is the field effect mobility. Μ can be calculated in the linear region from the transconductance by plotting I _D with respect to V _G when V _D is constantly low and correcting the slope of this curve equal to g _m , as shown in Equation 2 below. have:

If the drain electrode is biased more negatively than the gate electrode (ie, -V _D is greater than or equal to -V _G ) and the source electrode is grounded (ie V _S is zero), the current flows between the source and the electrode (I _D ) tends to saturate due to pinch-off in the cumulative layer (saturation region) (which no longer increases) and is modeled by the following equation:

FIG. 2A shows the dependence of I _D on V _G at saturation (Wi. Y. Lynn, D. J. Gundlaschi, T. N. Jackson, 54 ^th Annual Device Research Conference Digest, 1996, pg. 80). ]. Battlefield Effect Mobility for V _G Can be calculated from the slope of the curve. 2B is for V _G Shows the curve of. The mobility calculated from this curve is 0.62 cm 2 V ⁻¹ sec ⁻¹ . Gradient of S in the threshold voltage below the area is approximately the current modulation 10 per 14V (Y. Y. Lin, D. J. tiers latch, T. yen. Et Jackson [54 ^th Annual Device Research Conference Digest, 1996, pg .80].

It is an object of the present invention to achieve the desired combination of high field effect mobility, low threshold voltage, small slope in the region below the threshold voltage and high current modulation without reducing the thickness of the insulator or using a high operating voltage. It is to provide a TFT structure. Such structures contain a combination of a high dielectric constant inorganic gate insulator layer (eg barium strontium titanate) and an organic semiconductor (eg pentacene).

Another object of the present invention is to provide a method of manufacturing such a structure.

It is a further object of the present invention that these materials are deposited at high dielectric constant gate insulators, for example by chemical solution processes, at temperatures well below the processing temperatures (less than 650 ° C.) when glass and plastic substrates are used in memory. It is to produce an organic TFT structure treated at a temperature (150 to 400 ℃) suitable for.

In particular another object of the present invention is a metal oxide thin film, preferably barium strontium titanate, in which a high dielectric constant gate insulator is deposited by a chemical solution process using a metal alkoxyalkoxide solution, preferably a metal butoxyethoxide. To produce an organic TFT structure comprising a metal oxide thin film such as barium titanate, bismuth titanate, strontium titanate, barium zirconate titanate, strontium bismuth tantalate niobate and strontium bismuth tantalate.

1 shows the operating characteristics of a pentacene-based TFT device having a SiO ₂ gate insulator. The dependence of the drain current as a function of the source-drain voltage is shown for different individual gate voltage values. See Lin et al. (1996).

FIG. 2A shows the same data as FIG. 1, but again plotted to show the dependence of the drain current as a function of the gate electrode in the saturation region.

FIG. 2B shows the drain electrode taken from FIG. 2 as a function of the gate electrode in the saturated region to calculate the field effect mobility. The values are plotted.

3 shows measurements of the operating characteristics of a TFT device using standard pentacene (purity 97% or higher) as a semiconductor and 120 nm thick SiO ₂ as a gate insulator.

FIG. 4A is a replot of the data taken in FIG. 3, illustrating the dependence of the drain current on the gate voltage in the saturation region.

FIG. 4b shows the data taken in FIG. 4a on a semilogarithmic scale used to calculate current slope and slope in the region below the threshold voltage.

4C shows the drain current taken from FIG. 4A as a function of gate voltage in the saturation region to calculate the field effect mobility. The values are plotted.

FIG. 5 is a curve of the field-effect mobility calculated for the device characterized in FIG. 3 at different gate voltages and at the same source-drain voltage (-100V), showing a strong dependency on the gate voltage of mobility.

6 is a schematic of a pentacene-based TFT device having a high dielectric constant gate insulator presented in the present invention.

FIG. 7A shows spin coating of a barium strontium titanate film with a layer thickness of 90 nm as a standard pentacene (more than 97% purity) as a semiconductor and a gate insulator (as described in Example 21) Or deposited by a sol gel process from a precursor solution based on isopropoxide). The dependence of the drain current on the gate voltage at a constant source-drain voltage is shown.

FIG. 7B plots the semilog of the data taken in FIG. 7A to calculate the slope in the region below the current modulation and threshold voltage.

FIG. 7C shows the drain current taken in FIG. 7A as a function of gate voltage in the saturation region to calculate the field effect mobility. The values are plotted.

8 is deposited by spin coating of a standard pentacene (more than 97% purity) as a semiconductor and a barium strontium titanate film as a gate insulator (Ba, Sr, Ti isopropanol / acetic acid solution as described in Example 21, or alkoxides Measured by the sol gel process from the precursor solution of the substrate). The dependence of the drain current on the source-drain voltage at different gate voltages is shown.

9A shows a barium strontium titanate film having a layer thickness of 90 nm as a standard pentacene (more than 97% purity) as a semiconductor and a gate insulator (as described in Example 4 in Ba, Sr, Ti butoxy in butoxyethanol; Deposited by spin coating of the tocoxide solution, or by spin-coating with a solution different from the solution used in FIGS. 7 and 8). Show the dependence of drain current on gate voltage at constant source-drain voltage.

FIG. 9B plots the semilog of the data taken from FIG. 9A to calculate the slope in the region below the current modulation and threshold voltage.

9C shows the drain current taken in FIG. 9A as a function of gate voltage in the saturation region to calculate the field effect mobility. The values are plotted.

The TFT structure proposed in the present invention and its manufacturing method are a high dielectric constant thin film gate insulator such as barium strontium titanate (BST), an organic semiconductor such as pentacene, a metal, a conductive polymer, a thickly doped high conductive material or a combination thereof Is used as the gate, source and drain electrodes.

Candidates of high dielectric constant, which can be used as the gate insulator layer in the structure, include Ta ₂ O ₅ , Y ₂ O ₃ , TiO ₂ and PbZr _X Ti _1-X O ₃ (PZT), Bi ₄ Ti ₃ O ₁₂ , BaMgF ₄ , SrBi ₂ (Ta _1-X Nb _X ) ₂ O ₉ , Ba (Zr _1-X Ti _X ) O ₃ (BZT) and Ba _X Sr _1-X TiO ₃ (BST), BaTiO ₃ , SrTiO ₃ and Ferroelectric insulators such as, but not limited to, Bi ₄ Ti ₃ O ₁₂ . These materials have been studied and used in combination with inorganic semiconductors mainly for memory devices in the past (P.Balk, cited herein by Advanced Materials, Volume 7, pg.703, 1995). ] Has never been combined with an organic semiconductor. Typically these insulators are annealed above 600 ° C. to achieve dielectric constants ε greater than 150.

In general, the structure proposed in the present invention uses a high dielectric constant inorganic gate insulator together with an organic semiconductor (eg pentacene) in a TFT structure. The high ε insulator can be annealed at 400 ° C. to achieve ε of at least 15, thereby enabling the use of glass or plastic substrates. If the high dielectric constant organic insulator has a high dielectric constant (ε is 15 or more) and meets other requirements such as environmental stability, high breakdown voltage, good film-forming ability, absence of flow charge, this is also the case with the above-mentioned inorganic It may be used in the structure of the present invention instead of an insulator.

Typical procedures used in the manufacture of TFT structures of the present invention include the following steps:

(1) to fabricate a gate electrode, which may be a thickly doped Si if the gate electrode is the substrate itself, otherwise it may be a patterned metal (or conductive polymer or other conductive material) gate electrode deposited and patterned on the substrate. step;

Sol gel spin coating and baking, sputtering, chemical vapor deposition (CVD), laser ablative deposition, and physical vapor deposition Depositing a high dielectric constant gate insulator on the gate electrode by one of a variety of methods, including but not limited to;

(3) optionally annealing the film at a suitable temperature in the range of 150 ° C to 400 ° C to improve the performance of the film and improve the dielectric constant;

(4) depositing the organic semiconductor on the gate insulator by one of a variety of methods including, but not limited to, deposition, spin-coating from solution, self-assembly of layers from solution;

⑤ fabricating an electrically conductive source and drain electrode on the organic semiconductor;

(6) optionally passivating the insulator by chemical vapor deposition, physical vapor deposition, spin-coating and curing.

The order of the deposition steps of the organic semiconductor and the fabrication steps of the source and drain electrodes may be changed for process suitability and ease of fabrication.

3 is a standard pentacene (purity 97% or more, purchased from FLUKA Chemical Co.) as a semiconductor layer, a thickly doped Si wafer as a gate electrode, and a 120 nm thick thermally grown SiO ₂ as a gate insulator; , A device having an Au source and a drain electrode, and the dependence of the current flow (I _D ) between the source and drain electrodes on the voltage (V _D ) applied to the drain electrode at different voltages (V _G ) applied to the gate electrode. Shows.

The linear relationship of the curve (ie at low V _D ) can be modeled by Equation 1 above.

4a and 4b are for the same device as described above and show the dependence of I _D on V _G in the saturation region. Battlefield Effect Mobility (μ) Calculated from the slope of the vs. V _G curve, it was 0.52 cm 2 V ⁻¹ sec ⁻¹ (FIG. 4C). The slope S in the region below the threshold voltage is 13.7 V per 10 current modulations. This data is comparable to the data for similar TFT structures described above in the prior art. As described above, the mobility is suitable for the practical TFT, but the inclination in the region below the operating voltage and the threshold voltage is too large compared to the a-Si: H TFT. As in Figs. 3 and 4, the electric field effect mobility measured from the TFT element shows the gate voltage dependency. High mobility is obtained especially at higher gate voltages. This necessitates the use of unrealistically high operating voltages in order to obtain acceptable mobility. Of the full-length-effect mobility (μ) measured in the TFT elements as in Figures 3 and 4. In order to solve this problem, the applied gate voltage, which is dependent on V _G was more detailed study. FIG. 5 shows the dependence of μ on the maximum V _G used in different gate-voltage-sweep experiments (V _D is constant at −100 V and V _S has always been 0 V).

The observed behavior is due to the dependence of mobility on the gate electric field (E), where And y is the thickness of the insulator, in which case a thinner gate dielectric layer can be used to achieve a high gate electric field. This is typically accomplished by conventional methods used in inorganic semiconductor TFT devices, but the thin dielectric has the limitation that it has pinhole defects and exhibits lower dielectric breakdown voltage and higher leakage current. Therefore, this method has no stall in utilizing the gate voltage dependent mobility of the pentacene-based TFT.

On the one hand, but not necessarily, the gate voltage dependence may be to prove a change in the accumulated concentration of carriers in terms of semiconductor / insulation scheme. In organic semiconductors, the trap potential is more easily filled due to the excessive accumulation of charge carriers, allowing additional carriers to move more easily without being interrupted by trapping. Carrier accumulation can be facilitated by replacing SiO ₂ with an insulator having a similar thickness but with a higher dielectric constant. In this case, a cumulative carrier concentration similar to that of the SiO ₂ case is obtained under conditions where the gate electric field and gate voltage are much lower and all other measures are the same.

If this hypothesis is correct, in these devices, high mobility must be achieved even at lower voltages compared to TFTs using SiO ₂ of comparable thickness. In the opposite case, in other words, if mobility depends on the electric field but not on the carrier concentration, relatively low mobility should be observed under the low gate voltage used for the latter sample. As shown below, a comparison of field-effect mobility measurements of devices based on two different insulators with similar thicknesses but different dielectric constants proved the hypothesis to be correct. The example shows in more detail a method for producing a pentacene-based TFT using a high dielectric constant inorganic film as a gate insulator and high field effect mobility at low operating voltages.

The present invention relates broadly to a method of manufacturing a thin film field effect transistor comprising a metal oxide film such as barium strontium titanate, bismuth titanate, strontium bismuth tantalate, barium titanate and strontium titanate and an organic semiconductor. will be. These gate insulators are made using metal alkoxyalkoxides in solution. Metal alkoxyalkoxide solutions are prepared by dissolving metal alkoxyalkoxides in a solvent. The metal alkoxyalkoxide solution is applied to the substrate and heated to form a metal oxide film.

The metal alkoxyalkoxide is _a compound in the form of ML _a (wherein M is a metal, L is an alkoxyalkoxide ligand and a is a subscript representing the number of alkoxyalkoxide ligand units necessary to meet valence requirements). Alkoxyalcohols are distinguished from alcohols in that they have an ether bond, ie COC, in the hydrocarbon backbone of the alkoxyalcohol. Metals that may be used include barium, strontium, titanium, bismuth, tantalum, magnesium, lead, yttrium, lanthanum, magnesium, calcium, zirconium, niobium and other elements. Alkoxy alcohols that may be used include methoxyethanol, ethoxyethanol, propoxyethanol, butoxyethanol, pentoxyethanol, heptoxyethanol, methoxypropanol, ethoxypropanol, propoxypropanol, butoxypropanol, pentoxypropanol and Heptoxypropanol is included, preferably butoxyethanol. All the listed alkoxyalcohols and all the metals listed above can form metal alkoxyalkoxides. Any miscible solvent is used to synthesize the metal alkoxyalkoxide solution. Miscible solvents that can be used include xylene, hydrocarbons such as toluene, halogenated solvents such as chloroform, methanol, ethanol, isopropanol, methoxyethanol, ethoxyethanol, propoxyethanol, butoxyethanol, pentoxyethanol, heptoxyethanol, Methoxypropanol, ethoxypropanol, propoxypropanol, butoxypropanol, pentoxypropanol and heptoxypropanol and are preferably butoxyethanol.

Metal alkoxyalkoxides are synthesized by reacting the metal with excess alkoxyalcohol, reacting the metal alkoxide with excess alkoxyalcohol, or reacting the metal halide salt with the lithium, sodium or potassium salt of the alkoxyalcohol. When alkali metal (Group 1A: Li, Na, K, Rb, Cs, Fr) or alkaline earth metal (Group 2A: Be, Mg, Ca, Sr, Ba, Ra) is added to the excess alkoxyalcohol and heated, The following reaction occurs:

M + L → ML _a + ½H ₂

When metal alkoxide is added to excess alkoxyalcohol and heated, the following reaction occurs:

MA _a + L → ML _a + aA

Wherein A is an alkoxide.

When a sufficiently reactive metal halide salt is added to the alkali metal (Group 1A: Li, Na, K, Rb, Cs, Fr) salt of the alkoxyalcohol and heated, the following reaction occurs:

MX _a + aNL → ML _a + aNX

Wherein X is a halide and N is an alkali metal (Group 1A, Li, Na, K, Rb, Cs, Fr).

The reaction summarized above is general and the specific reaction depends on the metal, alkoxide and alkoxyalcohol used. Detailed examples will be described later.

Once the metal alkoxyalkoxide is formed it is dissolved in a miscible solvent and applied to the substrate. The coated substrate is heat treated to make the film dense. The coated substrate may be annealed to crystallize the film. Detailed examples will be described later.

Examples of precursors according to the invention and methods of using the precursors according to the invention will be described later.

Example

Example 1-Ba (butoxyethoxide) ₂ Manufacturing Method

Under nitrogen, 25.2 g of barium metal was added to 123 mL butoxyethanol. The slurry was refluxed for 1 hour to complete the reaction. The solution was cooled to rt and filtered through a layer of celite in vacuo. The filtrate was a barium butoxyethoxide stock solution having a concentration of 1.42 mol / l or barium 22.69 wt%.

Example 2- Sr (butoxyethoxide) ₂ Manufacturing Method

Under nitrogen, 26.1 g of strontium metal was added to 293 g of butoxyethanol. The slurry was refluxed for 1 hour to complete the reaction. The solution was cooled to rt and filtered through a layer of celite in vacuo. The filtrate was a strontium butoxyethoxide stock solution having a concentration of 0.919 mol / l or strontium 8.92% by weight.

Example 3- Ti (butoxyethoxide) ₄ Manufacturing Method

Under nitrogen, 110 g of titanium (IV) isopropoxide was added to 100 mL butoxyethanol. Isopropanol was distilled off and an additional 100 mL butoxyethanol was added and refluxed for 1 hour. The solution was cooled to rt and filtered through a layer of celite in vacuo. The filtrate was a titanium butoxyethoxide stock solution with a final concentration of 1.53 mol / l or 7.91 wt% titanium.

Example 4- Ba using Ba, Sr, Ti butoxyethoxide solution _0.7 Sr _0.3 TiO ₃ Membrane Preparation

Under nitrogen, 11.11 g (0.0175 mol) of barium butoxyethoxide stock solution (Example 1), 8.57 g (0.0075 mol) strontium butoxyethoxide stock solution (Example 2), 15.14 g (0.025 mol) Titanium butoxyethoxide stock solution (Example 3) was dissolved in butoxyethanol. The solution was stirred at rt overnight, filtered and diluted to 50 ml. The resulting 0.5 M stock was stored for several months without degrading under nitrogen. A spin solution was prepared to obtain a 400 cc / layer membrane by diluting 1 part Ba _0.7 Sr _0.3 Ti stock solution with 3 parts butoxyethanol. The spin solution was placed in a syringe and 0.45 μm and 0.2 μm Whatman syringe filters were attached. The solution was scanned onto a Pt / Ti / SiO ₂ / Si substrate until the substrate was fully wetted. The substrate was then spun at 2500 rpm for 60 seconds. The coated substrates were dried on a 300 ° C. hotplate and then annealed in O ₂ at 400 ° C. for 10 minutes. Thicker films were made by depositing additional layers of the same film. After annealing, Pt dots were evaporated onto the film and the capacitance to the film was measured. The resulting sample had a dielectric constant between 16 and 17. The coated substrates were dried on a 300 ° C. hotplate, then each layer was deposited and then annealed by rapid heat treatment at 700 ° C. for 2 minutes. The resulting three or four layer sample had a dielectric constant of 200 to 340.

Example 5- Zr (butoxyethoxide) ₄ Manufacturing Method

Under nitrogen, 110 g zirconium (IV) isopropoxide was added to 100 mL butoxyethanol. Isopropanol was distilled off, and additional 100 mL butoxyethanol was added and refluxed for 1 hour. The solution was cooled to rt and filtered through a layer of celite in vacuo. The filtrate was a zirconium butoxyethoxide stock solution.

Example 6 Ba (Zr) using Ba, Zr, Ti butoxyethoxide solution _0.5 Ti _0.5 ) O ₃ Membrane Preparation

Under nitrogen, 0.025 mol of barium butoxyethoxide stock solution (Example 1), 0.0125 mol of zirconium butoxy ethoxide stock solution (Example 4) and 0.0125 mol of titanium butoxy ethoxide stock solution (Example 3) Was dissolved in butoxyethanol. The solution was stirred at rt overnight, filtered and diluted to 50 ml. The resulting 0.5 M stock was stored for several months without degrading under nitrogen. A solution for spin coating was prepared by diluting 1 part BaZrTi stock solution with 3 parts butoxyethanol. The spin solution was placed in a syringe and 0.45 μm and 0.2 μm Whatman syringe filters were attached. The solution was scanned onto a Pt / Ti / SiO ₂ / Si substrate until the substrate was fully wetted. The substrate was then spun at 2500 rpm for 60 seconds. The coated substrates were dried on a 300 ° C. hotplate and then annealed in O ₂ at 400 ° C. for 10 minutes. Further layers were deposited to produce thicker membranes.

Example 7- Ba (methoxyethoxide) ₂ Manufacturing Method

Under nitrogen, 25.1 g of barium metal was added to 250 ml methoxyethanol. The slurry was refluxed for 1 hour to complete the reaction. The solution was cooled to rt and filtered through a layer of celite in vacuo. The filtrate was a barium methoxyethoxide stock solution having a concentration of 0.58 mol / l or 8.27 wt% barium.

Example 8-Sr (methoxyethoxide) ₂ Manufacturing Method

Under nitrogen, 25.4 g of strontium metal was added to 185 g of methoxyethanol. The slurry was refluxed for 1 hour to complete the reaction. The solution was cooled to rt and filtered through a layer of celite in vacuo. The filtrate was a strontium methoxyethoxide stock solution having a concentration of 1.51 mol / l or strontium 13.75% by weight.

Example 9-Ti (methoxyethoxide) ₄ Manufacturing Method

Under nitrogen, 71.06 g of titanium (IV) isopropoxide was added to 100 mL of methoxyethanol. Isopropanol was distilled off and additional 100 ml methoxyethanol was added and refluxed for 1 hour. The solution was cooled to rt and filtered through a layer of celite in vacuo. The filtrate was a titanium methoxyethoxide stock solution with a final concentration of 1.09 mol / l or 5.42 weight percent titanium.

Example 10 Ba using Ba, Sr, Ti methoxyethoxide solution _0.7 Sr _0.3 TiO ₃ Membrane Preparation

Under nitrogen, 58.12 g (0.035 mol) of barium methoxyethoxide stock solution (Example 7), 10.07 g (0.015 mol) of strontium methoxyethoxide stock solution (Example 8), 44.19 g (0.050 mol) The titanium methoxyethoxide stock solution (Example 9) was dissolved in 2-methoxyethanol with stirring. The solution was stirred overnight at room temperature, filtered and diluted to 250 ml marked flask. The resulting 0.2M stock was stored for several months without degrading under nitrogen. A solution for spin coating was obtained by diluting 1 part Ba _0.7 Sr _0.3 Ti methoxyethoxide stock solution with 1 part isopropanol to obtain a 200 cc / layer film. The spin solution was placed in a syringe and 0.45 μm and 0.2 μm Whatman syringe filters were attached. The solution was scanned onto a Pt / Ti / SiO ₂ / Si substrate until the substrate was fully wetted. The substrate was then spun at 2500 rpm for 60 seconds. The coated substrates were dried on a 200-400 ° C. hotplate and then annealed in O ₂ at 400 ° C. for 10 minutes. Additional layers were deposited to produce thicker films.

Example 11- Ta (butoxyethoxide) ₅ Manufacturing Method

Under nitrogen, 53.13 g of tantalum (V) ethoxide was added to 150 mL butoxyethanol with stirring. Ethanol was distilled off and an additional 50 ml of butoxyethanol was added and refluxed for 1 hour. The solution was cooled to room temperature and filtered through a layer of celite in vacuo. The filtrate was a tantalum butoxyethoxide stock solution.

Example 12- Ta (methoxyethoxide) ₅ Manufacturing Method

Under nitrogen, 4.06 g of tantalum (V) ethoxide was added to 100 ml of methoxyethanol with stirring. The solution was refluxed for 1 hour before the ethanol was distilled off. A further 100 ml methoxyethanol was added and the procedure was repeated two more times. The solution was cooled to rt and filtered through a layer of celite in vacuo. The filtrate was a tantalum butoxyethoxide stock solution with a final concentration of 0.079 mol / l or tantalum 1.5% by weight.

Example 13- Zr (methoxyethoxide) ₅ Manufacturing Method

Under nitrogen, 96.92 g zirconium (IV) isopropoxide was added to 100 mL of methoxyethanol with stirring. The solution was refluxed for 1 hour before the ethanol was distilled off. A further 100 ml methoxyethanol was added and the procedure was repeated two more times. The solution was cooled to rt and filtered through a layer of celite in vacuo. The filtrate was a zirconium methoxyethoxide stock solution with a final concentration of 0.94 mol / l or zirconium 8.89% by weight.

Example 14 Ba (Zr) using Ba, Zr, Ti methoxyethoxide solution _0.5 Ti _0.5 ) O ₃ Membrane Preparation

Under nitrogen, 0.02 mol of barium methoxyethoxide stock solution (Example 1), 0.01 mol of zirconium butoxyethoxide stock solution (Example 4) and 0.01 mol of titanium methoxyethoxide stock solution (Example 3) Was dissolved in methoxyethanol. The solution was stirred at rt overnight, filtered and diluted to 100 ml. The resulting 0.2M stock was stored for several months without degrading under nitrogen. Spin solutions were prepared by diluting 1 part BaZrTi stock solution with 1 part methoxyethanol. The spin solution was placed in a syringe and 0.45 μm and 0.2 μm Whatman syringe filters were attached. The solution was scanned onto a Pt / Ti / SiO ₂ / Si substrate until the substrate was fully wetted. The substrate was then spun at 2500 rpm for 60 seconds. The coated substrates were dried on a 300 ° C. hotplate and then annealed in O ₂ at 400 ° C. for 10 minutes. Additional layers were deposited to produce thicker films.

Example 15 Bi (butoxyethoxide) ₃ Manufacturing Method

Under an inert atmosphere, 28.9 g (0.244 moles) of butoxyethanol were added dropwise while stirring a suspension of 9.45 g (0.394 moles) of sodium hydride in 100 ml tetrahydrofuran. After stirring for 30 minutes, the slurry was filtered through a celite bed. To the filtrate was added 25.0 g (0.0793 moles) BiCl ₃ dissolved in 100 mL of tetrahydrofuran. After stirring for 12 hours, tetrahydrofuran was removed in vacuo to yield a cloudy yellow slurry which was extracted with 250 ml of anhydrous toluene. The extract was filtered through a celite bed. Toluene was removed from the filtrate in vacuo to yield a pale yellow oil which was extracted with 500 ml of pentane. The pentane extract was filtered through a layer of celite and the pentane was removed from the filtrate to give a pale yellow liquid.

Example 16-Nb (butoxyethoxide) ₅ Manufacturing Method

While stirring under nitrogen, 50.22 g of niobium (V) ethoxide was added to 150 mL butoxyethanol. Ethanol was distilled off and an additional 50 ml of butoxyethanol was added and refluxed for 1 hour. The solution was cooled to rt and filtered through a layer of celite in vacuo. The filtrate was a niobium butoxyethoxide stock solution.

Example 17- SrBi Using Sr, Bi, Ta Butoxyethoxide Solution ₂ Ta ₂ O ₉ Membrane Preparation

Under nitrogen, 0.02 mol of strontium butoxyethoxide stock solution (Example 2), 0.04 mol of bismuth butoxyethoxide stock solution (Example 15) and 0.04 mol of tantalum butoxyethoxide stock solution (Example 11) Was added. The solution was stirred at rt overnight, filtered and diluted to 100 ml. Spin solutions were prepared by diluting 1 part SrBi ₂ Ta ₂ stock solution with 1 part butoxyethanol. The spin solution was placed in a syringe and 0.45 μm and 0.2 μm Whatman syringe filters were attached. The solution was scanned onto a Pt / Ti / SiO ₂ / Si substrate until the substrate was fully wetted. The substrate was then spun at 2500 rpm for 60 seconds. The coated substrate was dried on a 300 ° C. hotplate and then annealed at 400 ° C. or 750 ° C. for 30 minutes. Additional layers were deposited to produce thicker films.

Example 18- Sr using Sr, Bi, Ta butoxyethoxide solution _0.8 Bi _2.2 Ta ₂ O ₉ Membrane Preparation

Under nitrogen, 0.016 mol of strontium butoxyethoxide stock solution (Example 2), 0.044 mol of bismuth butoxyethoxide stock solution (Example 15) and 0.04 mol of tantalum butoxyethoxide stock solution (Example 11) Was added. The solution was stirred at rt overnight, filtered and diluted to 100 ml. Spin solutions were prepared by diluting 1 part Sr _0.8 Ba _2.2 Ta ₂ stock solution with 1 part butoxyethanol. The spin solution was placed in a syringe and 0.45 μm and 0.2 μm Whatman syringe filters were attached. The solution was scanned onto a Pt / Ti / SiO ₂ / Si substrate until the substrate was fully wetted. The substrate was then spun at 2500 rpm for 60 seconds. The coated substrate was dried on a 300 ° C. hotplate and then annealed at 400 ° C. or 750 ° C. for 30 minutes. Additional layers were deposited to produce thicker films.

Example 19-SrBi Using Sr, Bi, Ta, Nb Butoxyethoxide Solution ₂ (Ta _1.5 Nb _0.5 ) O ₉ Membrane Preparation

Under nitrogen, 0.02 mol of strontium butoxyethoxide stock solution (Example 2), 0.04 mol of bismuth butoxyethoxide stock solution (Example 15), 0.03 mol of tantalum butoxyethoxide stock solution (Example 11) And 0.01 mol of niobium butoxyethoxide solution (Example 16) were added. The solution was stirred at rt overnight, filtered and diluted to 100 ml. Spin solutions were prepared by diluting 1 part Sr _0.8 Ba _2.2 Ta ₂ stock solution with 1 part butoxyethanol. The spin solution was placed in a syringe and 0.45 μm and 0.2 μm Whatman syringe filters were attached. The solution was scanned onto a Pt / Ti / SiO ₂ / Si substrate until the substrate was fully wetted. The substrate was then spun at 2500 rpm for 60 seconds. The coated substrate was dried on a 300 ° C. hotplate and then annealed at 400 ° C. or 750 ° C. for 30 minutes. Additional layers were deposited to produce thicker films.

Example 20 Bi, Bi Using Ta Butoxyethoxide Solution ₄ Ti ₃ O ₁₂ Membrane Preparation

Under nitrogen, 0.02 moles of bismuth butoxyethoxide stock solution (Example 15) and 0.015 moles of titanium butoxyethoxide stock solution (Example 3) were mixed with each other and stirred at room temperature overnight. The solution was filtered and diluted to 100 ml with butoxyethanol. The solution was stirred at rt overnight, filtered and diluted to 100 ml. Spin solutions were prepared by diluting 1 part Bi ₄ Ti ₃ stock solution with 1 part butoxyethanol. The spin solution was placed in a syringe and 0.45 μm and 0.2 μm Whatman syringe filters were attached. The solution was scanned onto a Pt / Ti / SiO ₂ / Si substrate until the substrate was fully wetted. The substrate was then spun at 2500 rpm for 60 seconds. The coated substrate was dried on a 300 ° C. hotplate and then annealed at 400 ° C. or 700 ° C. for 10 minutes. Additional layers were deposited to produce thicker films.

Example 21- Ba, Sr, Ba using Ti isopropanol / acetic acid solution _0.7 Sr _0.3 TiO ₃ Membrane Preparation

In a glove box, 23.985 g (0.035 mole) of 20.04 wt% BaIPA ₂ in IPA, 13.893 g (0.015 mole) of 9.46 wt% SrIPA ₂ and 14.213 g (0.05 mole) TIP were mixed with each other. While stirring under nitrogen, 200 ml of anhydrous IPA and 50 ml of glacial acetic acid were further added. A white precipitate formed which dissolved again when stirred. The solution was stirred at rt overnight and filtered through a celite bed in vacuo. The stock solution was stable for about 1 month under nitrogen, after which a barium precipitate was observed. Spin solutions were prepared by diluting the stock solution to 1: 1 with the same amount of IPA. The spin solution was placed in a syringe and 0.45 μm and 0.2 μm Whatman syringe filters were attached. The solution was scanned onto a Pt / Ti / SiO ₂ / Si substrate until the substrate was fully wetted. The substrate was then spun at 2500 rpm for 60 seconds. The coated substrate was dried on a 350 ° C. hotplate and then annealed at 400 ° C. for 10 minutes. Additional layers were deposited to produce thicker films. Pt dots were evaporated onto the annealed film and the capacitance to the film was measured.

Example 22-Fabrication of Organic Thin Film Transistors Using Chemically Solution Deposited Gate Dielectrics

As a gate insulator, a thin film of barium strontium titanate (BST) was deposited by a sol-gel method to produce a TFT. The organic semiconductor used in this device was deposited pentacene by vacuum sublimation. The gate electrode was an aluminum or Pt / Ti bilayer and the source and drain electrodes consisted of Au. The substrate used was a Si wafer covered with a quartz disk or a thermally grown SiO ₂ layer.

Oxidized silicon or quartz substrates were cleaned by ultrasonic stirring in an isopropanol bath and dried with nitrogen. It was then assembled using a metal mask with openings that fit the gate line, placed in an electron beam evaporator and pumped under high vacuum. A gate metal of two layers of 40 nm aluminum or 15 nm titanium and 30 nm Pt was deposited on the substrate by electron beam evaporation. The sample was removed from the assembly and a layer of high dielectric constant insulator was deposited by the sol-gel method or the chemical solution process described in the above examples.

In this method, metal oxide films were prepared using precursors or other types of organometallic precursor solutions, including, for example, short-chain metal alkoxides or metal alkoxyalkoxide solutions, including but not limited to metal isopropoxide. The solution was applied onto the substrate by liquid deposition (eg spin-coating). The coated substrates were baked to dry and anneal the precursors. Specifically, the spin solution was placed in a syringe equipped with 0.45 μm and 0.2 μm Whatman syringe filters. The solution was injected onto the substrate until the substrate was completely wetted. The substrate was then spun at 2500 rpm for 45 seconds. The coated substrate was dried on a 200-400 ° C. hotplate and then annealed for 10-20 minutes at a temperature below 400 ° C. Thicker membranes were made by repeating the process by continuous coating and annealing steps.

The film was intentionally baked only at a suitable temperature (below 400 ° C.) to enable use with glass and plastic substrates. The result was an amorphous insulator film with a dielectric constant of about 16, while the dielectric constant was greater than 300 when the film was crystallized by heating to 650 ° C. As seen briefly above, a slight increase in the dielectric constant obtained using this amorphous film is suitable for organic TFT applications. However, the scope of the present invention is not limited to this deposition method. Films of BST films and most gate insulators of the high dielectric constant described above can alternatively be deposited using sputter deposition methods, laser ablation or CVD, and using these methods is not a departure from the inventive concept.

The organic semiconductor layer (pentacene) was deposited by vapor deposition in an ultra high vacuum (UHV) chamber. It can also be deposited in cheaper high vacuum chambers, in which case similar results were obtained. On the one hand, such membranes can be deposited using soluble precursors of pentacene, which are converted to pentacene when heated to 140 ° C. in a vacuum {ARBrown, A. Pomp. , D.M. By DMde Leeuw, DBMKlaassen, EEHavinga, P.Herwig and K.Mullen Journal of Applied Physics, Volume 79, pg. 2136, 1996]. The sample was then assembled into a mask with openings for the source and drain contact electrodes, placed in an electron beam evaporator, pumped and covered with 60 nm gold to create source / drain contacts. The resulting TFT structure is schematically shown in FIG. Other source drain junction materials such as chromium, titanium, copper, aluminum, molybdenum, tungsten, nickel, gold, platinum, palladium, conductive polymers, oligomers and organic molecules may be used without departing from the inventive concept.

The completed TFT samples were then electrically tested using a Hewlett Packard Model 4145B semiconductor scale analyzer to determine their operating characteristics.

7A and 7B show typical examples of the pentacene-based TFT shown by schematic 6, wherein the thickness of the BST gate-insulator was about 90 nm and its dielectric constant ε is approximately 16. FIG. Insulators were deposited from isopropoxide-based solutions in isopropanol as described above. The source drain interval (channel length L) was 83 μm and the channel width W was 1500 μm. The figure shows the dependence of I _D on V _G at saturation. 7C shows I _D for V _G. The values are plotted. Battlefield Effect Mobility (μ) Calculated from the slope of the curve of vs V _G , 0.38 cm 2 V ⁻¹ sec ⁻¹ . Current modulation is 3 × 10 ⁵ or more for a 4V gate potential change. The slope S in the region below the threshold voltage is about 0.4V per 10 current modulations.

FIG. 8 shows the dependence of the current flow I _D between the source and drain electrodes on the voltage V _D applied to the drain electrode under the individual voltage V _G applied to the gate electrode for the device described above in the previous paragraph. Shows.

9A and 9B relate to the pentacene-based TFT shown by FIG. 6, wherein the capacitance per unit area of the BST gate-insulator layer is similar to the BST film in conventional devices. The BST layer was deposited from another type of sol-gel solution of Ba, Sr and Ti organometallic precursors as described above or as described in Example 4. Both figures show the dependence of I _D on V _G at saturation. 9C shows I _D for V _G. The values are plotted. Battlefield Effect Mobility (μ) Calculated from the slope of the curve of vs V _G , 0.62 cm 2 V ⁻¹ sec ⁻¹ . The slope S in the region below the threshold voltage is about 0.4V per 10 current modulations. The channel length is 109 μm and the channel width W is 250 μm.

Thus, it is evident that in a pentacene-based TFT device using a high dielectric constant film as the gate insulator, a high mobility and a small slope in the region below the threshold voltage can be achieved. This demonstrates our hypothesis that the gate voltage dependence in the device is due to the higher concentration of charge carriers achieved by the insulator by keeping the applied gate field very low.

Despite the specific mechanisms by which the properties are achieved, there is claimed a structure for achieving high field effect mobility, high current modulation and small slope in the region below the threshold voltage in a pentacene-based organic TFT and a method of manufacturing the same. While the present invention has been described in terms of preferred embodiments, those skilled in the art may make many changes, changes, and improvements without departing from the spirit and scope of the invention.

According to the present invention, a thin film transistor element structure based on an organic semiconductor material exhibiting a high electric field effect mobility, a high current modulation, and a smaller slope in a region below a threshold voltage at a lower operating voltage compared to current organic TFT devices is disclosed. Is provided. The use of high dielectric constant gate insulators in accordance with the present invention leverages the unexpected gate voltage dependence of organic semiconductors to achieve high field effect mobility levels at very low operating voltages. The material of such an insulator and the means for integrating it into the TFT structure can be appropriately selected and combined to facilitate fabrication on organic or plastic substrates and such devices can be used for flat panel display applications.

Claims (19)

In the thin film transistor device structure, A substrate on which a plurality of electrically conductive gate electrodes are located; (2) a layer of high dielectric constant gate insulator, positioned over this gate electrode; (3) a layer of organic semiconductor positioned on the insulator and substantially overlapping the gate electrode; (4) have several sets of electrically conductive source and drain electrodes in line with each gate electrode on this organic semiconductor; The insulator is barium strontium titanate, barium zirconate titanate, lead zirconate titanate, lead lanthanum titanate, barium titanate, strontium titanate, barium magnesium fluoride, tantalum pentoxide, titanium dioxide and yttrium trioxide Structure selected from the group consisting of. The method of claim 1, The structure further includes an insulating passivation layer positioned over the structure to further prevent the structure from being exposed to the process and external environment. The method of claim 1, Wherein the substrate is selected from the group consisting of glass, plastic, quartz, undoped silicon, and thickly doped silicon. The method of claim 1, Wherein the material of the gate electrode is selected from the group consisting of chromium, titanium, copper, aluminum, molybdenum, tungsten, nickel, gold, platinum, conductive polyaniline, conductive polypyrrole and combinations thereof. The method of claim 1, The gate electrode has a thickness of 30 nm to 500 nm and is manufactured by a method selected from the group consisting of evaporation, sputtering, chemical vapor deposition, electrodeposition, spin coating and electroless plating. . The method of claim 1, The insulator has a thickness of 80 nm to 1000 nm. The method of claim 1, Wherein the insulator is produced by a method selected from the group consisting of sputtering, chemical vapor deposition, sol-gel coating, evaporation and laser ablation deposition. The method of claim 1, The organic semiconductor is any polymeric or oligomeric semiconductor whose field effect mobility increases with increasing gate voltage. The method of claim 8, A structure in which an organic semiconductor is an acene molecular material. The method of claim 8, The organic semiconductor layer has a single layer to a thickness of 400nm. The method of claim 8, A structure in which a semiconductor layer is deposited by a method selected from the group consisting of evaporation, chemical vapor deposition, spin coating and baking, electron polymerization, molecular beam deposition, self-assembly from solution, and combinations thereof. The method of claim 8, A structure in which a semiconductor layer is optionally segmented by a process selected from the group consisting of deposition through a mask, screen printing, stamping, and patterning of a blanket film in order to minimize leakage and stray currents in a TFT device. The method of claim 1, Wherein the source and drain electrodes are made of a material selected from the group consisting of chromium, titanium, copper, aluminum, molybdenum, tungsten, nickel, gold, palladium, platinum, conductive polymers and combinations thereof. The method of claim 13, Any ohmic contact layer made of a material selected from the group consisting of gold, platinum, palladium, conductive polymers, oligomers, semi-conductive polymers and oligomers, and combinations thereof is provided between the source / drain electrodes and the semiconductor layer. Structure located at. The method of claim 13, Wherein the source and drain electrodes have a thickness of 30 nm to 500 nm. The method of claim 13, Wherein the source and drain electrodes are patterned by a method selected from the group consisting of deposition through a shadow mask and a lithographic patterning technique. The method of claim 2, Wherein said passivation layer is a polymer selected from the group consisting of polyimide, parylene, and undoped polyaniline. The method of claim 1, The structure wherein the metal oxide gate insulator is made from a precursor comprising a metal alkoxyalkoxide moiety, in particular a metal butoxyethoxide. The method of claim 1, The structure wherein the metal oxide gate insulator is made from a precursor comprising a metal alkoxide moiety, in particular a metal isopropoxide.