KR100302330B1 - A device of suppling frame pulse of counter - Google Patents

Abstract

The present invention relates to a counter for generating a required signal in synchronization with a frame pulse signal applied from a system, wherein the counter is operated at a stable timing period by detecting a clock error of the frame pulse signal. When the timing or period of the frame pulse is unstable, it prevents a malfunction and when the period of the frame pulse is changed, the timing period of the counter is also changed. An AND gate for outputting, a counter for counting and outputting in synchronization with a signal applied from the AND gate, and an error or clock change of a frame pulse signal applied from a system by an output signal of the counter. It consists of a frame pulse error detector that outputs an error signal to the data, and operates the counter stably from a short-term frame pulse error. When the clock frequency of the frame pulse is changed, the counter is adjusted to the changed clock frequency. By synchronizing, there is an effect of stable signal processing and an industrial use effect of improving the reliability of the system.

Description

Frame pulse supply of counter {A DEVICE OF SUPPLING FRAME PULSE OF COUNTER}

The present invention is a counter that generates a required signal in synchronization with a frame pulse signal applied from a system, so that the counter operates at a stable timing period by detecting a clock error of the frame pulse signal. In particular, when the timing or cycle of the frame pulse applied from the system is unstable, a malfunction is prevented, and when the period of the frame pulse is changed, the timing period of the counter is also changed. will be.

In one system, as a reference for digital signal processing, a system clock, a frame clock, and the like are generated and transmitted to each functional unit, and each functional unit configured as a separate board (BD) performs its own necessary signal processing. Thereafter, in transmitting the processed data to another functional unit of another board BD, the data is transmitted in synchronization with a reference system clock or frame pulse applied from the system.

However, the system clock may become unstable due to the minute specification error of many electronic components used in the system and the interference between various signals, and as described above, the data signal processing between the boards BD of the system may be unstable. If the system clock, which is a synchronous reference, is unstable, an error occurs in the whole system, and the reliability of the system is deteriorated by the data processing result of the unstable system.

Hereinafter, a counter operated by a frame pulse of the prior art will be described with reference to the accompanying drawings.

1 is a functional block diagram of a counter according to an embodiment of the prior art, and FIG. 2 is a signal timing diagram of a 6480 counter according to an embodiment of the prior art.

Referring to the counter according to the prior art with reference to the accompanying drawings, a frame pulse applied from the system is input, the value is synchronized to the frame pulse (Synchronous) in one embodiment, the value counted to 6480 binary It consists of a counter (Counter) 10 for outputting.

2 shows a normal frame pulse when the frame pulse inputted to the counter 10 is the same as the period of the first frame pulse inputted, an abnormal frame pulse inputted as fast as one clock cycle, and one clock cycle. The states of the counter output Q outputted from the counter by the abnormal frame pulse inputted later are respectively shown.

As described above, the detailed operation and operation of the counter according to one embodiment of the prior art are synchronized by a frame pulse inputted normally and stably from the system, and as an embodiment, The count output signal 'Q' of the 6480 binary counter 10 that counts and outputs from '0' to '6479' is synchronized with an applied frame pulse as shown in FIG. 2. The output Q of the counter 10 is restarted.

In this case, as shown in FIG. 2 attached to the above, when the frame pulse applied from the system is input as an error occurs one clock faster than the normal clock cycle, the counter 10 is input. After counting up to '6479' but not counting up to '6478', a new counted signal from '0' is output (Q) in synchronization with the frame pulse.

In addition, as shown in FIG. 2 attached to the above, when the frame pulse applied from the system is an embodiment of the clock than the normal clock cycle, when an error is generated and delayed one clock delay (Delay) input, the counter 10 outputs a signal of counting '6479' and counting '0' twice.

Therefore, there is a problem that the output Q of the counter 10 fluctuates even by minute clock fluctuation of the frame pulse signal applied from the system, and the result of the data processed by the system is also very unstable. There was a problem that the reliability is lowered.

The present invention detects a clock error of a frame pulse applied from the system so that the instantaneous clock error does not affect the counter, and if there is a clock variation following the frame pulse, the output signal of the counter is recalled. It is an object of the present invention to provide an apparatus for synchronizing and outputting a clock signal of a changed frame pulse.

In order to achieve the above object, the present invention provides an AND gate for receiving an frame signal signal from the system and performing an AND operation with an error signal, and a counter for counting and outputting in synchronization with the signal received from the AND gate. And a frame pulse supply device configured to detect an error or clock change of a frame pulse signal applied from a system by an output signal of the counter and output a frame pulse error detector to the AND gate as an error signal. .

1 is a functional block diagram of a counter according to an embodiment of the prior art,

2 is a signal timing diagram of a counter according to an embodiment of the prior art,

3 is a functional block diagram of a frame pulse supply apparatus of a counter according to an embodiment of the present invention;

4 is a detailed functional block diagram of a frame pulse error detector according to an embodiment of the present invention;

5 is a signal timing diagram for detecting a frame pulse error according to an embodiment of the present invention;

6 is a signal timing diagram when the frame pulse clock is changed according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10 counter 20 end gate

30: frame pulse error detector 32: decoder

34,35,36: the preflop 38: NOR gate

Hereinafter, a frame pulse supply apparatus of a counter according to the present invention will be described with reference to the accompanying drawings.

3 is a functional block diagram of a frame pulse supply apparatus of a counter according to an embodiment of the present invention, FIG. 4 is a detailed functional block diagram of a frame pulse error detector according to an embodiment of the present invention, and FIG. 6 is a signal timing diagram for detecting a frame pulse error, and FIG. 6 is a signal timing diagram when a frame pulse clock is changed according to an embodiment of the present invention.

Referring to the accompanying drawings as described above, the frame pulse supply apparatus of the counter according to the present invention is output from a frame pulse signal (Frame Pulse) signal, which is a standard of system operation from the system, and a frame pulse error detector 30 to be described later. An AND gate 20 for receiving an error signal, and performing AND calculation and outputting an AND signal,

A counter 10 that counts and outputs in synchronization with the signal received from the AND gate 20;

A decoder (32) for outputting an enable signal by a last count output signal applied from the counter (10); A first de-flop (34) for receiving a enable signal from the decoder (32) and outputting a frame pulse signal applied from a system; A second de-preflop (D-FF) for receiving an enable signal from the decoder 32 and outputting a signal applied from the first de-flop (D-FF) 34 ( 35); A third de-preflop (D-FF) 36 which receives an enable signal from the decoder 32 and outputs a signal applied from the second de-preflop (D-FF) 35; And a NOR gate 38 that receives the output signals of the first to third de-flops (D-FF) (34, 35, 36), and outputs an OR operation. The output signal of (10) is fed back, and the signal obtained as a result of detecting an error or clock change of a frame pulse signal applied from a system is inputted to the AND gate 20. ) Is composed of a frame pulse error detector 30 which outputs as an error signal.

Hereinafter, with reference to the accompanying drawings, the configuration as described above of the present invention will be described in detail.

When the synchronous signal is input, the counter 10 starts a new count according to the synchronous signal. In the configuration of the present invention as described above, the output signal of the AND gate 20 is a synchronous signal. In addition, the counter 10 uses a 6480-degree counter which repeatedly counts from '0' to '6479' as an embodiment.

The decoder 32 of the frame pulse error detector 30, which is fed back with the output signal of the counter 10, is applied in response to the 6479 th pulse signal among the output signals of the counter 10. One signal is output as an enable signal and applied to the enable terminals EN of the first to third D-FFs 34, 35, and 36, respectively.

The first D-FF 34 of the frame pulse error detector 30, which receives a frame pulse signal used as a reference signal from the system as an input signal, to the data input terminal D, is the decoder 32. The output signal Q is output according to the enable signal that is an output signal of.

The output signal Q of the first D-FF 34 is applied to one input terminal of the NOR gate 38 and is applied to the input data terminal D of the second D-FF 35.

Only when the second D-FF 35 also receives an enable signal from the decoder 32, the signal applied to the input terminal D is output to the output terminal Q, and the output is performed. The signal is applied to the NOR gate 38 and the input terminal D of the third D-FF, and the third D-FF 36 also receives an enable signal from the decoder 32. Only in this case, the signal applied to the input terminal D is applied to the input terminal of the NOR gate 38 through the output terminal Q.

The above operation will be described in more detail with reference to the timing chart of FIG. 5.

A frame pulse signal, which is a synchronous reference signal applied from the system, is applied to the AND gate 20 and the first D-FF 34 at a normal clock cycle, and is applied to the output signal of the counter 10. By outputting the enable signal of the high state by the 6479th count signal by the decoder 32, the output signal of the first to third D-FF are all high signal The NOR gate 38 outputs a signal in a low state to one end of the AND gate 20 as an error signal.

Therefore, the AND gate 20 does not output a frame pulse signal applied from the system, and thus, the counter 10 continuously performs counting operation without being re-synchronous.

As an example, a case in which an abnormal frame pulse signal is applied from the system will be described with reference to the timing diagram shown on the right side of FIG.

An abnormal frame pulse signal is applied to the first D-FF 34 one clock early, and an enable signal is normally supplied from the decoder 32 to the enable terminal of the first D-FF 34. EN).

Since the frame pulse is not applied when the enable signal is applied, the output of the first D-FF 34 is in a low state so that the second D-FF 35 and the NOR gate ( Apply to the input of 38).

Since the NOR gate 38 receives a signal of a high state from the second D-FF 35 and the third D-FF 36, an error signal as an output is a low state. Since it is applied to one side end of the AND gate 20, the abnormal frame pulse that is applied one clock early can not be applied to the counter 10.

In addition, even if a frame pulse is applied from the system one clock later, the above process is repeated. As a result, the counter 10 does not receive an abnormal frame pulse and is not synchronized, thereby generating a normal counter output (Q). .

As another embodiment, the case where the clock of the frame pulse applied from the system is changed will be described in detail with reference to FIG.

When the clock of a frame pulse applied from the system is normally output one clock fast, the AND gate 20 receiving the frame pulse receives a low signal from the NOR gate 38 to generate an output. The first D-FF 34 maintains the output low due to the enable signal of the decoder 34 and enables the next cycle of the decoder 32. The second D-FF 35 that receives the low state signal of the first D-FF 34 also outputs a low state signal by the enable signal. The third D-FF 36 also receives a low state signal of the second D-FF 35 according to a next cycle enable signal of the decoder 32. Since the signal of the state is output, all of the NOR gates 38 receive a low state signal, and eventually, Hi By applying the gh) signal to the AND gate 20, a frame pulse signal delayed by one clock period applied to the input of the other side of the AND gate 20 is output to the counter 10.

Accordingly, the counter 10 is synchronized with a frame pulse having a late one clock cycle to generate a count output Q.

As described above, the decoder 32 outputs an enable signal by the signal of the synchronized counter 10, and the first D-FF 34 receives the high (high) of the applied frame pulse. High) state is output.

In the state before receiving the high state signal from the first D-FF 34, the NOR gate 38 continuously applies a high state signal to the AND gate 20 so that the counter ( 10 is once again synchronized to the frame pulse.

At this time, the NOR gate 38 receiving the high output signal from the first D-FF applies the low output to the AND gate 20, and the counter is further Generates counter output (Q) stably without synchronous.

As the next cycle of the frame pulse is repeated, the second D-FF 35 and the third D-FF 36 sequentially generate high-state output, and then, the frame pulse. The counter 10 maintains stable operation by the frame pulse error detector 30 even when an error such as slight clock variation occurs.

Accordingly, the present invention having the above configuration allows the output of the counter 10 to operate stably without being synchronized when there is a slight variation in the clock frequency of the frame pulse applied from the system, and the clock frequency of the frame pulse is continuous. In case of fluctuation, the counter 10 is synchronized with a clock of a new frame pulse to generate an output Q.

The technique of the present invention as described above uses the AND gate and the frame pulse error detector to operate the counter stably from short-term frame pulse errors, and to counter the changed clock frequency when the clock frequency of the frame pulse is changed. By synchronizing, there is an effect of stable signal processing and an industrial use effect of improving the reliability of the system.

Claims (2)

An AND gate receiving a frame pulse signal from the system and performing an AND operation on the error signal and outputting the same; A counter for counting and outputting in synchronization with the signal received from the AND gate; And a frame pulse error detector which detects an error or clock change of a frame pulse signal applied from the system by the output signal of the counter and outputs the error signal to the AND gate as an error signal. According to claim 1, The frame pulse error detector includes: a decoder configured to output an enable signal according to a last count signal applied from the counter; A first depreflop receiving an enable signal from the decoder and outputting a frame pulse signal applied from a system; A second depreflop receiving an enable signal from the decoder and outputting a signal applied from the first depreflop; A third depreflop receiving an enable signal from the decoder and outputting a signal applied from the second depreflop; And a NOR gate configured to receive and output an output signal of the first to third de-preflops to output an output signal.