JPH06125247A - Input pulse control circuit - Google Patents

Abstract

PURPOSE:To always supply a clock pulse signal of the constant pulse width to a counter and to prevent the malfunctions of the counter by providing an inverting delay circuit and a flip-flop. CONSTITUTION:A flip-flop 2 latches an enable signal EN, and a clock pulse signal CLK supplied from a terminal 7 is delayed and inverted by an inverting delay circuit 1. The signal EN is latched at an L level of the delayed signal CLK. Therefore the signal CLK which is controlled by the signal EN and always has the fixed pulse width can be supplied to an counter 4 as long as an AND is secured between the signal CLK supplied from the terminal 7 and the output signal of the flip-flop 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input pulse control circuit, and more particularly to an input pulse control circuit for controlling an input pulse signal to a counter or the like.

[0002]

2. Description of the Related Art In a conventional input pulse control circuit, as shown in FIG. 3, an AND element 5 receives a clock pulse signal CLK input from a terminal 7 and an enable signal EN input from a terminal 8. The ANDed signal is output. This output signal is input to the clock input terminal C of the counter. FIG. 4 is a timing chart of the above-mentioned input pulse control circuit, in which the clock pulse signal is supplied to the clock input terminal C of the counter 6 only during the time period when the enable signal EN is at the H level. Here, when the timings of the enable signal and the clock signal do not match, the time widths T1 and T2 of the output of the AND element 5 in FIG. 4 sometimes become narrower than the pulse width of the regular clock.

[0003]

In this conventional input pulse control circuit, since the clock pulse signal is always supplied to the counter when the enable signal input is at the H level, it is supplied to the counter depending on the positional relationship between the enable signal and the clock pulse signal. The pulse width of the generated clock signal may become short (T1 and T2 in FIG. 4). Therefore, the counter may or may not operate at the time when the clock pulse width changes, which causes a malfunction.

[0004]

An input pulse control circuit according to the present invention delays and inverts a pulse signal supplied to a logic element, and an enable signal for controlling the pulse signal output from the inversion delay circuit. It has a flip-flop that latches at the rising edge of a signal, and a logic element that ANDs with the pulse signal and the output signal of the flip-flop.

[0005]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart explaining the operation of this embodiment.
In the embodiment of FIG. 1, the clock signal CL input from the terminal 7 is used.
It is composed of an inverting delay circuit 1 for inverting and delaying K, a flip-flop 2, and an AND element 3. In the basic operation of this embodiment, the clock signal CLK is input to the counter 4 only when the enable signal EN is "H".

Next, the operation of this embodiment will be described with reference to FIG. FIG. 2 is a timing chart showing the operation in the circuit, where H is H level and L is L level. The flip-flop 2 latches the enable signal EN. On the other hand, the clock pulse signal is a signal obtained by delaying and inverting the clock pulse signal CLK from the terminal 7 by the inverting delay circuit 1. The enable signal EN is latched at the L level portion of the delayed clock pulse signal. Therefore, by ANDing the clock pulse signal input from the terminal 7 and the output signal of the flip-flop 2, the clock pulse signal controlled by the enable signal and having a constant pulse width can be supplied to the counter 4.

[0007]

As described above, according to the present invention, by providing the inverting delay circuit and the flip-flop, it is possible to always supply the clock pulse signal having a constant pulse width to the counter. The effect is that it can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of this embodiment.

FIG. 3 is a block diagram of a conventional input pulse control circuit.

FIG. 4 is a timing chart showing the operation of a conventional input pulse control circuit.

[Explanation of symbols]

 1 inversion delay circuit 2 flip-flop 3 AND element 4 counter 5 AND element 6 counter 7, 8 terminal EN enable signal input terminal CLK clock pulse signal input terminal C counter clock signal input

Claims (2)

[Claims] 1. An inverting delay circuit for delaying and inverting a pulse signal supplied to a logic element, a flip-flop for latching an enable signal for controlling the pulse signal at a rising edge of an output signal of the inverting delay circuit, and the pulse. An input pulse control circuit having a signal and an output signal of a flip-flop and a logical element that performs AND. 2. The delay amount of the inverting delay circuit is set so that the “H” level of the enable signal, which is the output of the flip-flop, rises during the “L” level of the delayed pulse signal. The input pulse control circuit according to claim 1.