JPH03153118A - Input circuit - Google Patents

Abstract

PURPOSE:To eliminate noise of a delay component from a delay circuit by retarding the output signal of a level conversion circuit with a delay circuit in an input circuit of a semiconductor integrated circuit, and taking OR and AND to apply waveform shaping with an SR latch. CONSTITUTION:An external signal supplied to an input terminal 10 is matched with a signal level of an internal circuit by a level conversion circuit 11 at first. When the pulse width of an output signal (a) of the conversion circuit 11 is shorter than the delay time T of the delay circuit 12 and its level is lower, the output signal (c) of an OR gate 13 inputted to a set input S of the SR latch 15 is fixed to a low level. Thus, the SR latch 15 is reset continuously and an output Q is fixed to a high level and an output XQ is fixed to a lower level. Thus, the pulse with shorter width of the delay time T of the delay circuit 12 is eliminated as noise and the pulse width of the noise desired to be eliminated is simply changed by varying the delay time T of the delay circuit 12.

Description

[Detailed description of the invention] [Industrial application field 1 The present invention relates to an input circuit for a semiconductor integrated circuit.

[Summary of the Invention 1] The present invention reduces noise by the amount of delay in the delay circuit by delaying the output signal of a level conversion circuit in the input circuit of a semiconductor integrated circuit using a delay circuit, performing logical sum and logical product, and shaping the waveform using an SR latch. The present invention provides an input circuit that eliminates the

[Prior Art] A conventional input circuit has an inverter structure as shown in Fig. 2, which outputs a low level signal when the input signal is high level.
The configuration was such that a high level signal was output when the input signal was low level.

[Problems to be Solved by the Invention] However, with the above-mentioned conventional technology, among the noise contained in the input signal, noise with a narrow pulse width disappears due to element delay in the input circuit or internal circuit, but noise with a wide pulse width disappears. The noise is
This problem cannot be eliminated by element delays in the input circuit or internal circuit, causing the internal circuit to malfunction. SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, an object of the present invention is to provide an input circuit that removes input signal noise that may cause internal circuits to malfunction.

[Failure to solve the problem 1 The input circuit of the present invention is as follows.

a) A 1-novel conversion circuit that receives No. 48 from the outside as an input signal.

1)) A delay circuit that uses the output signal of the level conversion circuit as an input signal, and an OR gate and AND gate that uses the output signal of the c l iii 1 novel conversion circuit and the output signal of the delay circuit as input signals. d) an SR clutch whose input signals are the output signals of the OR gate and the AND gate.

[Function 1] According to the above configuration of the present invention, when a high level noise is superimposed on a low level signal, the output of the AND gate remains at a low level, and a low level signal is added to a high level signal. When noise is present, the output of the OR gate (iii) remains at a high level, so the output of the latch (5) is not affected by noise and is fixed at a high or low level.

[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention. The input of the level conversion circuit 11 is connected to the input terminal 10, the input of the delay circuit 12 is connected to the output of the level conversion circuit 11, and the inputs of the OR gate 13 and the AND gate 1-14 are connected to the input terminal 10 of the level conversion circuit 11. output and the output of the delay circuit 12, and the set signal S of the SR latch 15 is connected to the output of the OR gate 13.
The reset 1-signal R is connected to the output of the AND gate 1
It is connected to the output of 4.

An external signal applied to the input terminal 10 is first adjusted by the level conversion circuit 11 to the No. 15 level of the internal circuit. The timing charts when the pulse width of the output signal a of the level conversion circuit 11 is short relative to the delay time T in the delay circuit 12 are shown in FIGS. 3 and 4, and the timing chart when the pulse width is similarly long is m-1. - are Figs. 5 and 6.

The operation of the circuit diagram of FIG. 1 will be explained below based on timing chart 1-.

8 in FIG. 3 is the output (; li) of the 1-novel conversion circuit 11, and is a high 1-novel pulse signal whose pulse width is shorter than the delay time TJ of the delay circuit 12. 1 in FIG. In the output signal of the circuit 12, the pulse signal is delayed by the delay time T of the delay circuit 12.
This is a waveform obtained by NORing signal a and signal S with the output signal of No. 3. d in FIG. 3 is the output signal of the AND gate 14, and is the waveform obtained by A N D of the signal a and the signal S. The pulse width of the signal d is shorter than the delay time T of the delay circuit 12. Therefore, it is fixed at a low level. C in FIG. 3 is the signal waveform of the output XQ of the SR clutch 5, and f in FIG. 3 is the signal waveform of the output Q of the SR clutch 5. SR clutch 5 is set manually S
The signal C input to the reset input H sets the clutch, but since the signal d input to the reset input H is fixed at a low level of 1, the reset is not applied.In other words, the SR clutch 5 is in a state where it is not set and the output is 0. is fixed at a low level, and the output xQ is fixed at a high level.

FIG. 4 shows the pulse width of the SR clutch 5, which is shorter than the delay time T of the Hr delay circuit 12, but whose timing (-, .
・Output signal C of logical sum game 1-13 with human input S
Since is fixed at a low level, the SR controller 15 enters the reset 1 state and is in a state where the output Q is fixed at a high level and the output XQ is fixed at a low level.

FIG. 5 is a timing chart when a high-level pulse signal whose pulse width is longer than the delay time of the delay circuit 12 is input. The output signal C of the 9-OR gate 13 is initially high at 17 bells, and the signal a It rises in synchronization with the falling edge of signal L. The output signal d of the AND gate 14 initially rises at a low level in synchronization with the rising edge of the signal A, and then falls in synchronization with the falling edge of the signal a. The pulse width of signal d is determined by delay circuit 1.
It is equal to the difference between the delay time T and the delay time T of 2. The SR clutch 5 is first set by the signal C, and the output Q becomes low, and a high level signal is not applied to high level, output XQ changes to low level, and signal C
When the signal rises, the setting is applied again, and the output Q becomes a low level and the output XQ becomes a high level. That is, the signal e of the output Q of the SR clutch 5 is equal to the output signal a of the level conversion circuit 11 in the same phase and delayed by the delay time T of the delay circuit 12, and the signal f of the output XQ of the SR clutch 5 is equal to the output signal a of the level conversion circuit 11. 11 and is equal to the output signal a delayed by the delay time T of the delay circuit 12 in the opposite phase.

FIG. 6 is a timing chart when a low-level pulse signal whose pulse width is longer than the delay time T of the delay circuit 12 is input. In this case as well, SR
The signal e of the output Q of the clutch 5 is equal to the output signal a of the level conversion circuit 11 in the same phase and delayed by the delay time T of the delay circuit 12, and the signal f of the output XQ of the SR clutch 5 is equal to the output signal a of the level conversion circuit 11. Delay circuit 1 with opposite phase to output signal a
2 delayed by a delay time T.

Therefore, in the embodiment shown in FIG. 1, when a pulse signal whose pulse width is longer than the delay time T of the delay circuit 12 is input, the signal is transmitted and output, and a pulse whose pulse width is shorter than the delay time T of the delay circuit 12 is transmitted. An input circuit that removes the signal and does not output it when a signal is input can be realized. That is, in the circuit of this embodiment, pulses having a width shorter than the delay time T of the delay circuit 12 can be removed as noise.
By changing the delay time T in step 2, the pulse width of the noise to be removed can be easily set.

[Effect of the Invention 1] As described above, according to the present invention, the output signal of a level conversion circuit whose input signal is an external signal and the output signal of a delay circuit whose input signal is an input signal of the level conversion circuit are NORed. The output signal of the level conversion circuit is input to the set terminal of the SR latch, the output signal of the level conversion circuit is input to the signal from the outside, and the output signal of the delay circuit is input to the output signal of the level conversion circuit. By inputting the ANDed signal to the reset terminal of the SR latch,
When a pulse signal whose pulse width is longer than the delay time T of the delay circuit is input from the outside, the signal is transmitted and output; when a pulse signal whose pulse width is shorter than the delay time T of the delay circuit is input from the outside. can realize an input circuit that removes the signal and does not output it. That is, pulses with a width shorter than the delay time T of the delay circuit can be removed as noise;
Furthermore, by changing the delay time T of the delay circuit, the pulse width of the noise to be removed can be easily set.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the input circuit of the present invention. FIG. 2 is a circuit diagram of a conventional input circuit. 3, FIG. 4, FIG. 5, and FIG. 6 are timing charts of the circuit of FIG. 1. 10...Input terminal 11...Level conversion circuit l2, l3, l4, l5, S, R, Q, XQ, 0 b, C'd, 0 f, delay circuit OR gate AND Gate SR latch SR latch set terminal SR latch reset terminal SR latch normal output terminal SR latch inverted output terminal Level conversion circuit output signal Delay circuit output signal OR gate output signal AND gate output signal SR Normal rotation output signal of latch SR latch inversion output signal or higher

Claims (1)

[Scope of Claims] a) a level conversion circuit that takes an external signal as an input signal; b) a delay circuit that takes an output signal of the level conversion circuit as an input signal; c) an output signal of the level conversion circuit. and (d) an SR latch whose input signals are the output signals of the OR gate and the AND gate. Characteristic input circuit.