JPS62100022A - Counter control circuit - Google Patents

Abstract

PURPOSE:To simplify the counter control circuit by stopping count tentatively only when a counter read request exists and restarting the count after a time required to read the count elapses. CONSTITUTION:When a counter read request exists, a counter read request signal is turned on for one system clock. Then a non-inverting output of a FF1 is turned on and an inverting output is turned off in the next system clock. Thus, a binary counter 2 executes no count and since an output of the FF1 is turned on, a read register 4 reads the count of the binary counter 2. That is, since the binary counter 2 stops the count by one system clock each when the counter read request exists, a count error is generated in a strict sense. So long as the titled circuit is not applied to a circuit requiring a frequent count read request, however, the accuracy sufficient practically is attained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a counter control circuit for an electronic computer.

[Conventional technology]

Various types of counters are used in electronic computers, and are usually implemented as binary counters that count up or down at certain intervals. The time interval for counting up or down takes various values depending on the purpose of use, but the system clock counter is an example of one with the shortest counting time interval.

When a counter value is required, the counter control circuit that has received the counter read request reads the counter value into a counter read register and outputs it to an external circuit.

A counter read register is provided separately from the counter.
The reason why the counter value is once read into the counter read register is to enable the counter value at the time of the counter read request to be output to the external circuit, regardless of the constantly changing counter.

[Problem that the invention seeks to solve]

However, due to circuit implementation constraints, it may not be possible to mount the counter and the counter read register close to each other. On the other hand, as electronic computers become faster, system clocks also tend to become faster, and when the counter value changes rapidly like the system clock counter mentioned above, the counter value cannot be changed within one counter clock. The problem arises that the read register cannot be read.

An object of the present invention is to provide a counter control circuit that solves these problems.

[Means for solving problems]

The counter control circuit of the present invention has means for stopping counting for a number of count clocks corresponding to the time required to read the counter value when a counter reading request is made.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a system clock counter control circuit which is an embodiment of the present invention, and shows flip-flops 1 and 2.
It consists of a binary counter 2, an update logic circuit 3 for controlling this binary counter, and a read register 4. The non-inverting output terminal 5 of the flip-flop 1 is connected to the control input terminal 7 of the read register 4, and the inverting output terminal 6 is connected to one input terminal of each control AND gate 8 of the binary counter 2. The other input terminal of each AND gate 8 is connected to each output terminal 9 of update logic circuit 3, and each output terminal 10 of binary counter 2 is connected to each input terminal 11 of update logic circuit 3 and each input terminal of readout register 4. They are connected to terminals 12, respectively. Note that the counter reading request signal is input to the flip-flop 1.

Next, the operation of this embodiment will be explained.

When there is no counter read request, the counter read request signal is off, the non-inverted output of the flip-flop 1 is off, and the inverted output is on. At this time, the binary counter 2 counts the system clock under the control of the update logic circuit 3.

Also, since the non-inverting output of the flip-flop 1 is off, the read register 4 retains the previously read counter value.

If there is a counter read request, the counter read request signal is on for one system clock. Then, at the next system clock, the non-inverted output of flip-flop 1 is turned on and the -inverted output is turned off. At this time, since the inverted output of flip-flop 1 is turned off, 2
The digit counter 2 does not count, and the read register 4 has the output of the flip-flop 1 turned on, so
Read the value of binary counter 2.

At the next system clock, the counter read request signal is already off, the non-inverted output of flip-flop 1 is turned off, and the inverted output is turned on. Therefore, the binary counter 2 restarts counting, and the read register 4 retains the counter value at the time of the previous counter read request.

As can be seen from the above explanation, the binary counter 2 stops counting for one system clock every time there is a counter reading request, so in a strict sense, a counting error occurs. However, it is possible to maintain sufficient accuracy for practical use as long as it is not applicable to a circuit where counter reading requests are frequently issued.

In this embodiment, for simplicity, an example is given in which the read request pulse is equivalent to one system clock, but in order to stop counting for multiple system clocks, the counter read request signal is made into a pulse equivalent to multiple system clocks, and this pulse This can be easily realized by sampling the output of the binary counter 2 into the readout register 4 using the trailing edge differential pulse.

Further, although the above embodiment has been described using a system clock counter as an example, it is obvious that the present invention can also be applied to other counters such as an instruction execution number counter, a timer counter, etc.

〔Effect of the invention〕

As explained above, the present invention temporarily stops counting only when there is a request to read the counter, and resumes counting after the time required to read the counter value has passed. This has the advantage that a simple counter control circuit can be constructed while maintaining accuracy.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1...Flip-flop 2...Binary counter 3...Update logic circuit 4...Read register 8...AND gate

Claims (1)

[Claims] (1) A counter control circuit characterized by having means for stopping counting for a number of count clocks corresponding to the time required to read a counter value when a counter reading request is made.