KR100192966B1 - Mos control diode and manufacturing method thereof - Google Patents

Abstract

A MOS control with one or two electrode terminals that can compensate for the large leakage current characteristics of Schottky diodes by minimizing the generation of large reverse current at high temperature, which is a disadvantage of conventional Schottky diodes, while being a multi-carrier device capable of high-speed switching. Disclosed are a diode and a method of manufacturing the same. In order to achieve this, in the present invention, a gate electrode having a structure in which a gate oxide film is formed at both edges of the front surface of the first conductive silicon substrate so that the bottom center portion is in direct contact with the substrate is formed. A base well of a second conductivity type is formed in the substrate, a source well is formed in the base well, an insulating film is formed along the entire surface of the gate electrode, and the front of the substrate on which the resultant is formed. On the surface, a MOS control diode having a structure in which a first metal electrode is formed to contact the source well and a second metal electrode is formed on a back surface of the silicon substrate is provided. In this case, the source electrode terminal is connected to the first metal electrode, and the drain electrode terminal is connected to the second metal electrode.

Description

MOS control diode and its manufacturing method

The present invention relates to a high-speed switching diode, and more particularly, a multi-carrier device having a high-speed switching characteristics without a separate life time control process, the switching operation is very fast and the reverse current is very small, the large leakage current characteristics of the Schottky diode The present invention relates to a MOS control diode having two complementary terminals and a method of manufacturing the same.

Recently, with the progress of high performance and advanced electronic devices, switching power sources capable of high efficiency and miniaturization are increasing, and these power stages require diodes with low switching losses. In order to meet such demands, conventionally, a diode having a PN junction structure is doped with a life time killer such as gold (Au) or platinum (Pt), or particle irradiation such as electron beams or gamma rays. Although high-speed switching is implemented as a method of making a recombination center in low silicon, the process is difficult and expensive, and has a disadvantage of serious voltage drop and reverse leakage current.

In addition, a conventional Schottky barrier using a schottky barrier is a multiple carrier device having three terminals (eg, a gate terminal, a source terminal, and a drain terminal), and has a separate life time because there is no accumulation effect of minority carriers. High-speed switching operation is possible without the control process, but its reverse voltage is low and the reverse current is large at high temperatures.

Accordingly, an object of the present invention is to provide a MOS control diode designed as a multi-carrier element as well as capable of high-speed switching as well as having a very low reverse current at high temperature.

Another object of the present invention is to provide a manufacturing method that can effectively manufacture the MOS control diode of the above structure.

1A to 1D are process flowcharts showing a method of manufacturing a MOS control diode having two terminals according to the present invention.

FIG. 2 shows electron flow and depletion layer diffusion patterns when negative and negative voltages are applied to the source electrode and the drain electrode when the diode formed as a result of the process of FIGS. 1a to 1d has the NPN structure. Shown cross section.

3 is a cross-sectional view of the state where the depletion layers have reached pinch-off contacting each other when the applied voltage is further increased in the state of FIG.

4 is a depletion layer in which reverse bias is applied between a source well and a base well when a positive voltage and a negative voltage are applied to the source electrode terminal and the drain electrode terminal of the diode resulting from the process shown in FIGS. 1A to 1D, respectively. This cross-sectional view shows the state extending in both directions.

FIG. 5 is a characteristic diagram showing forward and reverse characteristics of a diode produced as a result of the process of FIGS. 1A to 1D.

* Explanation of symbols for main parts of the drawings

1 silicon substrate 2 gate oxide film

3: gate electrode 4: base well

5 source well 6 insulating film

7: first metal electrode 8: second metal electrode

9: depletion layer 10: source electrode terminal

11 drain electrode terminal 12 electron flow line

In order to achieve the above object, in the present invention, a gate electrode is formed on the front surface of the first conductive silicon substrate, the gate electrode is provided on both edges thereof so that the bottom center portion is in direct contact with the substrate; A base well of a second conductivity type formed in the substrate between the gate electrodes; A source well formed in said base well between said gate electrodes;

An insulating film surrounding the surface of the gate electrode; A first metal electrode formed on an entire surface of the front surface of the substrate on which the resultant is formed to be in contact with the source well; And a second metal electrode formed on the back surface of the silicon substrate to provide a MOS control diode configured to have two electrode terminals.

In order to achieve the above object, the present invention includes the steps of: forming a gate oxide film on the front surface of the substrate so that the surface of the first conductive silicon substrate is selectively exposed; Forming a gate electrode on the front surface of the substrate, the surface of which is exposed so as to partially overlap the gate oxide film; Ion implanting and diffusing a second conductive impurity onto the resultant to form a second well-type base well in the substrate between the gate electrodes; Implanting an ion of a first conductivity type impurity onto the resultant and then diffusing it to form a source well of the first conductivity type in the base well; Removing the gate oxide film between the gate electrodes; Forming an insulating film along the entire surface of the gate electrode; Forming a first metal electrode on a front surface of the front surface of the substrate on which the resultant is formed to be in contact with the source well; And forming a second metal electrode on the back surface of the substrate.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1A to 1D show a process flow diagram illustrating a method of manufacturing a MOS control diode having two electrode terminals presented in the present invention. Referring to this, the manufacturing method is divided into four steps.

As a first step, as shown in FIG. 1A, a gate oxide film 2 is formed on the front surface of the first conductive silicon substrate 1, and then a predetermined partial etching is performed to form a surface of the substrate 1. Expose a portion. A polysilicon gate electrode 3 is formed on the front surface of the substrate 1, the surface of which is exposed to overlap the gate oxide layer 2 with a predetermined portion.

As a second step, as shown in Fig. 1B, a second conductive type impurity is ion-implanted onto the resultant and then diffused to form a base of the second conductive type in the substrate 1 between the gate electrodes 3. The well 4 is formed.

As a third step, as shown in FIG. 1C, the first conductive type impurities are ion-implanted again onto the resultant and then diffused to form a first well type source well 5 inside the base well 4. Form.

As a fourth step, as shown in FIG. 1D, the gate oxide film 2 having the surface exposed between the gate electrodes 3 is removed, and then the gate electrodes 3 are insulated to insulate the two gate electrodes. An insulating film 6 is formed along the entire surface. Subsequently, a first metal electrode 7 is formed on the entire front surface of the substrate 1 on which the resultant is formed to contact the source well 5, and the second metal electrode is formed on the back surface of the substrate 1 again. By forming (8), this process progress is completed.

As a result, as shown in FIG. 1D, the front surface of the first conductive silicon substrate 1 has a structure in which gate oxide films 2 are provided on both edges thereof so that the bottom center portion thereof is in direct contact with the substrate 1. A gate electrode 3 is formed, and a second well-type base well 4 is formed in the substrate 1 between the gate electrodes 3, and a source well 3 is formed in the base well 4. 5) is formed, and an insulating film 6 is formed along the entire surface of the gate electrode 3, and the front surface of the substrate 1 on which the resultant is formed is in contact with the source well 5. The first metal electrode 7 is formed, and a MOS control diode having a structure in which the second metal electrode 8 is formed on the back surface of the silicon substrate 1 is formed. In this case, a source electrode terminal 10 is connected to the first metal electrode 7, and a drain electrode terminal 11 is connected to the second metal electrode 8.

Here, when the pentavalent impurity is used as the first conductivity type impurity, the trivalent impurity is used as the second conductivity type impurity, whereas when the trivalent impurity is used as the first conductivity type impurity, the pentavalent impurity is used as the second conductive impurity. Impurities are used.

Accordingly, the polysilicon constituting the gate electrode 3 may be doped with a pentavalent impurity, while the trivalent impurity may be doped depending on the process procedure in which the MOS control diode is manufactured.

FIG. 2 shows the source electrode terminal 10 and the drain when the source well 5 and the base well 4 and the substrate 1 used as the drain region of the diode resulting from the process shown in FIGS. 1A to 1D have an NPN structure. This is a cross-sectional view showing the flow of electrons and the depletion of electrons when a negative voltage is applied to the electrode terminal 11. Referring to the cross-sectional view, a positive voltage applied to the drain electrode terminal 11 As the channel is applied to the gate electrode 3 to the surface of the base well 4 through the gate oxide film 2, the electron flow is caused by the potential difference between the electrode terminals 10 and 11. have.

3 is a cross-sectional view illustrating a state in which the depletion layers reach a pinch off contacting each other when the applied voltage is further increased in the state of FIG. 2. Referring to the cross-sectional view, the depletion layer is extended toward the silicon substrate 1. When the pinch-off state reaches each other, it can be seen that the current does not increase any more and is saturated.

FIG. 4 shows the source well 5 and the base well when the source electrode terminal 10 and the drain electrode terminal 11 of the diode produced as a result of the process shown in FIGS. 1A to 1D are respectively applied with positive and negative voltages. 4) A cross-sectional view showing a state in which the depletion layer 9 extends in both directions with reverse bias applied therebetween.

FIG. 5 is a characteristic diagram showing the forward and reverse characteristics of the diode resulting from the process of FIGS. 1A to 1D. Referring to the drawing, when a forward voltage is applied, a current flows through a channel, and at a higher voltage, a pinch-off occurs. It can be seen that is no longer increased, and when the opposite voltage is applied, the channel is blocked and turned off. At this time, a reverse voltage is applied between the source well 5 and the base well 4 and the fast switching diode 9 extends to both sides.

As described above, according to the present invention, it is possible to minimize the generation of reverse current at a high temperature, which is a disadvantage of the conventional Schottky diode, while being a multi-carrier device capable of high-speed switching, thereby compensating for the large leakage current characteristic of the Schottky diode. Thus, the reliability of the MOS control diode can be achieved.

Claims (12)

A gate electrode formed on the front surface of the first conductive silicon substrate and provided with gate oxide films on both edges thereof so that the bottom center portion thereof is in direct contact with the substrate; A source well formed in a base well of a second conductivity type formed in the substrate between the gate electrodes; An insulating film surrounding the surface of the gate electrode; A first metal electrode formed on an entire surface of the front surface of the substrate on which the resultant is formed to be in contact with the source well; And a second metal electrode formed on the back surface of the silicon substrate, wherein the MOS control diode is configured to have two electrode terminals. The MOS control diode of claim 1, wherein the first conductive type is a pentavalent impurity, and the second conductive type is a trivalent impurity. The MOS control diode of claim 1, wherein the first conductivity type is a trivalent impurity, and the second conductivity type is a valent impurity. The MOS control diode of claim 1, wherein the gate electrode is made of polysilicon. The MOS control diode of claim 4, wherein the polysilicon is doped with pentavalent impurities. 5. The MOS control diode of claim 4, wherein the polysilicon is doped with trivalent impurities. Forming a gate oxide film on the front surface of the substrate such that the surface of the first conductive silicon substrate is selectively exposed to a predetermined portion; Forming a gate electrode on the front surface of the substrate, the surface of which is exposed so as to partially overlap the gate oxide film; Implanting and diffusing a second conductive impurity onto the resultant to form a second well-type base well in the substrate between the gate electrodes; Implanting an ion of a first conductivity type impurity onto the resultant and then diffusing it to form a source well of the first conductivity type in the base well; Removing the gate oxide film between the gate electrodes; Forming an insulating film along the entire surface of the gate electrode; Forming a first metal electrode on a front surface of the front surface of the substrate on which the resultant is formed to be in contact with the source well; And forming a second metal electrode on the back surface of the substrate. 8. The method of claim 7, wherein a pentavalent impurity is used as the first conductive type and a trivalent impurity is used as the second conductive type. 8. The method of claim 7, wherein trivalent impurities are used as the first conductive type and pentavalent impurities are used as the second conductive type. The method of claim 7, wherein the gate electrode is formed of polysilicon. The method of claim 10, wherein the polysilicon is doped with pentavalent impurities. The method of claim 10, wherein the polysilicon is doped with trivalent impurities.